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[24.150.219.207]) by smtp.gmail.com with ESMTPSA id o11-20020a0ce40b000000b00699437d4dfbsm3828996qvl.72.2024.04.09.10.41.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Apr 2024 10:41:29 -0700 (PDT) From: Trevor Gamblin To: linux-pwm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, u.kleine-koenig@pengutronix.de, michael.hennerich@analog.com, nuno.sa@analog.com, tgamblin@baylibre.com, dlechner@baylibre.com Subject: [PATCH 2/2 v2] pwm: axi-pwmgen: add duty offset support Date: Tue, 9 Apr 2024 13:41:26 -0400 Message-ID: <20240409174126.1296318-3-tgamblin@baylibre.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240409174126.1296318-1-tgamblin@baylibre.com> References: <20240409174126.1296318-1-tgamblin@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable duty_offset feature now that it is supported in the pwm subsystem. Related macros and struct fields related to duty_offset are renamed to be consistent. Signed-off-by: Trevor Gamblin --- v2 changes: * Address feedback for driver in v1: * Remove line setting supports_offset flag in pwm_chip, since that has been removed from the struct in core.c. --- drivers/pwm/pwm-axi-pwmgen.c | 34 ++++++++++++++++++++++++++-------- 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/drivers/pwm/pwm-axi-pwmgen.c b/drivers/pwm/pwm-axi-pwmgen.c index 539625c404ac..25a083003432 100644 --- a/drivers/pwm/pwm-axi-pwmgen.c +++ b/drivers/pwm/pwm-axi-pwmgen.c @@ -6,9 +6,9 @@ * Copyright 2024 Baylibre SAS * * Limitations: - * - The writes to registers for period and duty are shadowed until - * LOAD_CONFIG is written to AXI_PWMGEN_REG_CONFIG at the end of the - * current period. + * - The writes to registers for period, duty, and duty_offset are + * shadowed until LOAD_CONFIG is written to AXI_PWMGEN_REG_CONFIG at + * the end of the current period. * - Writing LOAD_CONFIG also has the effect of re-synchronizing all * enabled channels, which could cause glitching on other channels. It * is therefore expected that channels are assigned harmonic periods @@ -34,7 +34,7 @@ #define AXI_PWMGEN_REG_NPWM 0x14 #define AXI_PWMGEN_CHX_PERIOD(v, ch) ((v)->period_base + (v)->ch_step * (c= h)) #define AXI_PWMGEN_CHX_DUTY(v, ch) ((v)->duty_base + (v)->ch_step * (ch)) -#define AXI_PWMGEN_CHX_OFFSET(v, ch) ((v)->offset_base + (v)->ch_step * (c= h)) +#define AXI_PWMGEN_CHX_DUTY_OFFSET(v, ch) ((v)->duty_offset_base + (v)->ch= _step * (ch)) #define AXI_PWMGEN_REG_CORE_MAGIC_VAL 0x601A3471 /* Identification number = to test during setup */ #define AXI_PWMGEN_LOAD_CONFIG BIT(1) #define AXI_PWMGEN_RESET BIT(0) @@ -42,7 +42,7 @@ struct axi_pwm_variant { u8 period_base; u8 duty_base; - u8 offset_base; + u8 duty_offset_base; u8 major_version; u8 ch_step; }; @@ -62,7 +62,7 @@ static const struct regmap_config axi_pwmgen_regmap_confi= g =3D { static const struct axi_pwm_variant pwmgen_1_00_variant =3D { .period_base =3D 0x40, .duty_base =3D 0x44, - .offset_base =3D 0x48, + .duty_offset_base =3D 0x48, .major_version =3D 1, .ch_step =3D 12, }; @@ -70,7 +70,7 @@ static const struct axi_pwm_variant pwmgen_1_00_variant = =3D { static const struct axi_pwm_variant pwmgen_2_00_variant =3D { .period_base =3D 0x40, .duty_base =3D 0x80, - .offset_base =3D 0xC0, + .duty_offset_base =3D 0xC0, .major_version =3D 2, .ch_step =3D 4, }; @@ -83,7 +83,7 @@ static int axi_pwmgen_apply(struct pwm_chip *chip, struct= pwm_device *pwm, unsigned int ch =3D pwm->hwpwm; struct regmap *regmap =3D ddata->regmap; const struct axi_pwm_variant *variant =3D ddata->variant; - u64 period_cnt, duty_cnt; + u64 period_cnt, duty_cnt, duty_offset_cnt; int ret; =20 if (state->polarity !=3D PWM_POLARITY_NORMAL) @@ -108,6 +108,14 @@ static int axi_pwmgen_apply(struct pwm_chip *chip, str= uct pwm_device *pwm, ret =3D regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(variant, ch), duty_cnt); if (ret) return ret; + + duty_offset_cnt =3D mul_u64_u64_div_u64(state->duty_offset, ddata->clk_r= ate_hz, NSEC_PER_SEC); + if (duty_offset_cnt > UINT_MAX) + duty_offset_cnt =3D UINT_MAX; + + ret =3D regmap_write(regmap, AXI_PWMGEN_CHX_DUTY_OFFSET(variant, ch), du= ty_offset_cnt); + if (ret) + return ret; } else { ret =3D regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(variant, ch), 0); if (ret) @@ -116,6 +124,10 @@ static int axi_pwmgen_apply(struct pwm_chip *chip, str= uct pwm_device *pwm, ret =3D regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(variant, ch), 0); if (ret) return ret; + + ret =3D regmap_write(regmap, AXI_PWMGEN_CHX_DUTY_OFFSET(variant, ch), 0); + if (ret) + return ret; } =20 return regmap_write(regmap, AXI_PWMGEN_REG_CONFIG, AXI_PWMGEN_LOAD_CONFIG= ); @@ -145,6 +157,12 @@ static int axi_pwmgen_get_state(struct pwm_chip *chip,= struct pwm_device *pwm, =20 state->duty_cycle =3D DIV_ROUND_UP_ULL((u64)cnt * NSEC_PER_SEC, ddata->cl= k_rate_hz); =20 + ret =3D regmap_read(regmap, AXI_PWMGEN_CHX_DUTY_OFFSET(variant, ch), &cnt= ); + if (ret) + return ret; + + state->duty_offset =3D DIV_ROUND_UP_ULL((u64)cnt * NSEC_PER_SEC, ddata->c= lk_rate_hz); + state->polarity =3D PWM_POLARITY_NORMAL; =20 return 0; --=20 2.44.0