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[24.150.219.207]) by smtp.gmail.com with ESMTPSA id o11-20020a0ce40b000000b00699437d4dfbsm3828996qvl.72.2024.04.09.10.41.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Apr 2024 10:41:28 -0700 (PDT) From: Trevor Gamblin To: linux-pwm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, u.kleine-koenig@pengutronix.de, michael.hennerich@analog.com, nuno.sa@analog.com, tgamblin@baylibre.com, dlechner@baylibre.com Subject: [PATCH 1/2 v2] pwm: add duty offset support Date: Tue, 9 Apr 2024 13:41:25 -0400 Message-ID: <20240409174126.1296318-2-tgamblin@baylibre.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240409174126.1296318-1-tgamblin@baylibre.com> References: <20240409174126.1296318-1-tgamblin@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some PWM chips support a "phase" or "duty_offset" feature. This patch continues adding support for configuring this property in the PWM subsystem. Functions duty_offset_show(), duty_offset_store(), and pwm_get_duty_offset() are added to match what exists for duty_cycle. Handle duty_offset in the new pwmchip char device logic. Add a check to disallow applying a state with both inversed polarity and a nonzero duty_offset. Also add duty_offset to TP_printk in include/trace/events/pwm.h so that it is reported with other properties when using the event tracing pipe for debug. Signed-off-by: Trevor Gamblin --- v2 changes: * Address feedback in v1: * Remove supports_offset flag in pwm_chip struct * Don't return EINVAL when state->duty_offset + state->duty_cycle > state->period in __pwm_apply(), since this is valid as long as neither is greater than state->period on its own * Add a check to disallow setting the PWM signal as inverse and a nonzero duty_offset at the same time in __pwm_apply(), with a comment explaining why --- drivers/pwm/core.c | 82 +++++++++++++++++++++++++++++++++++--- include/linux/pwm.h | 15 +++++++ include/trace/events/pwm.h | 6 ++- 3 files changed, 95 insertions(+), 8 deletions(-) diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c index 2745941a008b..0d12cce67be7 100644 --- a/drivers/pwm/core.c +++ b/drivers/pwm/core.c @@ -80,6 +80,7 @@ static void pwm_apply_debug(struct pwm_device *pwm, */ if (s1.enabled && s1.polarity !=3D state->polarity) { s2.polarity =3D state->polarity; + s2.duty_offset =3D s1.duty_cycle; s2.duty_cycle =3D s1.period - s1.duty_cycle; s2.period =3D s1.period; s2.enabled =3D s1.enabled; @@ -121,6 +122,23 @@ static void pwm_apply_debug(struct pwm_device *pwm, state->duty_cycle, state->period, s2.duty_cycle, s2.period); =20 + if (state->enabled && + last->polarity =3D=3D state->polarity && + last->period =3D=3D s2.period && + last->duty_offset > s2.duty_offset && + last->duty_offset <=3D state->duty_offset) + dev_warn(pwmchip_parent(chip), + ".apply didn't pick the best available duty offset (requested: %llu/%l= lu, applied: %llu/%llu, possible: %llu/%llu)\n", + state->duty_offset, state->period, + s2.duty_offset, s2.period, + last->duty_offset, last->period); + + if (state->enabled && state->duty_offset < s2.duty_offset) + dev_warn(pwmchip_parent(chip), + ".apply is supposed to round down duty_offset (requested: %llu/%llu, a= pplied: %llu/%llu)\n", + state->duty_offset, state->period, + s2.duty_offset, s2.period); + if (!state->enabled && s2.enabled && s2.duty_cycle > 0) dev_warn(pwmchip_parent(chip), "requested disabled, but yielded enabled with duty > 0\n"); @@ -144,12 +162,13 @@ static void pwm_apply_debug(struct pwm_device *pwm, if (s1.enabled !=3D last->enabled || s1.polarity !=3D last->polarity || (s1.enabled && s1.period !=3D last->period) || + (s1.enabled && s1.duty_offset !=3D last->duty_offset) || (s1.enabled && s1.duty_cycle !=3D last->duty_cycle)) { dev_err(pwmchip_parent(chip), - ".apply is not idempotent (ena=3D%d pol=3D%d %llu/%llu) -> (ena=3D%d po= l=3D%d %llu/%llu)\n", + ".apply is not idempotent (ena=3D%d pol=3D%d %llu/%llu/%llu) -> (ena=3D= %d pol=3D%d %llu/%llu/%llu)\n", s1.enabled, s1.polarity, s1.duty_cycle, s1.period, - last->enabled, last->polarity, last->duty_cycle, - last->period); + s1.duty_offset, last->enabled, last->polarity, + last->duty_cycle, last->period, last->duty_offset); } } =20 @@ -164,13 +183,24 @@ static int __pwm_apply(struct pwm_device *pwm, const = struct pwm_state *state) int err; =20 if (!pwm || !state || !state->period || - state->duty_cycle > state->period) + state->duty_cycle > state->period || + state->duty_offset > state->period) return -EINVAL; =20 chip =3D pwm->chip; =20 + /*=20 + * There is no need to set duty_offset with inverse polarity, + * since signals with duty_offset values greater than 0.5 * + * period can equivalently be represented by an inverted signal + * without offset. + */ + if (state->polarity =3D=3D PWM_POLARITY_INVERSED && state->duty_offset) + return -EINVAL; + if (state->period =3D=3D pwm->state.period && state->duty_cycle =3D=3D pwm->state.duty_cycle && + state->duty_offset =3D=3D pwm->state.duty_offset && state->polarity =3D=3D pwm->state.polarity && state->enabled =3D=3D pwm->state.enabled && state->usage_power =3D=3D pwm->state.usage_power) @@ -292,10 +322,11 @@ int pwm_adjust_config(struct pwm_device *pwm) * been configured. * * In either case, we setup the new period and polarity, and assign a - * duty cycle of 0. + * duty cycle and offset of 0. */ if (!state.period) { state.duty_cycle =3D 0; + state.duty_offset =3D 0; state.period =3D pargs.period; state.polarity =3D pargs.polarity; =20 @@ -617,6 +648,41 @@ static ssize_t duty_cycle_store(struct device *pwm_dev, return ret ? : size; } =20 +static ssize_t duty_offset_show(struct device *pwm_dev, + struct device_attribute *attr, + char *buf) +{ + const struct pwm_device *pwm =3D pwm_from_dev(pwm_dev); + struct pwm_state state; + + pwm_get_state(pwm, &state); + + return sysfs_emit(buf, "%llu\n", state.duty_offset); +} + +static ssize_t duty_offset_store(struct device *pwm_dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct pwm_export *export =3D pwmexport_from_dev(pwm_dev); + struct pwm_device *pwm =3D export->pwm; + struct pwm_state state; + u64 val; + int ret; + + ret =3D kstrtou64(buf, 0, &val); + if (ret) + return ret; + + mutex_lock(&export->lock); + pwm_get_state(pwm, &state); + state.duty_offset =3D val; + ret =3D pwm_apply_might_sleep(pwm, &state); + mutex_unlock(&export->lock); + + return ret ? : size; +} + static ssize_t enable_show(struct device *pwm_dev, struct device_attribute *attr, char *buf) @@ -731,6 +797,7 @@ static ssize_t capture_show(struct device *pwm_dev, =20 static DEVICE_ATTR_RW(period); static DEVICE_ATTR_RW(duty_cycle); +static DEVICE_ATTR_RW(duty_offset); static DEVICE_ATTR_RW(enable); static DEVICE_ATTR_RW(polarity); static DEVICE_ATTR_RO(capture); @@ -738,6 +805,7 @@ static DEVICE_ATTR_RO(capture); static struct attribute *pwm_attrs[] =3D { &dev_attr_period.attr, &dev_attr_duty_cycle.attr, + &dev_attr_duty_offset.attr, &dev_attr_enable.attr, &dev_attr_polarity.attr, &dev_attr_capture.attr, @@ -1290,7 +1358,7 @@ static long pwm_cdev_ioctl(struct file *file, unsigne= d int cmd, unsigned long ar if (state.enabled) { cstate.period =3D state.period; if (state.polarity =3D=3D PWM_POLARITY_NORMAL) { - cstate.duty_offset =3D 0; + cstate.duty_offset =3D state.duty_offset; cstate.duty_cycle =3D state.duty_cycle; } else { cstate.duty_offset =3D state.duty_cycle; @@ -1356,6 +1424,7 @@ static long pwm_cdev_ioctl(struct file *file, unsigne= d int cmd, unsigned long ar state.period =3D cstate.period; state.polarity =3D PWM_POLARITY_NORMAL; state.duty_cycle =3D cstate.duty_cycle; + state.duty_offset =3D cstate.duty_offset; } else { state.enabled =3D false; } @@ -1991,6 +2060,7 @@ static void pwm_dbg_show(struct pwm_chip *chip, struc= t seq_file *s) =20 seq_printf(s, " period: %llu ns", state.period); seq_printf(s, " duty: %llu ns", state.duty_cycle); + seq_printf(s, " duty_offset: %llu ns", state.duty_offset); seq_printf(s, " polarity: %s", state.polarity ? "inverse" : "normal"); =20 diff --git a/include/linux/pwm.h b/include/linux/pwm.h index a58db7011807..5a93212c58eb 100644 --- a/include/linux/pwm.h +++ b/include/linux/pwm.h @@ -51,6 +51,7 @@ enum { * struct pwm_state - state of a PWM channel * @period: PWM period (in nanoseconds) * @duty_cycle: PWM duty cycle (in nanoseconds) + * @duty_offset: PWM duty offset (in nanoseconds) * @polarity: PWM polarity * @enabled: PWM enabled status * @usage_power: If set, the PWM driver is only required to maintain the p= ower @@ -61,6 +62,7 @@ enum { struct pwm_state { u64 period; u64 duty_cycle; + u64 duty_offset; enum pwm_polarity polarity; bool enabled; bool usage_power; @@ -130,6 +132,15 @@ static inline u64 pwm_get_duty_cycle(const struct pwm_= device *pwm) return state.duty_cycle; } =20 +static inline u64 pwm_get_duty_offset(const struct pwm_device *pwm) +{ + struct pwm_state state; + + pwm_get_state(pwm, &state); + + return state.duty_offset; +} + static inline enum pwm_polarity pwm_get_polarity(const struct pwm_device *= pwm) { struct pwm_state state; @@ -161,6 +172,9 @@ static inline void pwm_get_args(const struct pwm_device= *pwm, * ->duty_cycle value exceed the pwm_args->period one, which would trigger * an error if the user calls pwm_apply_might_sleep() without adjusting ->= duty_cycle * first. + * + * ->duty_offset is likewise set to zero to avoid inconsistent default + * states. */ static inline void pwm_init_state(const struct pwm_device *pwm, struct pwm_state *state) @@ -176,6 +190,7 @@ static inline void pwm_init_state(const struct pwm_devi= ce *pwm, state->period =3D args.period; state->polarity =3D args.polarity; state->duty_cycle =3D 0; + state->duty_offset =3D 0; state->usage_power =3D false; } =20 diff --git a/include/trace/events/pwm.h b/include/trace/events/pwm.h index 12b35e4ff917..2d25ac5de816 100644 --- a/include/trace/events/pwm.h +++ b/include/trace/events/pwm.h @@ -18,6 +18,7 @@ DECLARE_EVENT_CLASS(pwm, __field(struct pwm_device *, pwm) __field(u64, period) __field(u64, duty_cycle) + __field(u64, duty_offset) __field(enum pwm_polarity, polarity) __field(bool, enabled) __field(int, err) @@ -27,13 +28,14 @@ DECLARE_EVENT_CLASS(pwm, __entry->pwm =3D pwm; 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[24.150.219.207]) by smtp.gmail.com with ESMTPSA id o11-20020a0ce40b000000b00699437d4dfbsm3828996qvl.72.2024.04.09.10.41.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Apr 2024 10:41:29 -0700 (PDT) From: Trevor Gamblin To: linux-pwm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, u.kleine-koenig@pengutronix.de, michael.hennerich@analog.com, nuno.sa@analog.com, tgamblin@baylibre.com, dlechner@baylibre.com Subject: [PATCH 2/2 v2] pwm: axi-pwmgen: add duty offset support Date: Tue, 9 Apr 2024 13:41:26 -0400 Message-ID: <20240409174126.1296318-3-tgamblin@baylibre.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240409174126.1296318-1-tgamblin@baylibre.com> References: <20240409174126.1296318-1-tgamblin@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable duty_offset feature now that it is supported in the pwm subsystem. Related macros and struct fields related to duty_offset are renamed to be consistent. Signed-off-by: Trevor Gamblin --- v2 changes: * Address feedback for driver in v1: * Remove line setting supports_offset flag in pwm_chip, since that has been removed from the struct in core.c. --- drivers/pwm/pwm-axi-pwmgen.c | 34 ++++++++++++++++++++++++++-------- 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/drivers/pwm/pwm-axi-pwmgen.c b/drivers/pwm/pwm-axi-pwmgen.c index 539625c404ac..25a083003432 100644 --- a/drivers/pwm/pwm-axi-pwmgen.c +++ b/drivers/pwm/pwm-axi-pwmgen.c @@ -6,9 +6,9 @@ * Copyright 2024 Baylibre SAS * * Limitations: - * - The writes to registers for period and duty are shadowed until - * LOAD_CONFIG is written to AXI_PWMGEN_REG_CONFIG at the end of the - * current period. + * - The writes to registers for period, duty, and duty_offset are + * shadowed until LOAD_CONFIG is written to AXI_PWMGEN_REG_CONFIG at + * the end of the current period. * - Writing LOAD_CONFIG also has the effect of re-synchronizing all * enabled channels, which could cause glitching on other channels. It * is therefore expected that channels are assigned harmonic periods @@ -34,7 +34,7 @@ #define AXI_PWMGEN_REG_NPWM 0x14 #define AXI_PWMGEN_CHX_PERIOD(v, ch) ((v)->period_base + (v)->ch_step * (c= h)) #define AXI_PWMGEN_CHX_DUTY(v, ch) ((v)->duty_base + (v)->ch_step * (ch)) -#define AXI_PWMGEN_CHX_OFFSET(v, ch) ((v)->offset_base + (v)->ch_step * (c= h)) +#define AXI_PWMGEN_CHX_DUTY_OFFSET(v, ch) ((v)->duty_offset_base + (v)->ch= _step * (ch)) #define AXI_PWMGEN_REG_CORE_MAGIC_VAL 0x601A3471 /* Identification number = to test during setup */ #define AXI_PWMGEN_LOAD_CONFIG BIT(1) #define AXI_PWMGEN_RESET BIT(0) @@ -42,7 +42,7 @@ struct axi_pwm_variant { u8 period_base; u8 duty_base; - u8 offset_base; + u8 duty_offset_base; u8 major_version; u8 ch_step; }; @@ -62,7 +62,7 @@ static const struct regmap_config axi_pwmgen_regmap_confi= g =3D { static const struct axi_pwm_variant pwmgen_1_00_variant =3D { .period_base =3D 0x40, .duty_base =3D 0x44, - .offset_base =3D 0x48, + .duty_offset_base =3D 0x48, .major_version =3D 1, .ch_step =3D 12, }; @@ -70,7 +70,7 @@ static const struct axi_pwm_variant pwmgen_1_00_variant = =3D { static const struct axi_pwm_variant pwmgen_2_00_variant =3D { .period_base =3D 0x40, .duty_base =3D 0x80, - .offset_base =3D 0xC0, + .duty_offset_base =3D 0xC0, .major_version =3D 2, .ch_step =3D 4, }; @@ -83,7 +83,7 @@ static int axi_pwmgen_apply(struct pwm_chip *chip, struct= pwm_device *pwm, unsigned int ch =3D pwm->hwpwm; struct regmap *regmap =3D ddata->regmap; const struct axi_pwm_variant *variant =3D ddata->variant; - u64 period_cnt, duty_cnt; + u64 period_cnt, duty_cnt, duty_offset_cnt; int ret; =20 if (state->polarity !=3D PWM_POLARITY_NORMAL) @@ -108,6 +108,14 @@ static int axi_pwmgen_apply(struct pwm_chip *chip, str= uct pwm_device *pwm, ret =3D regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(variant, ch), duty_cnt); if (ret) return ret; + + duty_offset_cnt =3D mul_u64_u64_div_u64(state->duty_offset, ddata->clk_r= ate_hz, NSEC_PER_SEC); + if (duty_offset_cnt > UINT_MAX) + duty_offset_cnt =3D UINT_MAX; + + ret =3D regmap_write(regmap, AXI_PWMGEN_CHX_DUTY_OFFSET(variant, ch), du= ty_offset_cnt); + if (ret) + return ret; } else { ret =3D regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(variant, ch), 0); if (ret) @@ -116,6 +124,10 @@ static int axi_pwmgen_apply(struct pwm_chip *chip, str= uct pwm_device *pwm, ret =3D regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(variant, ch), 0); if (ret) return ret; + + ret =3D regmap_write(regmap, AXI_PWMGEN_CHX_DUTY_OFFSET(variant, ch), 0); + if (ret) + return ret; } =20 return regmap_write(regmap, AXI_PWMGEN_REG_CONFIG, AXI_PWMGEN_LOAD_CONFIG= ); @@ -145,6 +157,12 @@ static int axi_pwmgen_get_state(struct pwm_chip *chip,= struct pwm_device *pwm, =20 state->duty_cycle =3D DIV_ROUND_UP_ULL((u64)cnt * NSEC_PER_SEC, ddata->cl= k_rate_hz); =20 + ret =3D regmap_read(regmap, AXI_PWMGEN_CHX_DUTY_OFFSET(variant, ch), &cnt= ); + if (ret) + return ret; + + state->duty_offset =3D DIV_ROUND_UP_ULL((u64)cnt * NSEC_PER_SEC, ddata->c= lk_rate_hz); + state->polarity =3D PWM_POLARITY_NORMAL; =20 return 0; --=20 2.44.0