From nobody Fri Sep 20 01:36:46 2024 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9172712C53D; Tue, 9 Apr 2024 11:42:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662953; cv=none; b=f8979kyauVXADIrkzCSvwR9BYkq6w7ItSvmDNFT80oXqMj64RYFjGGNHqL4iI1x4vLSs4Urujn+vxNQVdFcbq5RPw6Qsh/DKXYk3drnI7tIwGcEq3xOMIxLOB0jRWpABu2/PFwdbGlra5d/s/IvzWhc6467UcfAVN2BH58Q9XMw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662953; c=relaxed/simple; bh=lRpaqbeDxkCxJuVuV7wFw13Xw8Co2VG0r3GNWGlOryA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Tivd7ovWBizi5A/i5affPsXhDG7Xs10wcgoVcy979mQZ4kR/ANtx2jwNJ5JJWIvtSIAILs9A3Q+cCB4uxoHfzrdR4gyM35hpKE0Pl1JYmw3tKxmJeZCLZWHuLueqUl7MmXYjHhi70t0fW1UHEozNq6G3j7iL8d0L0KwS8GTSAgU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=5WhdTDlk; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="5WhdTDlk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1712662949; bh=lRpaqbeDxkCxJuVuV7wFw13Xw8Co2VG0r3GNWGlOryA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=5WhdTDlkiKrSe2GfXSJrPNQond3nkwTpxc3x0pRZGKHszjxKRKNaLKFbBqv5BFXwj mxmeb/aHZw+z9+II0rBbBVPf0j8UE0tpWCkAzwm7c7emzG9sxXRVF35QhON3xDcsJX yig/p4HfQWJAnpgOOGwd0WHvuStK01CRWs9WMJLzPHpuBKeOX6zEazbD57ZOtQrZoc 0bBdD+82QH5P0aKthO5+wEI5aHOa646K8oItvS37R7sF2Tv68PrjOGJwEdIi78I8tr lsSMWjuKw0THnAX8DH8Kk0NXXPfLmendQOe+Xj+gs4fGQCAcrFY7+NSKm1Dn8cBRg/ kerNjyJAT6qIg== Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 8149C378212C; Tue, 9 Apr 2024 11:42:28 +0000 (UTC) From: AngeloGioacchino Del Regno To: linux-mediatek@lists.infradead.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH 4/5] arm64: dts: mediatek: mt8395-nio-12l: Enable PHYs and USB role switch Date: Tue, 9 Apr 2024 13:42:10 +0200 Message-ID: <20240409114211.310462-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240409114211.310462-1-angelogioacchino.delregno@collabora.com> References: <20240409114211.310462-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the PCIe0 PHY to be able to set calibrations read from eFuses, improving the stability and performance of the PCIe link. While at it, also enable the T-PHYs for both PCIe1 and for USB, allowing the USB ports to finally switch to gadget mode if needed, and configure the VBUS/ID pins of both USB ports for the same. Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt8395-radxa-nio-12l.dts | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/a= rm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index f699633659b6..5cbe969da425 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -685,6 +685,26 @@ pins-bus { }; }; =20 + usb3_port0_pins: usb3p0-default-pins { + pins-vbus { + pinmux =3D ; + input-enable; + }; + }; + + usb2_port0_pins: usb2p0-default-pins { + pins-iddig { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + + pins-vbus { + pinmux =3D ; + output-low; + }; + }; + wifi_vreg_pins: wifi-vreg-pins { pins-wifi-pmu-en { pinmux =3D ; @@ -709,6 +729,10 @@ &pcie1 { status =3D "okay"; }; =20 +&pciephy { + status =3D "okay"; +}; + &pmic { interrupts-extended =3D <&pio 222 IRQ_TYPE_LEVEL_HIGH>; }; @@ -776,6 +800,18 @@ mt6315_7_vbuck1: vbuck1 { }; }; =20 +&u3phy0 { + status =3D "okay"; +}; + +&u3phy1 { + status =3D "okay"; +}; + +&u3phy2 { + status =3D "okay"; +}; + &uart0 { /* Exposed at 40 pin connector */ pinctrl-0 =3D <&uart0_pins>; @@ -791,6 +827,8 @@ &uart1 { }; =20 &ssusb0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb3_port0_pins>; role-switch-default-mode =3D "host"; usb-role-switch; vusb33-supply =3D <&mt6359_vusb_ldo_reg>; @@ -804,6 +842,8 @@ mtu3_hs0_role_sw: endpoint { }; =20 &ssusb2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb2_port0_pins>; vusb33-supply =3D <&mt6359_vusb_ldo_reg>; status =3D "okay"; }; --=20 2.44.0