From nobody Sun Feb 8 00:11:49 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D1CD86AC8 for ; Tue, 9 Apr 2024 11:30:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662228; cv=none; b=Q0XTDuRmWclQXxNAQHUWrfQQW8NbysWimiqIa6etm1dK3GrxbEivxyKygmEUgpXsiOsx1+F1wOwzTLIuWwLDpxQ9EOv7B+5zPoGdJaezjSethc+3xXHSKpENPjqcWuemj7tiXheKRKxxq1D005AujmYsz/4rr5Z2/+MqRk2yzRo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662228; c=relaxed/simple; bh=u3Qc0wRiMBUyZISMmXLXVFu8KBsdxgntgzukFDreyA8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FPy57jXwRGFgDnoxSawn57JeC/b9KfbsYYHx8vIWOkIzxm7OmsNGPx3Pr83kBgo8vE2n6hr0jFxXlY20XcSBnxTPf5OBVNwLewD+lwwgRyDAoQFOTdo3Mbh/m7Ygf1l4Pf7XieVO4YAaJ8YJ+RBtg0eYfLN2vtQOT66hg+ZIHTU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.helo=mgamail.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=m8/Jasfd; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.helo=mgamail.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="m8/Jasfd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712662227; x=1744198227; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=u3Qc0wRiMBUyZISMmXLXVFu8KBsdxgntgzukFDreyA8=; b=m8/JasfdIcOExxHjA5MJwwJtNr3HA1EUuUZQ/HQIa34/EbCiH5hj1UY2 6x2lo+TVjA5QLxMtB3v7gu5xvXsigOkUz6VK46O4jbfKp4cvJXqNnG950 zp1ywXrelW9fm6PCrX5VkwSsbR6IG/5EmqIjwgdMns+wFhcbb36a9M4/W rz8lHKeYWhRzrQrpwG6+0i63ed0+RgQsH+aHN4aTU5v9O6CsMo8EH5FZP 7Y8Alv+5IhkIPn923W7suQGoP4d0/6EW6wD/gPfvmXJgJdIACWQuOhD2W MQwyyIYm3Sr40oK2IEayvsZVXlWbvOAKmAvn/3D4svdO7TRkD7ncvaXlO w==; X-CSE-ConnectionGUID: dGrCqw7lQc28BAsvYM0P5Q== X-CSE-MsgGUID: GixwO8I0RQmzW3I8j6ufjA== X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="30460323" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="30460323" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Apr 2024 04:30:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="937093311" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="937093311" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 09 Apr 2024 04:30:18 -0700 Received: by black.fi.intel.com (Postfix, from userid 1000) id 7465B193; Tue, 9 Apr 2024 14:30:17 +0300 (EEST) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" , Tao Liu Subject: [PATCHv10 01/18] x86/acpi: Extract ACPI MADT wakeup code into a separate file Date: Tue, 9 Apr 2024 14:29:53 +0300 Message-ID: <20240409113010.465412-2-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> References: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to prepare for the expansion of support for the ACPI MADT wakeup method, move the relevant code into a separate file. Introduce a new configuration option to clearly indicate dependencies without the use of ifdefs. There have been no functional changes. Signed-off-by: Kirill A. Shutemov Reviewed-by: Kuppuswamy Sathyanarayanan Acked-by: Kai Huang Reviewed-by: Baoquan He Reviewed-by: Thomas Gleixner Tested-by: Tao Liu --- arch/x86/Kconfig | 7 +++ arch/x86/include/asm/acpi.h | 5 ++ arch/x86/kernel/acpi/Makefile | 11 ++-- arch/x86/kernel/acpi/boot.c | 86 +----------------------------- arch/x86/kernel/acpi/madt_wakeup.c | 82 ++++++++++++++++++++++++++++ 5 files changed, 101 insertions(+), 90 deletions(-) create mode 100644 arch/x86/kernel/acpi/madt_wakeup.c diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 9c637f5b2c76..50ea71adb098 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1116,6 +1116,13 @@ config X86_LOCAL_APIC depends on X86_64 || SMP || X86_32_NON_STANDARD || X86_UP_APIC || PCI_MSI select IRQ_DOMAIN_HIERARCHY =20 +config X86_ACPI_MADT_WAKEUP + def_bool y + depends on X86_64 + depends on ACPI + depends on SMP + depends on X86_LOCAL_APIC + config X86_IO_APIC def_bool y depends on X86_LOCAL_APIC || X86_UP_IOAPIC diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h index f896eed4516c..2625b915ae7f 100644 --- a/arch/x86/include/asm/acpi.h +++ b/arch/x86/include/asm/acpi.h @@ -76,6 +76,11 @@ static inline bool acpi_skip_set_wakeup_address(void) =20 #define acpi_skip_set_wakeup_address acpi_skip_set_wakeup_address =20 +union acpi_subtable_headers; + +int __init acpi_parse_mp_wake(union acpi_subtable_headers *header, + const unsigned long end); + /* * Check if the CPU can handle C2 and deeper */ diff --git a/arch/x86/kernel/acpi/Makefile b/arch/x86/kernel/acpi/Makefile index fc17b3f136fe..8c7329c88a75 100644 --- a/arch/x86/kernel/acpi/Makefile +++ b/arch/x86/kernel/acpi/Makefile @@ -1,11 +1,12 @@ # SPDX-License-Identifier: GPL-2.0 =20 -obj-$(CONFIG_ACPI) +=3D boot.o -obj-$(CONFIG_ACPI_SLEEP) +=3D sleep.o wakeup_$(BITS).o -obj-$(CONFIG_ACPI_APEI) +=3D apei.o -obj-$(CONFIG_ACPI_CPPC_LIB) +=3D cppc.o +obj-$(CONFIG_ACPI) +=3D boot.o +obj-$(CONFIG_ACPI_SLEEP) +=3D sleep.o wakeup_$(BITS).o +obj-$(CONFIG_ACPI_APEI) +=3D apei.o +obj-$(CONFIG_ACPI_CPPC_LIB) +=3D cppc.o +obj-$(CONFIG_X86_ACPI_MADT_WAKEUP) +=3D madt_wakeup.o =20 ifneq ($(CONFIG_ACPI_PROCESSOR),) -obj-y +=3D cstate.o +obj-y +=3D cstate.o endif =20 diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c index 4bf82dbd2a6b..53b8802e01e7 100644 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -67,13 +67,6 @@ static bool has_lapic_cpus __initdata; static bool acpi_support_online_capable; #endif =20 -#ifdef CONFIG_X86_64 -/* Physical address of the Multiprocessor Wakeup Structure mailbox */ -static u64 acpi_mp_wake_mailbox_paddr; -/* Virtual address of the Multiprocessor Wakeup Structure mailbox */ -static struct acpi_madt_multiproc_wakeup_mailbox *acpi_mp_wake_mailbox; -#endif - #ifdef CONFIG_X86_IO_APIC /* * Locks related to IOAPIC hotplug @@ -341,60 +334,6 @@ acpi_parse_lapic_nmi(union acpi_subtable_headers * hea= der, const unsigned long e =20 return 0; } - -#ifdef CONFIG_X86_64 -static int acpi_wakeup_cpu(u32 apicid, unsigned long start_ip) -{ - /* - * Remap mailbox memory only for the first call to acpi_wakeup_cpu(). - * - * Wakeup of secondary CPUs is fully serialized in the core code. - * No need to protect acpi_mp_wake_mailbox from concurrent accesses. - */ - if (!acpi_mp_wake_mailbox) { - acpi_mp_wake_mailbox =3D memremap(acpi_mp_wake_mailbox_paddr, - sizeof(*acpi_mp_wake_mailbox), - MEMREMAP_WB); - } - - /* - * Mailbox memory is shared between the firmware and OS. Firmware will - * listen on mailbox command address, and once it receives the wakeup - * command, the CPU associated with the given apicid will be booted. - * - * The value of 'apic_id' and 'wakeup_vector' must be visible to the - * firmware before the wakeup command is visible. smp_store_release() - * ensures ordering and visibility. - */ - acpi_mp_wake_mailbox->apic_id =3D apicid; - acpi_mp_wake_mailbox->wakeup_vector =3D start_ip; - smp_store_release(&acpi_mp_wake_mailbox->command, - ACPI_MP_WAKE_COMMAND_WAKEUP); - - /* - * Wait for the CPU to wake up. - * - * The CPU being woken up is essentially in a spin loop waiting to be - * woken up. It should not take long for it wake up and acknowledge by - * zeroing out ->command. - * - * ACPI specification doesn't provide any guidance on how long kernel - * has to wait for a wake up acknowledgement. It also doesn't provide - * a way to cancel a wake up request if it takes too long. - * - * In TDX environment, the VMM has control over how long it takes to - * wake up secondary. It can postpone scheduling secondary vCPU - * indefinitely. Giving up on wake up request and reporting error opens - * possible attack vector for VMM: it can wake up a secondary CPU when - * kernel doesn't expect it. Wait until positive result of the wake up - * request. - */ - while (READ_ONCE(acpi_mp_wake_mailbox->command)) - cpu_relax(); - - return 0; -} -#endif /* CONFIG_X86_64 */ #endif /* CONFIG_X86_LOCAL_APIC */ =20 #ifdef CONFIG_X86_IO_APIC @@ -1124,29 +1063,6 @@ static int __init acpi_parse_madt_lapic_entries(void) } return 0; } - -#ifdef CONFIG_X86_64 -static int __init acpi_parse_mp_wake(union acpi_subtable_headers *header, - const unsigned long end) -{ - struct acpi_madt_multiproc_wakeup *mp_wake; - - if (!IS_ENABLED(CONFIG_SMP)) - return -ENODEV; - - mp_wake =3D (struct acpi_madt_multiproc_wakeup *)header; - if (BAD_MADT_ENTRY(mp_wake, end)) - return -EINVAL; - - acpi_table_print_madt_entry(&header->common); - - acpi_mp_wake_mailbox_paddr =3D mp_wake->base_address; - - apic_update_callback(wakeup_secondary_cpu_64, acpi_wakeup_cpu); - - return 0; -} -#endif /* CONFIG_X86_64 */ #endif /* CONFIG_X86_LOCAL_APIC */ =20 #ifdef CONFIG_X86_IO_APIC @@ -1343,7 +1259,7 @@ static void __init acpi_process_madt(void) smp_found_config =3D 1; } =20 -#ifdef CONFIG_X86_64 +#ifdef CONFIG_X86_ACPI_MADT_WAKEUP /* * Parse MADT MP Wake entry. */ diff --git a/arch/x86/kernel/acpi/madt_wakeup.c b/arch/x86/kernel/acpi/madt= _wakeup.c new file mode 100644 index 000000000000..7f164d38bd0b --- /dev/null +++ b/arch/x86/kernel/acpi/madt_wakeup.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +#include +#include +#include +#include +#include + +/* Physical address of the Multiprocessor Wakeup Structure mailbox */ +static u64 acpi_mp_wake_mailbox_paddr; + +/* Virtual address of the Multiprocessor Wakeup Structure mailbox */ +static struct acpi_madt_multiproc_wakeup_mailbox *acpi_mp_wake_mailbox; + +static int acpi_wakeup_cpu(u32 apicid, unsigned long start_ip) +{ + /* + * Remap mailbox memory only for the first call to acpi_wakeup_cpu(). + * + * Wakeup of secondary CPUs is fully serialized in the core code. + * No need to protect acpi_mp_wake_mailbox from concurrent accesses. + */ + if (!acpi_mp_wake_mailbox) { + acpi_mp_wake_mailbox =3D memremap(acpi_mp_wake_mailbox_paddr, + sizeof(*acpi_mp_wake_mailbox), + MEMREMAP_WB); + } + + /* + * Mailbox memory is shared between the firmware and OS. Firmware will + * listen on mailbox command address, and once it receives the wakeup + * command, the CPU associated with the given apicid will be booted. + * + * The value of 'apic_id' and 'wakeup_vector' must be visible to the + * firmware before the wakeup command is visible. smp_store_release() + * ensures ordering and visibility. + */ + acpi_mp_wake_mailbox->apic_id =3D apicid; + acpi_mp_wake_mailbox->wakeup_vector =3D start_ip; + smp_store_release(&acpi_mp_wake_mailbox->command, + ACPI_MP_WAKE_COMMAND_WAKEUP); + + /* + * Wait for the CPU to wake up. + * + * The CPU being woken up is essentially in a spin loop waiting to be + * woken up. It should not take long for it wake up and acknowledge by + * zeroing out ->command. + * + * ACPI specification doesn't provide any guidance on how long kernel + * has to wait for a wake up acknowledgment. It also doesn't provide + * a way to cancel a wake up request if it takes too long. + * + * In TDX environment, the VMM has control over how long it takes to + * wake up secondary. It can postpone scheduling secondary vCPU + * indefinitely. Giving up on wake up request and reporting error opens + * possible attack vector for VMM: it can wake up a secondary CPU when + * kernel doesn't expect it. Wait until positive result of the wake up + * request. + */ + while (READ_ONCE(acpi_mp_wake_mailbox->command)) + cpu_relax(); + + return 0; +} + +int __init acpi_parse_mp_wake(union acpi_subtable_headers *header, + const unsigned long end) +{ + struct acpi_madt_multiproc_wakeup *mp_wake; + + mp_wake =3D (struct acpi_madt_multiproc_wakeup *)header; + if (BAD_MADT_ENTRY(mp_wake, end)) + return -EINVAL; + + acpi_table_print_madt_entry(&header->common); + + acpi_mp_wake_mailbox_paddr =3D mp_wake->base_address; + + apic_update_callback(wakeup_secondary_cpu_64, acpi_wakeup_cpu); + + return 0; +} --=20 2.43.0 From nobody Sun Feb 8 00:11:49 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87704128366 for ; Tue, 9 Apr 2024 11:30:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662228; cv=none; b=iDIo8F7hphrUolLGA8TuJ96P98k4eKrKX3rywBYgcP5J0cqh5G/+g6xcrFs4IIgq87vamT4lsEDyxKYVTszo/wr8oTAxqdy2HsgmiLYdD18L1cn9FOuurGPpgwypfeNcb/E/KADY7G82ZRlAVX4oo2bAWA0io0K++fZ2BqRHI6M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662228; c=relaxed/simple; bh=TxEZrVwney4pCeOb1c0lFVUFay3kAApGY+zEuDo/6UA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MUphpU5sfzOOO8ODrdlNpa80a8GS/CHepIiMdHR57ZEnCWTtuxPkCz0GjCf1G35W9zfMkXdbI8EiXheercwtL+MAnRx3uS0WUD74dDRAKBR8qsBB5zIqGXi1sUdjSn2jZViq23EwbnBduBxgSyzSJplEafmeJrp/Ge9KUXNToMg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.helo=mgamail.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Oa53gI9O; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.helo=mgamail.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Oa53gI9O" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712662228; x=1744198228; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TxEZrVwney4pCeOb1c0lFVUFay3kAApGY+zEuDo/6UA=; b=Oa53gI9OjCuiBcvTcvniP/hBaIBSAPxf2Q8IXTBH86iOSK/0mua1vpb6 Qxi9ne08h3bv/1YSPLnrAa0Q6WCPQdcwFuN2k+CcFvQcTEAPq6DXwXGnY PYr+yV6qo7R4QQWfbezgqhql56bZAV5k568wJbgNPCXVZZ9QoE6vadpsZ pnmVbmc2oRnm+wCWXBuYewy85g46x7esDTJXAM9oOmwzkiR4TM40r+TzM JcUq+8vzzgQVbUW8vtrcs9UfaQKfIfwwDyHqkXEXgGC5aHuiHMtc3k7ML 5e65d58cLGR7PXT0YuP4kCn71b+pl5SYZ5wFehA321Fg3BorVYW6G60V7 Q==; X-CSE-ConnectionGUID: rsFyu/yxRJihL9yYMPg97Q== X-CSE-MsgGUID: rtbJR12USbqQhos/xZ01CA== X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="30460333" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="30460333" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Apr 2024 04:30:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="937093313" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="937093313" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 09 Apr 2024 04:30:18 -0700 Received: by black.fi.intel.com (Postfix, from userid 1000) id 847D5357; Tue, 9 Apr 2024 14:30:17 +0300 (EEST) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" , Tao Liu Subject: [PATCHv10 02/18] x86/apic: Mark acpi_mp_wake_* variables as __ro_after_init Date: Tue, 9 Apr 2024 14:29:54 +0300 Message-ID: <20240409113010.465412-3-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> References: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" acpi_mp_wake_mailbox_paddr and acpi_mp_wake_mailbox initialized once during ACPI MADT init and never changed. Signed-off-by: Kirill A. Shutemov Acked-by: Kai Huang Reviewed-by: Baoquan He Reviewed-by: Thomas Gleixner Tested-by: Tao Liu --- arch/x86/kernel/acpi/madt_wakeup.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/acpi/madt_wakeup.c b/arch/x86/kernel/acpi/madt= _wakeup.c index 7f164d38bd0b..cf79ea6f3007 100644 --- a/arch/x86/kernel/acpi/madt_wakeup.c +++ b/arch/x86/kernel/acpi/madt_wakeup.c @@ -6,10 +6,10 @@ #include =20 /* Physical address of the Multiprocessor Wakeup Structure mailbox */ -static u64 acpi_mp_wake_mailbox_paddr; +static u64 acpi_mp_wake_mailbox_paddr __ro_after_init; =20 /* Virtual address of the Multiprocessor Wakeup Structure mailbox */ -static struct acpi_madt_multiproc_wakeup_mailbox *acpi_mp_wake_mailbox; +static struct acpi_madt_multiproc_wakeup_mailbox *acpi_mp_wake_mailbox __r= o_after_init; =20 static int acpi_wakeup_cpu(u32 apicid, unsigned long start_ip) { --=20 2.43.0 From nobody Sun Feb 8 00:11:49 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1428386651 for ; Tue, 9 Apr 2024 11:30:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662227; cv=none; b=umRdEdAYUiGru2vydrn2Rm3yTgOluu8fPbsET/ENB+UOIHvM0mpiNwlxciwGOj1hYtKyIsDBcen1Eu/OEF10OV3xNiuB0FOjyc/eQhRu9FNsZTDrJwNxm0a26DYQyndJEtrFd9UHMG1uqX9MNZ7jB1VdQb8UtqN+4xmpdB7AAJg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662227; c=relaxed/simple; bh=PcGW20f9JUfyIYDmdaZjLxpufn1UsRTL7qIDtM0mrrc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gG2o4ssBvakhgH/PH1+c/6Llc+0PUciizF9EcDarxO2S2wZBISUyJT/BW5+dv/kc4QyxIBb68JWC0+ezuDKxaO6EAOPdHPB0Fg3GNjz7PG7zSCtcjw4lfD+fYnFVxLEjuuy9GBUy3f5rBNH6IlXv9XrqFioktqBqi7VbMjvgLMk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.helo=mgamail.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=QHQDDjh3; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.helo=mgamail.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="QHQDDjh3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712662227; x=1744198227; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PcGW20f9JUfyIYDmdaZjLxpufn1UsRTL7qIDtM0mrrc=; b=QHQDDjh3nFsRO/80sXLwHYY+L/QeuFUQK0LJWrfD1vyAUW8DhvmBVkEn 8O1iBmB42qi7a4kgFPizOa6YleL7GMA+j9xiCTsv/w5fB8ZHCTsmCYQFi DtJf/G4dIiVLJbacOiZqYotbp6wrITxC2pIkJZ4C3HzJqsGbriHTg7OFg GyPg9a16gRx3dMtF8aLa8ZDftKctLHBE2xUwa3Op2I29Ot/rInRXcWtPr bXrNMbMN+C36y0g1joKmb5VruG9q7818+cqOGqhIiNDCMZAVU2PE08mr2 JmYWSpjwKjmUKqftvOf5GFGmSR+H45V3BPNoBLovKEHGY7H0TQIAuS8F4 g==; X-CSE-ConnectionGUID: 7BLg5ohtTPCOBunpRUxrTg== X-CSE-MsgGUID: sW/zlbclTM6TSVNuAqSZVw== X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="30460313" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="30460313" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Apr 2024 04:30:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="937093309" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="937093309" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 09 Apr 2024 04:30:18 -0700 Received: by black.fi.intel.com (Postfix, from userid 1000) id 900688C9; Tue, 9 Apr 2024 14:30:17 +0300 (EEST) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" , Tao Liu Subject: [PATCHv10 03/18] cpu/hotplug: Add support for declaring CPU offlining not supported Date: Tue, 9 Apr 2024 14:29:55 +0300 Message-ID: <20240409113010.465412-4-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> References: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The ACPI MADT mailbox wakeup method doesn't allow to offline CPU after it got woke up. Currently offlining hotplug is prevented based on the confidential computing attribute which is set for Intel TDX. But TDX is not the only possible user of the wake up method. The MADT wakeup can be implemented outside of a confidential computing environment. Offline support is a property of the wakeup method, not the CoCo implementation. Introduce cpu_hotplug_disable_offlining() that can be called to indicate that CPU offlining should be disabled. This function is going to replace CC_ATTR_HOTPLUG_DISABLED for ACPI MADT wakeup method. Signed-off-by: Kirill A. Shutemov Reviewed-by: Thomas Gleixner Tested-by: Tao Liu --- include/linux/cpu.h | 2 ++ kernel/cpu.c | 13 ++++++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/include/linux/cpu.h b/include/linux/cpu.h index 272e4e79e15c..cfe29e52ce84 100644 --- a/include/linux/cpu.h +++ b/include/linux/cpu.h @@ -141,6 +141,7 @@ extern void cpus_read_lock(void); extern void cpus_read_unlock(void); extern int cpus_read_trylock(void); extern void lockdep_assert_cpus_held(void); +extern void cpu_hotplug_disable_offlining(void); extern void cpu_hotplug_disable(void); extern void cpu_hotplug_enable(void); void clear_tasks_mm_cpumask(int cpu); @@ -156,6 +157,7 @@ static inline void cpus_read_lock(void) { } static inline void cpus_read_unlock(void) { } static inline int cpus_read_trylock(void) { return true; } static inline void lockdep_assert_cpus_held(void) { } +static inline void cpu_hotplug_disable_offlining(void) { } static inline void cpu_hotplug_disable(void) { } static inline void cpu_hotplug_enable(void) { } static inline int remove_cpu(unsigned int cpu) { return -EPERM; } diff --git a/kernel/cpu.c b/kernel/cpu.c index 8f6affd051f7..08860baa6ce0 100644 --- a/kernel/cpu.c +++ b/kernel/cpu.c @@ -483,6 +483,8 @@ static int cpu_hotplug_disabled; =20 DEFINE_STATIC_PERCPU_RWSEM(cpu_hotplug_lock); =20 +static bool cpu_hotplug_offline_disabled __ro_after_init; + void cpus_read_lock(void) { percpu_down_read(&cpu_hotplug_lock); @@ -542,6 +544,14 @@ static void lockdep_release_cpus_lock(void) rwsem_release(&cpu_hotplug_lock.dep_map, _THIS_IP_); } =20 +/* Declare CPU offlining not supported */ +void cpu_hotplug_disable_offlining(void) +{ + cpu_maps_update_begin(); + cpu_hotplug_offline_disabled =3D true; + cpu_maps_update_done(); +} + /* * Wait for currently running CPU hotplug operations to complete (if any) = and * disable future CPU hotplug (from sysfs). The 'cpu_add_remove_lock' prot= ects @@ -1518,7 +1528,8 @@ static int cpu_down_maps_locked(unsigned int cpu, enu= m cpuhp_state target) * If the platform does not support hotplug, report it explicitly to * differentiate it from a transient offlining failure. */ - if (cc_platform_has(CC_ATTR_HOTPLUG_DISABLED)) + if (cc_platform_has(CC_ATTR_HOTPLUG_DISABLED) || + cpu_hotplug_offline_disabled) return -EOPNOTSUPP; if (cpu_hotplug_disabled) return -EBUSY; --=20 2.43.0 From nobody Sun Feb 8 00:11:49 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3327128806 for ; Tue, 9 Apr 2024 11:30:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662229; cv=none; b=n4ykG8QBiqBLGDXlKbaexBPGTWqp/Ki7Hzx1LN8k4+5MgVPaJA7qxV1EmkUtGS0MeKcdrUSgm5Wg+15s9vtjK1wHfPX5McHHSxTvTjDfbKfdbwFPNdYrSHjbboCtvvUpudAJk42/37cpPfQpLLnCjipPc8Ns91wj3q7W9OgC/W8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662229; c=relaxed/simple; bh=IXySMsd1LbCuYXSWDngaVCbkpG0HLAxIAN3nQj47ksE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=anO2p3kEzubo552q8d90WYw+4VRBWEYDiwwhd2jtVdW13CmJYT1JYICV89F25VGIhgtJifI7orESd8Rkv2grOgIY/Iy9GzKgmOcTl4GFvLsojNuVqaumzQPQCR8MWTSAGIUzsFWMYbtbE/4/qF4WvTvocrYHi7oycbp0lufJSwA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.helo=mgamail.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=QANIiwI8; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.helo=mgamail.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="QANIiwI8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712662228; x=1744198228; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IXySMsd1LbCuYXSWDngaVCbkpG0HLAxIAN3nQj47ksE=; b=QANIiwI8cX1pvUpzWP7rAaIXH8eeFx9rZs3yhBJ4k5UeSRJp0SSWOo/4 QjfqF7NmP+JQBF5MSyaPp/dP1BsYe30hayTALI7uUh5qgwO5TvRSLuAlN fqGP7T2nwVfWeqa8JHUo86D9Ft0ewDlakr74ekLhBCigGsmUCIfedtEVU FU9qIN3JfogqHclzA8WwDRStE6OJ9NNyLDuO0epcvYSS8ULsuUXb3Dn+D wQ+0whhxGaLGWzVyVg1Vv4VxM0O81wDcTTzs72Dm7Lhn0LU2pUENqAqkA RmqTGqkuZOYQpN+0+7uuTH9Tee8kc2lW9ceDsgYGESe+FZbBXYG2Z7wJE w==; X-CSE-ConnectionGUID: s0wYpC75TxedTdWpm4AUNA== X-CSE-MsgGUID: TxN69dd4Q0m71ut3RziHJw== X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="30460342" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="30460342" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Apr 2024 04:30:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="937093315" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="937093315" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 09 Apr 2024 04:30:18 -0700 Received: by black.fi.intel.com (Postfix, from userid 1000) id 9EFDA8CA; Tue, 9 Apr 2024 14:30:17 +0300 (EEST) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" , Tao Liu Subject: [PATCHv10 04/18] cpu/hotplug, x86/acpi: Disable CPU offlining for ACPI MADT wakeup Date: Tue, 9 Apr 2024 14:29:56 +0300 Message-ID: <20240409113010.465412-5-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> References: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" ACPI MADT doesn't allow to offline CPU after it got woke up. Currently CPU hotplug is prevented based on the confidential computing attribute which is set for Intel TDX. But TDX is not the only possible user of the wake up method. Disable CPU offlining on ACPI MADT wakeup enumeration. Signed-off-by: Kirill A. Shutemov Reviewed-by: Thomas Gleixner Tested-by: Tao Liu --- arch/x86/coco/core.c | 1 - arch/x86/kernel/acpi/madt_wakeup.c | 3 +++ include/linux/cc_platform.h | 10 ---------- kernel/cpu.c | 3 +-- 4 files changed, 4 insertions(+), 13 deletions(-) diff --git a/arch/x86/coco/core.c b/arch/x86/coco/core.c index b31ef2424d19..0f81f70aca82 100644 --- a/arch/x86/coco/core.c +++ b/arch/x86/coco/core.c @@ -29,7 +29,6 @@ static bool noinstr intel_cc_platform_has(enum cc_attr at= tr) { switch (attr) { case CC_ATTR_GUEST_UNROLL_STRING_IO: - case CC_ATTR_HOTPLUG_DISABLED: case CC_ATTR_GUEST_MEM_ENCRYPT: case CC_ATTR_MEM_ENCRYPT: return true; diff --git a/arch/x86/kernel/acpi/madt_wakeup.c b/arch/x86/kernel/acpi/madt= _wakeup.c index cf79ea6f3007..d222be8d7a07 100644 --- a/arch/x86/kernel/acpi/madt_wakeup.c +++ b/arch/x86/kernel/acpi/madt_wakeup.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later #include +#include #include #include #include @@ -76,6 +77,8 @@ int __init acpi_parse_mp_wake(union acpi_subtable_headers= *header, =20 acpi_mp_wake_mailbox_paddr =3D mp_wake->base_address; =20 + cpu_hotplug_disable_offlining(); + apic_update_callback(wakeup_secondary_cpu_64, acpi_wakeup_cpu); =20 return 0; diff --git a/include/linux/cc_platform.h b/include/linux/cc_platform.h index 60693a145894..caa4b4430634 100644 --- a/include/linux/cc_platform.h +++ b/include/linux/cc_platform.h @@ -81,16 +81,6 @@ enum cc_attr { */ CC_ATTR_GUEST_SEV_SNP, =20 - /** - * @CC_ATTR_HOTPLUG_DISABLED: Hotplug is not supported or disabled. - * - * The platform/OS is running as a guest/virtual machine does not - * support CPU hotplug feature. - * - * Examples include TDX Guest. - */ - CC_ATTR_HOTPLUG_DISABLED, - /** * @CC_ATTR_HOST_SEV_SNP: AMD SNP enabled on the host. * diff --git a/kernel/cpu.c b/kernel/cpu.c index 08860baa6ce0..a70767aee9d0 100644 --- a/kernel/cpu.c +++ b/kernel/cpu.c @@ -1528,8 +1528,7 @@ static int cpu_down_maps_locked(unsigned int cpu, enu= m cpuhp_state target) * If the platform does not support hotplug, report it explicitly to * differentiate it from a transient offlining failure. */ - if (cc_platform_has(CC_ATTR_HOTPLUG_DISABLED) || - cpu_hotplug_offline_disabled) + if (cpu_hotplug_offline_disabled) return -EOPNOTSUPP; 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Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv10 05/18] x86/kexec: Keep CR4.MCE set during kexec for TDX guest Date: Tue, 9 Apr 2024 14:29:57 +0300 Message-ID: <20240409113010.465412-6-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> References: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Depending on setup, TDX guests might be allowed to clear CR4.MCE. Attempt to clear it leads to #VE. Use alternatives to keep the flag during kexec for TDX guests. The change doesn't affect non-TDX-guest environments. Signed-off-by: Kirill A. Shutemov Reviewed-by: Kai Huang --- arch/x86/kernel/relocate_kernel_64.S | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/x86/kernel/relocate_kernel_64.S b/arch/x86/kernel/relocat= e_kernel_64.S index 56cab1bb25f5..8e2037d78a1f 100644 --- a/arch/x86/kernel/relocate_kernel_64.S +++ b/arch/x86/kernel/relocate_kernel_64.S @@ -5,6 +5,8 @@ */ =20 #include +#include +#include #include #include #include @@ -145,11 +147,17 @@ SYM_CODE_START_LOCAL_NOALIGN(identity_mapped) * Set cr4 to a known state: * - physical address extension enabled * - 5-level paging, if it was enabled before + * - Machine check exception on TDX guest, if it was enabled before. + * Clearing MCE might not allowed in TDX guests, depending on setup. */ movl $X86_CR4_PAE, %eax testq $X86_CR4_LA57, %r13 jz 1f orl $X86_CR4_LA57, %eax +1: + testq $X86_CR4_MCE, %r13 + jz 1f + ALTERNATIVE "", __stringify(orl $X86_CR4_MCE, %eax), X86_FEATURE_TDX_GUEST 1: movq %rax, %cr4 =20 --=20 2.43.0 From nobody Sun Feb 8 00:11:49 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2171812A151 for ; Tue, 9 Apr 2024 11:30:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662231; cv=none; b=e2qlNP6uE4V31PTl7s5lww5WLqeEkDhZS7+iDe66YDxk0mlTuKeMYoL+YcYcq7Zoa+yZmP+vsExn2GTDWJHVsNeV7BBInWk156HDlkkOI1iFyOiZIb7sHFeiy9kPpu1FLZgGrZVVJg6dTNNt80pY6oWrc77b4WvbFuX33pxFybA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662231; c=relaxed/simple; bh=CEXjQL+jNGkhJ9l4MdiVkcG+/RoIx9FwHANoikn9plk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uBcaOLdbnFXEiIEUN+yId5zpx7KxCSPOUV3Kixi8XS9TcFwNhoLFfkWNrRGLmeoRJy4i1mWU9CRJot8PlqeYvMJ6as9m/N3RKT7tUaWp9Csiuc2KUo0g+heTyUh3SGSdSfzPTDnyQ/luIR5Ps5n8OGOvPvPZyhXtVXy6pEwkLFA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.helo=mgamail.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=aBGb2zE1; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.helo=mgamail.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="aBGb2zE1" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712662230; x=1744198230; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CEXjQL+jNGkhJ9l4MdiVkcG+/RoIx9FwHANoikn9plk=; b=aBGb2zE1BWS52PK3KaHNQO2ZK8v7cxOZl7phIYTAOco3pkENP+mvPoq3 /I0b44GI3npSpLFHVe/sPzgI8Lq8Ksip7y5UCJR2wlTgztqQaiZ5bpb5e iPAllATero4teb/hiOb0DX1wght73c67n0Ieo4HyStJW1+pLGDug2+LCI ynQVJ8VTTdh1UVlTCIeDr4EVyjHUPnH9BHoTWb7pwPsXF9I7RCZwMPcUC LCyR8PgEaSFBu0s/U1UYG4CrrlK4I/OqTYsO4IECszrW/aDx4/NuH3Epk X37n9yL1w1NQRtHqDqVzoN72EazfR4llB3yvHH0d3rDUV1510tCJlva+k w==; X-CSE-ConnectionGUID: hj9yicJWQ66TcKwEEpvDHA== X-CSE-MsgGUID: caHoRSOcRmWlc5X7L57N8w== X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="30460367" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="30460367" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Apr 2024 04:30:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="937093329" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="937093329" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 09 Apr 2024 04:30:23 -0700 Received: by black.fi.intel.com (Postfix, from userid 1000) id BA2189BC; Tue, 9 Apr 2024 14:30:17 +0300 (EEST) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" , Dave Hansen , Tao Liu Subject: [PATCHv10 06/18] x86/mm: Make x86_platform.guest.enc_status_change_*() return errno Date: Tue, 9 Apr 2024 14:29:58 +0300 Message-ID: <20240409113010.465412-7-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> References: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" TDX is going to have more than one reason to fail enc_status_change_prepare(). Change the callback to return errno instead of assuming -EIO; enc_status_change_finish() changed too to keep the interface symmetric. Signed-off-by: Kirill A. Shutemov Reviewed-by: Dave Hansen Reviewed-by: Kai Huang Tested-by: Tao Liu --- arch/x86/coco/tdx/tdx.c | 20 +++++++++++--------- arch/x86/hyperv/ivm.c | 22 ++++++++++------------ arch/x86/include/asm/x86_init.h | 4 ++-- arch/x86/kernel/x86_init.c | 4 ++-- arch/x86/mm/mem_encrypt_amd.c | 8 ++++---- arch/x86/mm/pat/set_memory.c | 8 +++++--- 6 files changed, 34 insertions(+), 32 deletions(-) diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index c1cb90369915..26fa47db5782 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -798,28 +798,30 @@ static bool tdx_enc_status_changed(unsigned long vadd= r, int numpages, bool enc) return true; } =20 -static bool tdx_enc_status_change_prepare(unsigned long vaddr, int numpage= s, - bool enc) +static int tdx_enc_status_change_prepare(unsigned long vaddr, int numpages, + bool enc) { /* * Only handle shared->private conversion here. * See the comment in tdx_early_init(). */ - if (enc) - return tdx_enc_status_changed(vaddr, numpages, enc); - return true; + if (enc && !tdx_enc_status_changed(vaddr, numpages, enc)) + return -EIO; + + return 0; } =20 -static bool tdx_enc_status_change_finish(unsigned long vaddr, int numpages, +static int tdx_enc_status_change_finish(unsigned long vaddr, int numpages, bool enc) { /* * Only handle private->shared conversion here. * See the comment in tdx_early_init(). */ - if (!enc) - return tdx_enc_status_changed(vaddr, numpages, enc); - return true; + if (!enc && !tdx_enc_status_changed(vaddr, numpages, enc)) + return -EIO; + + return 0; } =20 void __init tdx_early_init(void) diff --git a/arch/x86/hyperv/ivm.c b/arch/x86/hyperv/ivm.c index 768d73de0d09..b4a851d27c7c 100644 --- a/arch/x86/hyperv/ivm.c +++ b/arch/x86/hyperv/ivm.c @@ -523,9 +523,9 @@ static int hv_mark_gpa_visibility(u16 count, const u64 = pfn[], * transition is complete, hv_vtom_set_host_visibility() marks the pages * as "present" again. */ -static bool hv_vtom_clear_present(unsigned long kbuffer, int pagecount, bo= ol enc) +static int hv_vtom_clear_present(unsigned long kbuffer, int pagecount, boo= l enc) { - return !set_memory_np(kbuffer, pagecount); + return set_memory_np(kbuffer, pagecount); } =20 /* @@ -536,20 +536,19 @@ static bool hv_vtom_clear_present(unsigned long kbuff= er, int pagecount, bool enc * with host. This function works as wrap of hv_mark_gpa_visibility() * with memory base and size. */ -static bool hv_vtom_set_host_visibility(unsigned long kbuffer, int pagecou= nt, bool enc) +static int hv_vtom_set_host_visibility(unsigned long kbuffer, int pagecoun= t, bool enc) { enum hv_mem_host_visibility visibility =3D enc ? VMBUS_PAGE_NOT_VISIBLE : VMBUS_PAGE_VISIBLE_READ_WRITE; u64 *pfn_array; phys_addr_t paddr; + int i, pfn, err; void *vaddr; int ret =3D 0; - bool result =3D true; - int i, pfn; =20 pfn_array =3D kmalloc(HV_HYP_PAGE_SIZE, GFP_KERNEL); if (!pfn_array) { - result =3D false; + ret =3D -ENOMEM; goto err_set_memory_p; } =20 @@ -568,10 +567,8 @@ static bool hv_vtom_set_host_visibility(unsigned long = kbuffer, int pagecount, bo if (pfn =3D=3D HV_MAX_MODIFY_GPA_REP_COUNT || i =3D=3D pagecount - 1) { ret =3D hv_mark_gpa_visibility(pfn, pfn_array, visibility); - if (ret) { - result =3D false; + if (ret) goto err_free_pfn_array; - } pfn =3D 0; } } @@ -586,10 +583,11 @@ static bool hv_vtom_set_host_visibility(unsigned long= kbuffer, int pagecount, bo * order to avoid leaving the memory range in a "broken" state. Setting * the PRESENT bits shouldn't fail, but return an error if it does. */ - if (set_memory_p(kbuffer, pagecount)) - result =3D false; + err =3D set_memory_p(kbuffer, pagecount); + if (err && !ret) + ret =3D err; =20 - return result; + return ret; } =20 static bool hv_vtom_tlb_flush_required(bool private) diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_ini= t.h index 6149eabe200f..28ac3cb9b987 100644 --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h @@ -151,8 +151,8 @@ struct x86_init_acpi { * @enc_cache_flush_required Returns true if a cache flush is needed befor= e changing page encryption status */ struct x86_guest { - bool (*enc_status_change_prepare)(unsigned long vaddr, int npages, bool e= nc); - bool (*enc_status_change_finish)(unsigned long vaddr, int npages, bool en= c); + int (*enc_status_change_prepare)(unsigned long vaddr, int npages, bool en= c); + int (*enc_status_change_finish)(unsigned long vaddr, int npages, bool enc= ); bool (*enc_tlb_flush_required)(bool enc); bool (*enc_cache_flush_required)(void); }; diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c index d5dc5a92635a..a7143bb7dd93 100644 --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c @@ -134,8 +134,8 @@ struct x86_cpuinit_ops x86_cpuinit =3D { =20 static void default_nmi_init(void) { }; =20 -static bool enc_status_change_prepare_noop(unsigned long vaddr, int npages= , bool enc) { return true; } -static bool enc_status_change_finish_noop(unsigned long vaddr, int npages,= bool enc) { return true; } +static int enc_status_change_prepare_noop(unsigned long vaddr, int npages,= bool enc) { return 0; } +static int enc_status_change_finish_noop(unsigned long vaddr, int npages, = bool enc) { return 0; } static bool enc_tlb_flush_required_noop(bool enc) { return false; } static bool enc_cache_flush_required_noop(void) { return false; } static bool is_private_mmio_noop(u64 addr) {return false; } diff --git a/arch/x86/mm/mem_encrypt_amd.c b/arch/x86/mm/mem_encrypt_amd.c index 422602f6039b..e7b67519ddb5 100644 --- a/arch/x86/mm/mem_encrypt_amd.c +++ b/arch/x86/mm/mem_encrypt_amd.c @@ -283,7 +283,7 @@ static void enc_dec_hypercall(unsigned long vaddr, unsi= gned long size, bool enc) #endif } =20 -static bool amd_enc_status_change_prepare(unsigned long vaddr, int npages,= bool enc) +static int amd_enc_status_change_prepare(unsigned long vaddr, int npages, = bool enc) { /* * To maintain the security guarantees of SEV-SNP guests, make sure @@ -292,11 +292,11 @@ static bool amd_enc_status_change_prepare(unsigned lo= ng vaddr, int npages, bool if (cc_platform_has(CC_ATTR_GUEST_SEV_SNP) && !enc) snp_set_memory_shared(vaddr, npages); =20 - return true; + return 0; } =20 /* Return true unconditionally: return value doesn't matter for the SEV si= de */ -static bool amd_enc_status_change_finish(unsigned long vaddr, int npages, = bool enc) +static int amd_enc_status_change_finish(unsigned long vaddr, int npages, b= ool enc) { /* * After memory is mapped encrypted in the page table, validate it @@ -308,7 +308,7 @@ static bool amd_enc_status_change_finish(unsigned long = vaddr, int npages, bool e if (!cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT)) enc_dec_hypercall(vaddr, npages << PAGE_SHIFT, enc); =20 - return true; + return 0; } =20 static void __init __set_clr_pte_enc(pte_t *kpte, int level, bool enc) diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c index 80c9037ffadf..e5b454036bf3 100644 --- a/arch/x86/mm/pat/set_memory.c +++ b/arch/x86/mm/pat/set_memory.c @@ -2156,7 +2156,8 @@ static int __set_memory_enc_pgtable(unsigned long add= r, int numpages, bool enc) cpa_flush(&cpa, x86_platform.guest.enc_cache_flush_required()); =20 /* Notify hypervisor that we are about to set/clr encryption attribute. */ - if (!x86_platform.guest.enc_status_change_prepare(addr, numpages, enc)) + ret =3D x86_platform.guest.enc_status_change_prepare(addr, numpages, enc); + if (ret) goto vmm_fail; =20 ret =3D __change_page_attr_set_clr(&cpa, 1); @@ -2174,7 +2175,8 @@ static int __set_memory_enc_pgtable(unsigned long add= r, int numpages, bool enc) return ret; =20 /* Notify hypervisor that we have successfully set/clr encryption attribu= te. */ - if (!x86_platform.guest.enc_status_change_finish(addr, numpages, enc)) + ret =3D x86_platform.guest.enc_status_change_finish(addr, numpages, enc); + if (ret) goto vmm_fail; =20 return 0; @@ -2183,7 +2185,7 @@ static int __set_memory_enc_pgtable(unsigned long add= r, int numpages, bool enc) WARN_ONCE(1, "CPA VMM failure to convert memory (addr=3D%p, numpages=3D%d= ) to %s.\n", (void *)addr, numpages, enc ? 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Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" , Dave Hansen , Tao Liu Subject: [PATCHv10 07/18] x86/mm: Return correct level from lookup_address() if pte is none Date: Tue, 9 Apr 2024 14:29:59 +0300 Message-ID: <20240409113010.465412-8-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> References: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, lookup_address() returns two things: 1. A "pte_t" (which might be a p[g4um]d_t) 2. The 'level' of the page tables where the "pte_t" was found (returned via a pointer) If no pte_t is found, 'level' is essentially garbage. Always fill out the level. For NULL "pte_t"s, fill in the level where the p*d_none() entry was found mirroring the "found" behavior. Always filling out the level allows using lookup_address() to precisely skip over holes when walking kernel page tables. Add one more entry into enum pg_level to indicate the size of the VA covered by one PGD entry in 5-level paging mode. Update comments for lookup_address() and lookup_address_in_pgd() to reflect changes in the interface. Signed-off-by: Kirill A. Shutemov Reviewed-by: Rick Edgecombe Reviewed-by: Baoquan He Reviewed-by: Dave Hansen Tested-by: Tao Liu --- arch/x86/include/asm/pgtable_types.h | 1 + arch/x86/mm/pat/set_memory.c | 16 ++++++++-------- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pg= table_types.h index 0b748ee16b3d..3f648ffdfbe5 100644 --- a/arch/x86/include/asm/pgtable_types.h +++ b/arch/x86/include/asm/pgtable_types.h @@ -548,6 +548,7 @@ enum pg_level { PG_LEVEL_2M, PG_LEVEL_1G, PG_LEVEL_512G, + PG_LEVEL_256T, PG_LEVEL_NUM }; =20 diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c index e5b454036bf3..6c49f69c0368 100644 --- a/arch/x86/mm/pat/set_memory.c +++ b/arch/x86/mm/pat/set_memory.c @@ -657,7 +657,8 @@ static inline pgprot_t verify_rwx(pgprot_t old, pgprot_= t new, unsigned long star =20 /* * Lookup the page table entry for a virtual address in a specific pgd. - * Return a pointer to the entry and the level of the mapping. + * Return a pointer to the entry (or NULL if the entry does not exist) and + * the level of the entry. */ pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long address, unsigned int *level) @@ -666,32 +667,32 @@ pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned lon= g address, pud_t *pud; pmd_t *pmd; =20 - *level =3D PG_LEVEL_NONE; + *level =3D PG_LEVEL_256T; =20 if (pgd_none(*pgd)) return NULL; =20 + *level =3D PG_LEVEL_512G; p4d =3D p4d_offset(pgd, address); if (p4d_none(*p4d)) return NULL; =20 - *level =3D PG_LEVEL_512G; if (p4d_leaf(*p4d) || !p4d_present(*p4d)) return (pte_t *)p4d; =20 + *level =3D PG_LEVEL_1G; pud =3D pud_offset(p4d, address); if (pud_none(*pud)) return NULL; =20 - *level =3D PG_LEVEL_1G; if (pud_leaf(*pud) || !pud_present(*pud)) return (pte_t *)pud; =20 + *level =3D PG_LEVEL_2M; pmd =3D pmd_offset(pud, address); if (pmd_none(*pmd)) return NULL; =20 - *level =3D PG_LEVEL_2M; if (pmd_leaf(*pmd) || !pmd_present(*pmd)) return (pte_t *)pmd; =20 @@ -704,9 +705,8 @@ pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long = address, * Lookup the page table entry for a virtual address. Return a pointer * to the entry and the level of the mapping. * - * Note: We return pud and pmd either when the entry is marked large - * or when the present bit is not set. Otherwise we would return a - * pointer to a nonexisting mapping. + * Note: the function returns p4d, pud or pmd either when the entry is mar= ked + * large or when the present bit is not set. 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Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" , Tao Liu Subject: [PATCHv10 08/18] x86/tdx: Account shared memory Date: Tue, 9 Apr 2024 14:30:00 +0300 Message-ID: <20240409113010.465412-9-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> References: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The kernel will convert all shared memory back to private during kexec. The direct mapping page tables will provide information on which memory is shared. It is extremely important to convert all shared memory. If a page is missed, it will cause the second kernel to crash when it accesses it. Keep track of the number of shared pages. This will allow for cross-checking against the shared information in the direct mapping and reporting if the shared bit is lost. Signed-off-by: Kirill A. Shutemov Reviewed-by: Kai Huang Tested-by: Tao Liu --- arch/x86/coco/tdx/tdx.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index 26fa47db5782..979891e97d83 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -38,6 +38,8 @@ =20 #define TDREPORT_SUBTYPE_0 0 =20 +static atomic_long_t nr_shared; + /* Called from __tdx_hypercall() for unrecoverable failure */ noinstr void __noreturn __tdx_hypercall_failed(void) { @@ -821,6 +823,11 @@ static int tdx_enc_status_change_finish(unsigned long = vaddr, int numpages, if (!enc && !tdx_enc_status_changed(vaddr, numpages, enc)) return -EIO; =20 + if (enc) + atomic_long_sub(numpages, &nr_shared); + else + atomic_long_add(numpages, &nr_shared); + return 0; } =20 --=20 2.43.0 From nobody Sun Feb 8 00:11:49 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA74F12F363 for ; Tue, 9 Apr 2024 11:30:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662235; cv=none; b=JIEmdXiIkvJZ2nSbdmEaUKnvgEe1bbB09IhyzrirPlEcbCq+JLVOGo9jLOMqEIFI82SVwF0+uhGIJcvJNBtGSq+qqIozplrcHVxFS2y/jEbHeDjjTizpR6wNGZpWVS4uR0iIIGWQhinUtqgc3sA765flx5cADQOzYdtrphGRFEM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662235; c=relaxed/simple; bh=nTkqIKFbFNF7KIfvSjwb+TYQAkwBV6/1sk3/m2T/8JA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=m64+0dPHvPFHq5KpZOaetlhMGdWcwboNERVCEp/78LtNKLOORY7rs3ESHUg6nsdyeZ73epqnylL5qFBhGnCIb3ZrgExkuduxx34A+Ta/IIUI8YwTpl5rZUu5FLLZztSxXeZfxsv0dZtXg9aMPbImRk0hg9X5ouH4SFT9yRwp7IA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.helo=mgamail.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=DN+XHNXb; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.helo=mgamail.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="DN+XHNXb" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712662234; x=1744198234; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nTkqIKFbFNF7KIfvSjwb+TYQAkwBV6/1sk3/m2T/8JA=; b=DN+XHNXbSxhXQk/JUm1ptrqYwi15KP7JZmlXmZzK+ijgTFm/Kd9RhFFV hmNBKqJYZzp4xhtF6QuBvN2vrrwmxkxfBvVpeaRTwBL/2Pj1tA9Y1xLhl K+vtV+pS+iS3SfFQEswerQLgP/IQ/YKQQQERXtFKljCh7D25aTYUDKJW3 tfWisr+fo6OolQqS8VP+5Hcr7mWQZJeyfcpM3tIclByp+h2HjPTAzNkRn enjXlXxDKdZAZ9CFwGOwMV12EhvIrFY1cav4WSj78Qy+VE4Szm/Q2HD5n VDuq9+QrwimhljK8yc92OgaRKUj83pMaHO8yfaCFG9oxEYfPrY2gJAyYJ A==; X-CSE-ConnectionGUID: cGXj707XRYuev3T6rXpLlw== X-CSE-MsgGUID: 7W7xph+PSeS+bfDZdRxEPw== X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="30460432" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="30460432" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Apr 2024 04:30:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="937093342" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="937093342" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 09 Apr 2024 04:30:24 -0700 Received: by black.fi.intel.com (Postfix, from userid 1000) id DAE3DBC4; Tue, 9 Apr 2024 14:30:17 +0300 (EEST) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" , Nikolay Borisov , Tao Liu Subject: [PATCHv10 09/18] x86/mm: Adding callbacks to prepare encrypted memory for kexec Date: Tue, 9 Apr 2024 14:30:01 +0300 Message-ID: <20240409113010.465412-10-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> References: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AMD SEV and Intel TDX guests allocate shared buffers for performing I/O. This is done by allocating pages normally from the buddy allocator and then converting them to shared using set_memory_decrypted(). On kexec, the second kernel is unaware of which memory has been converted in this manner. It only sees E820_TYPE_RAM. Accessing shared memory as private is fatal. Therefore, the memory state must be reset to its original state before starting the new kernel with kexec. The process of converting shared memory back to private occurs in two steps: - enc_kexec_stop_conversion() stops new conversions. - enc_kexec_unshare_mem() unshares all existing shared memory, reverting it back to private. Signed-off-by: Kirill A. Shutemov Reviewed-by: Nikolay Borisov x Reviewed-by: Kai Huang Tested-by: Tao Liu --- arch/x86/include/asm/x86_init.h | 2 ++ arch/x86/kernel/crash.c | 6 ++++++ arch/x86/kernel/reboot.c | 12 ++++++++++++ arch/x86/kernel/x86_init.c | 4 ++++ 4 files changed, 24 insertions(+) diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_ini= t.h index 28ac3cb9b987..c731e6bc4343 100644 --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h @@ -155,6 +155,8 @@ struct x86_guest { int (*enc_status_change_finish)(unsigned long vaddr, int npages, bool enc= ); bool (*enc_tlb_flush_required)(bool enc); bool (*enc_cache_flush_required)(void); + void (*enc_kexec_stop_conversion)(bool crash); + void (*enc_kexec_unshare_mem)(void); }; =20 /** diff --git a/arch/x86/kernel/crash.c b/arch/x86/kernel/crash.c index e74d0c4286c1..7a1560d7e62d 100644 --- a/arch/x86/kernel/crash.c +++ b/arch/x86/kernel/crash.c @@ -128,6 +128,12 @@ void native_machine_crash_shutdown(struct pt_regs *reg= s) #ifdef CONFIG_HPET_TIMER hpet_disable(); #endif + + if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT)) { + x86_platform.guest.enc_kexec_stop_conversion(true); + x86_platform.guest.enc_kexec_unshare_mem(); + } + crash_save_cpu(regs, safe_smp_processor_id()); } =20 diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c index f3130f762784..1ec478f40963 100644 --- a/arch/x86/kernel/reboot.c +++ b/arch/x86/kernel/reboot.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -716,6 +717,14 @@ static void native_machine_emergency_restart(void) =20 void native_machine_shutdown(void) { + /* + * Call enc_kexec_stop_conversion() while all CPUs are still active and + * interrupts are enabled. This will allow all in-flight memory + * conversions to finish cleanly. + */ + if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT) && kexec_in_progress) + x86_platform.guest.enc_kexec_stop_conversion(false); + /* Stop the cpus and apics */ #ifdef CONFIG_X86_IO_APIC /* @@ -752,6 +761,9 @@ void native_machine_shutdown(void) #ifdef CONFIG_X86_64 x86_platform.iommu_shutdown(); #endif + + if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT) && kexec_in_progress) + x86_platform.guest.enc_kexec_unshare_mem(); } =20 static void __machine_emergency_restart(int emergency) diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c index a7143bb7dd93..045ce1c70070 100644 --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c @@ -138,6 +138,8 @@ static int enc_status_change_prepare_noop(unsigned long= vaddr, int npages, bool static int enc_status_change_finish_noop(unsigned long vaddr, int npages, = bool enc) { return 0; } static bool enc_tlb_flush_required_noop(bool enc) { return false; } static bool enc_cache_flush_required_noop(void) { return false; } +static void enc_kexec_stop_conversion_noop(bool crash) {} +static void enc_kexec_unshare_mem_noop(void) {} static bool is_private_mmio_noop(u64 addr) {return false; } =20 struct x86_platform_ops x86_platform __ro_after_init =3D { @@ -161,6 +163,8 @@ struct x86_platform_ops x86_platform __ro_after_init = =3D { .enc_status_change_finish =3D enc_status_change_finish_noop, .enc_tlb_flush_required =3D enc_tlb_flush_required_noop, .enc_cache_flush_required =3D enc_cache_flush_required_noop, + .enc_kexec_stop_conversion =3D enc_kexec_stop_conversion_noop, + .enc_kexec_unshare_mem =3D enc_kexec_unshare_mem_noop, }, }; =20 --=20 2.43.0 From nobody Sun Feb 8 00:11:49 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3259312D75A for ; Tue, 9 Apr 2024 11:30:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662234; cv=none; b=YVcGqx63vrEb4+kaLdwTuw6hGskmsK3k2q7gnRjbJNxaIqlwNw3vwyeOV/rLFwHpCHj8/C5DHrHj7c//6X/gdYhAXsuRSNoV6SM8MpuNv6ceajzk22065pk+561ssZjfRij7lnOJ99GCxNk0J54p9YES/zHxHV75ij62cyrKLy0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662234; c=relaxed/simple; bh=a64FQvJDD4gr5bqdxdYkrWENcXNUNDUgRRX0Ht95AlE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=luvONipQdgwFC2oCh0jZM4ERVhOV7Fv4ejOp8upenUsVO0vDqIFlP/4vmGE3cGtkqkRX8O7br97HV/rcwG1fCX7yQHt9matpwOg/324d/NgvDMlCz9eDSjfltYsQPETgQaYnAbndauU7h8iWY5+ITUeGbZzaZ4tDGLTUkDn0dp4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.helo=mgamail.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=VfaKoX/R; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.helo=mgamail.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="VfaKoX/R" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712662232; x=1744198232; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=a64FQvJDD4gr5bqdxdYkrWENcXNUNDUgRRX0Ht95AlE=; b=VfaKoX/RedsqBID0DdR+5FMxbD/DyNHRxMjrdgOLFAFTbiN/Sqbkojew ds/Fvgups6L3dgbif9AV27jYeIjbSFju03e5L+Q6MLqitsRRY4ytiitTj gAjzgfCXG3I2EMkZbQNDfRINBwf/05AzcavtC/XCpKejDoWFdQVe0YCNE 3B1kZSFbGqlNOLgRtr1WcxuyZe5dTXXV6oBik4lhoCp7mUrq4tk0iqERZ DyVjoPg53MY+1iD638oA1NyRvb5u7oFTFKuTEmo5Uv1vCBcl8TrDGjyeX XL0cYzDPx3JDHPuC2/Nd+l0wnV8HfPlDkOVj10FEQQN9Xef/TiVYuQ/Cj Q==; X-CSE-ConnectionGUID: eRTJsV5vQxCixaIxyLVzOw== X-CSE-MsgGUID: /XoqRurzTGeunPBFLmjIVg== X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="30460414" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="30460414" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Apr 2024 04:30:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="937093337" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="937093337" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 09 Apr 2024 04:30:24 -0700 Received: by black.fi.intel.com (Postfix, from userid 1000) id F0AA9D63; Tue, 9 Apr 2024 14:30:17 +0300 (EEST) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" , Tao Liu Subject: [PATCHv10 10/18] x86/tdx: Convert shared memory back to private on kexec Date: Tue, 9 Apr 2024 14:30:02 +0300 Message-ID: <20240409113010.465412-11-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> References: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" TDX guests allocate shared buffers to perform I/O. It is done by allocating pages normally from the buddy allocator and converting them to shared with set_memory_decrypted(). The second kernel has no idea what memory is converted this way. It only sees E820_TYPE_RAM. Accessing shared memory via private mapping is fatal. It leads to unrecoverable TD exit. On kexec walk direct mapping and convert all shared memory back to private. It makes all RAM private again and second kernel may use it normally. The conversion occurs in two steps: stopping new conversions and unsharing all memory. In the case of normal kexec, the stopping of conversions takes place while scheduling is still functioning. This allows for waiting until any ongoing conversions are finished. The second step is carried out when all CPUs except one are inactive and interrupts are disabled. This prevents any conflicts with code that may access shared memory. Signed-off-by: Kirill A. Shutemov Reviewed-by: Rick Edgecombe Reviewed-by: Kai Huang Tested-by: Tao Liu --- arch/x86/coco/tdx/tdx.c | 72 +++++++++++++++++++++++++++++++ arch/x86/include/asm/pgtable.h | 5 +++ arch/x86/include/asm/set_memory.h | 3 ++ arch/x86/mm/pat/set_memory.c | 35 +++++++++++++-- 4 files changed, 112 insertions(+), 3 deletions(-) diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index 979891e97d83..59776ce1c1d7 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -14,6 +15,7 @@ #include #include #include +#include =20 /* MMIO direction */ #define EPT_READ 0 @@ -831,6 +833,73 @@ static int tdx_enc_status_change_finish(unsigned long = vaddr, int numpages, return 0; } =20 +/* Stop new private<->shared conversions */ +static void tdx_kexec_stop_conversion(bool crash) +{ + /* + * Crash kernel reaches here with interrupts disabled: can't wait for + * conversions to finish. + * + * If race happened, just report and proceed. + */ + bool wait_for_lock =3D !crash; + + if (!stop_memory_enc_conversion(wait_for_lock)) + pr_warn("Failed to stop shared<->private conversions\n"); +} + +static void tdx_kexec_unshare_mem(void) +{ + unsigned long addr, end; + long found =3D 0, shared; + + /* + * Walk direct mapping and convert all shared memory back to private, + */ + + addr =3D PAGE_OFFSET; + end =3D PAGE_OFFSET + get_max_mapped(); + + while (addr < end) { + unsigned long size; + unsigned int level; + pte_t *pte; + + pte =3D lookup_address(addr, &level); + size =3D page_level_size(level); + + if (pte && pte_decrypted(*pte)) { + int pages =3D size / PAGE_SIZE; + + /* + * Touching memory with shared bit set triggers implicit + * conversion to shared. + * + * Make sure nobody touches the shared range from + * now on. + */ + set_pte(pte, __pte(0)); + + if (!tdx_enc_status_changed(addr, pages, true)) { + pr_err("Failed to unshare range %#lx-%#lx\n", + addr, addr + size); + } + + found +=3D pages; + } + + addr +=3D size; + } + + __flush_tlb_all(); + + shared =3D atomic_long_read(&nr_shared); + if (shared !=3D found) { + pr_err("shared page accounting is off\n"); + pr_err("nr_shared =3D %ld, nr_found =3D %ld\n", shared, found); + } +} + void __init tdx_early_init(void) { struct tdx_module_args args =3D { @@ -890,6 +959,9 @@ void __init tdx_early_init(void) x86_platform.guest.enc_cache_flush_required =3D tdx_cache_flush_required; x86_platform.guest.enc_tlb_flush_required =3D tdx_tlb_flush_required; =20 + x86_platform.guest.enc_kexec_stop_conversion =3D tdx_kexec_stop_conversio= n; + x86_platform.guest.enc_kexec_unshare_mem =3D tdx_kexec_unshare_mem; + /* * TDX intercepts the RDMSR to read the X2APIC ID in the parallel * bringup low level code. That raises #VE which cannot be handled diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h index 315535ffb258..17f4d97fae06 100644 --- a/arch/x86/include/asm/pgtable.h +++ b/arch/x86/include/asm/pgtable.h @@ -140,6 +140,11 @@ static inline int pte_young(pte_t pte) return pte_flags(pte) & _PAGE_ACCESSED; } =20 +static inline bool pte_decrypted(pte_t pte) +{ + return cc_mkdec(pte_val(pte)) =3D=3D pte_val(pte); +} + #define pmd_dirty pmd_dirty static inline bool pmd_dirty(pmd_t pmd) { diff --git a/arch/x86/include/asm/set_memory.h b/arch/x86/include/asm/set_m= emory.h index 9aee31862b4a..44b6d711296c 100644 --- a/arch/x86/include/asm/set_memory.h +++ b/arch/x86/include/asm/set_memory.h @@ -49,8 +49,11 @@ int set_memory_wb(unsigned long addr, int numpages); int set_memory_np(unsigned long addr, int numpages); int set_memory_p(unsigned long addr, int numpages); int set_memory_4k(unsigned long addr, int numpages); + +bool stop_memory_enc_conversion(bool wait); int set_memory_encrypted(unsigned long addr, int numpages); int set_memory_decrypted(unsigned long addr, int numpages); + int set_memory_np_noalias(unsigned long addr, int numpages); int set_memory_nonglobal(unsigned long addr, int numpages); int set_memory_global(unsigned long addr, int numpages); diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c index 6c49f69c0368..21835339c0e6 100644 --- a/arch/x86/mm/pat/set_memory.c +++ b/arch/x86/mm/pat/set_memory.c @@ -2188,12 +2188,41 @@ static int __set_memory_enc_pgtable(unsigned long a= ddr, int numpages, bool enc) return ret; } =20 +static DECLARE_RWSEM(mem_enc_lock); + +/* + * Stop new private<->shared conversions. + * + * Taking the exclusive mem_enc_lock waits for in-flight conversions to co= mplete. + * The lock is not released to prevent new conversions from being started. + * + * If sleep is not allowed, as in a crash scenario, try to take the lock. + * Failure indicates that there is a race with the conversion. + */ +bool stop_memory_enc_conversion(bool wait) +{ + if (!wait) + return down_write_trylock(&mem_enc_lock); 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09 Apr 2024 04:30:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="937093349" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="937093349" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 09 Apr 2024 04:30:24 -0700 Received: by black.fi.intel.com (Postfix, from userid 1000) id 078D6EA4; Tue, 9 Apr 2024 14:30:18 +0300 (EEST) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" , Dave Hansen , Tao Liu Subject: [PATCHv10 11/18] x86/mm: Make e820_end_ram_pfn() cover E820_TYPE_ACPI ranges Date: Tue, 9 Apr 2024 14:30:03 +0300 Message-ID: <20240409113010.465412-12-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> References: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" e820__end_of_ram_pfn() is used to calculate max_pfn which, among other things, guides where direct mapping ends. Any memory above max_pfn is not going to be present in the direct mapping. e820__end_of_ram_pfn() finds the end of the ram based on the highest E820_TYPE_RAM range. But it doesn't includes E820_TYPE_ACPI ranges into calculation. Despite the name, E820_TYPE_ACPI covers not only ACPI data, but also EFI tables and might be required by kernel to function properly. Usually the problem is hidden because there is some E820_TYPE_RAM memory above E820_TYPE_ACPI. But crashkernel only presents pre-allocated crash memory as E820_TYPE_RAM on boot. If the preallocated range is small, it can fit under the last E820_TYPE_ACPI range. Modify e820__end_of_ram_pfn() and e820__end_of_low_ram_pfn() to cover E820_TYPE_ACPI memory. The problem was discovered during debugging kexec for TDX guest. TDX guest uses E820_TYPE_ACPI to store the unaccepted memory bitmap and pass it between the kernels on kexec. Signed-off-by: Kirill A. Shutemov Reviewed-by: Dave Hansen Tested-by: Tao Liu --- arch/x86/kernel/e820.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c index 6f1b379e3b38..f29969428443 100644 --- a/arch/x86/kernel/e820.c +++ b/arch/x86/kernel/e820.c @@ -827,7 +827,7 @@ u64 __init e820__memblock_alloc_reserved(u64 size, u64 = align) /* * Find the highest page frame number we have available */ -static unsigned long __init e820_end_pfn(unsigned long limit_pfn, enum e82= 0_type type) +static unsigned long __init e820_end_ram_pfn(unsigned long limit_pfn) { int i; unsigned long last_pfn =3D 0; @@ -838,7 +838,8 @@ static unsigned long __init e820_end_pfn(unsigned long = limit_pfn, enum e820_type unsigned long start_pfn; unsigned long end_pfn; =20 - if (entry->type !=3D type) + if (entry->type !=3D E820_TYPE_RAM && + entry->type !=3D E820_TYPE_ACPI) continue; =20 start_pfn =3D entry->addr >> PAGE_SHIFT; @@ -864,12 +865,12 @@ static unsigned long __init e820_end_pfn(unsigned lon= g limit_pfn, enum e820_type =20 unsigned long __init e820__end_of_ram_pfn(void) { - return e820_end_pfn(MAX_ARCH_PFN, E820_TYPE_RAM); + return e820_end_ram_pfn(MAX_ARCH_PFN); } =20 unsigned long __init e820__end_of_low_ram_pfn(void) { - return e820_end_pfn(1UL << (32 - PAGE_SHIFT), E820_TYPE_RAM); + return e820_end_ram_pfn(1UL << (32 - PAGE_SHIFT)); } =20 static void __init early_panic(char *msg) --=20 2.43.0 From nobody Sun Feb 8 00:11:49 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67B8E12D75F for ; Tue, 9 Apr 2024 11:30:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662233; cv=none; b=HmwoqWNPMCwUJ49keKACvj3gyuXS0kJlwy/pXEPC84D3e6CR1EkXuZxJLubePvmLLLRtLuA+JM8CY/TK9GStoHE0FCJ/3KrhNeTLwPz0/bvvMA0hprC98YYaRGKvkalWFXndXjbrvPDO9cGvX497FVFjPf2A2twS0yz7Lj8DrRY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662233; c=relaxed/simple; bh=DBcJsWV4nfgk/8fw3M6vcKnfFbP1zoB1PzLmLNRfgyE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hcZXTqaBlb8zgSq0d562HnXoZhzgsX5O3piC7F38ZaPqZJ0/XC8T0BFGbz4lRY6RwaZ4qvYL7ygAjJchN8L0PirCM5j4ZJmY5PG0vtoHYKChJaQN6rxhyYUqZIxpzsTnTRtW90jRX1YkkJt1bVaTdzLJ2HJva5XzQnEMeWd9Bxw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.helo=mgamail.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=npaABGW3; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.helo=mgamail.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="npaABGW3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712662232; x=1744198232; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DBcJsWV4nfgk/8fw3M6vcKnfFbP1zoB1PzLmLNRfgyE=; b=npaABGW3ZiTiRiQZQ6bPIEc0m0Qn2yApAwArDHHFO/QmzGWJWKytFRkC kGvl2WHp7GDwE73D8HtokeEU6R0Fs+XzCy1iYa/P99N2oQSf5Qhk6C1A7 8/JkF9LSwbCzPvjZw7JJVQD2soRSp2W6h4NVdecCQKDNdfmaCDotBkzy9 h2m9U47CBAe0KWsD0o6QGZbia/v+PS+w7q+B5BnCrYgonUGn8Wiy2o+YV jLpnY2sdFiHGXn7ZfPfkAZvZ/u69lFi4GmbGstBPtwDeA19hoqEYy3mH6 rZMag7EsR6wG+mmIEE3tEV0Ll8ZIZv3b0T+XV2WgTlTgwEwa+dNpdITgK A==; X-CSE-ConnectionGUID: uhmJcgCSSeOBO9mFvx1v0Q== X-CSE-MsgGUID: iU4l+MOkS5KTc36wqfSqBw== X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="30460383" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="30460383" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Apr 2024 04:30:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="937093331" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="937093331" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 09 Apr 2024 04:30:24 -0700 Received: by black.fi.intel.com (Postfix, from userid 1000) id 11CC1C09; Tue, 9 Apr 2024 14:30:18 +0300 (EEST) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A . Shutemov" Subject: [PATCHv10 12/18] x86/mm: Do not zap page table entries mapping unaccepted memory table during kdump. Date: Tue, 9 Apr 2024 14:30:04 +0300 Message-ID: <20240409113010.465412-13-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> References: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ashish Kalra During crashkernel boot only pre-allocated crash memory is presented as E820_TYPE_RAM. This can cause page table entries mapping unaccepted memory table to be zapped during phys_pte_init(), phys_pmd_init(), phys_pud_init() and phys_p4d_init() as SNP/TDX guest use E820_TYPE_ACPI to store the unaccepted memory table and pass it between the kernels on kexec/kdump. E820_TYPE_ACPI covers not only ACPI data, but also EFI tables and might be required by kernel to function properly. The problem was discovered during debugging kdump for SNP guest. The unaccepted memory table stored with E820_TYPE_ACPI and passed between the kernels on kdump was getting zapped as the PMD entry mapping this is above the E820_TYPE_RAM range for the reserved crashkernel memory. Signed-off-by: Ashish Kalra Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/init_64.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c index 7e177856ee4f..28002cc7a37d 100644 --- a/arch/x86/mm/init_64.c +++ b/arch/x86/mm/init_64.c @@ -469,7 +469,9 @@ phys_pte_init(pte_t *pte_page, unsigned long paddr, uns= igned long paddr_end, !e820__mapped_any(paddr & PAGE_MASK, paddr_next, E820_TYPE_RAM) && !e820__mapped_any(paddr & PAGE_MASK, paddr_next, - E820_TYPE_RESERVED_KERN)) + E820_TYPE_RESERVED_KERN) && + !e820__mapped_any(paddr & PAGE_MASK, paddr_next, + E820_TYPE_ACPI)) set_pte_init(pte, __pte(0), init); continue; } @@ -524,7 +526,9 @@ phys_pmd_init(pmd_t *pmd_page, unsigned long paddr, uns= igned long paddr_end, !e820__mapped_any(paddr & PMD_MASK, paddr_next, E820_TYPE_RAM) && !e820__mapped_any(paddr & PMD_MASK, paddr_next, - E820_TYPE_RESERVED_KERN)) + E820_TYPE_RESERVED_KERN) && + !e820__mapped_any(paddr & PMD_MASK, paddr_next, + E820_TYPE_ACPI)) set_pmd_init(pmd, __pmd(0), init); continue; } @@ -611,7 +615,9 @@ phys_pud_init(pud_t *pud_page, unsigned long paddr, uns= igned long paddr_end, !e820__mapped_any(paddr & PUD_MASK, paddr_next, E820_TYPE_RAM) && !e820__mapped_any(paddr & PUD_MASK, paddr_next, - E820_TYPE_RESERVED_KERN)) + E820_TYPE_RESERVED_KERN) && + !e820__mapped_any(paddr & PUD_MASK, paddr_next, + E820_TYPE_ACPI)) set_pud_init(pud, __pud(0), init); continue; } @@ -698,7 +704,9 @@ phys_p4d_init(p4d_t *p4d_page, unsigned long paddr, uns= igned long paddr_end, !e820__mapped_any(paddr & P4D_MASK, paddr_next, E820_TYPE_RAM) && !e820__mapped_any(paddr & P4D_MASK, paddr_next, - E820_TYPE_RESERVED_KERN)) + E820_TYPE_RESERVED_KERN) && + !e820__mapped_any(paddr & P4D_MASK, paddr_next, + E820_TYPE_ACPI)) set_p4d_init(p4d, __p4d(0), init); continue; } --=20 2.43.0 From nobody Sun Feb 8 00:11:49 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 316A512EBCF for ; Tue, 9 Apr 2024 11:30:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662234; cv=none; b=M3pRinGe6ozaqnukbNgc4QuXCw3JtIRvT+cizDLW20goh/oevOPRc2hWzlichPRNZtmxg2CKNwOxBbB/2lZyd5cZ9wuMvkUkKS7Mh2A0QeuvtmQYPtAQD2Ka/F6rcuDon3h9n1hEQsi47RJ3+U0+LeyN9cD8edPW/uG0e62aC7A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662234; c=relaxed/simple; bh=HYQcRDjwuubK7Sq3dwYtItnV9wch/fOBnHCCGhl7Y4M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=I0odMV/mZrRmhvUI5JCTPYThAPcxs28socL74PRfldWqUc7k3uuLOLEjx5GshJ6if9sijIQPVng3gRQ5DcvzgvmTqCO0mPfOoRdZceaGuERTpFvBZV7EUmVFRQydUWp+GJd2It1JnANhW6L81bkorxZmdAUAQLoQnxruk7pp1xw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.helo=mgamail.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=DJtQA9IW; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.helo=mgamail.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="DJtQA9IW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712662234; x=1744198234; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HYQcRDjwuubK7Sq3dwYtItnV9wch/fOBnHCCGhl7Y4M=; b=DJtQA9IWII7AUH6/CaIGR0Ue4fftS6SbzntSzrHa28ReuWYfWnm0Uphs +cgTI/8Gwp4P4pBL2fr8WXJrTMYLfpxDax39F0f6Ng5xcEG5OACCYw/FK irceD0/88hTB0P4E6ZZWo6shVt/vTYPhWAGdjHqSGXJV4KBWYb5yU7jBC 6XtvhyvJN37K/JpnbWQr7jJXj0E02DiMgWRNGffI93DHclPgSnTAV1sLj /bNOlF6pfL1Nhnr+ITLqT53W01+OSSPirhlMJgqa6u3j22qFW2B4aJAaQ l39ZCUKgBus/EVhEQAmAiJqyfm4Fkf4DLcDl9nuPzQl+uPmP7qv+LHXA1 A==; X-CSE-ConnectionGUID: y6d78V13TV29DUUaucehSA== X-CSE-MsgGUID: 5q6VDxF9QKK8R9UYoSrKnQ== X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="30460434" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="30460434" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Apr 2024 04:30:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="937093345" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="937093345" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 09 Apr 2024 04:30:24 -0700 Received: by black.fi.intel.com (Postfix, from userid 1000) id 24CB6F69; Tue, 9 Apr 2024 14:30:18 +0300 (EEST) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" , Tao Liu Subject: [PATCHv10 13/18] x86/acpi: Rename fields in acpi_madt_multiproc_wakeup structure Date: Tue, 9 Apr 2024 14:30:05 +0300 Message-ID: <20240409113010.465412-14-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> References: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To prepare for the addition of support for MADT wakeup structure version 1, it is necessary to provide more appropriate names for the fields in the structure. The field 'mailbox_version' renamed as 'version'. This field signifies the version of the structure and the related protocols, rather than the version of the mailbox. This field has not been utilized in the code thus far. The field 'base_address' renamed as 'mailbox_address' to clarify the kind of address it represents. In version 1, the structure includes the reset vector address. Clear and distinct naming helps to prevent any confusion. Signed-off-by: Kirill A. Shutemov Reviewed-by: Kai Huang Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Thomas Gleixner Tested-by: Tao Liu --- arch/x86/kernel/acpi/madt_wakeup.c | 2 +- include/acpi/actbl2.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/acpi/madt_wakeup.c b/arch/x86/kernel/acpi/madt= _wakeup.c index d222be8d7a07..004801b9b151 100644 --- a/arch/x86/kernel/acpi/madt_wakeup.c +++ b/arch/x86/kernel/acpi/madt_wakeup.c @@ -75,7 +75,7 @@ int __init acpi_parse_mp_wake(union acpi_subtable_headers= *header, =20 acpi_table_print_madt_entry(&header->common); =20 - acpi_mp_wake_mailbox_paddr =3D mp_wake->base_address; + acpi_mp_wake_mailbox_paddr =3D mp_wake->mailbox_address; =20 cpu_hotplug_disable_offlining(); =20 diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index 9775384d61c6..e1a395af7591 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -1117,9 +1117,9 @@ struct acpi_madt_generic_translator { =20 struct acpi_madt_multiproc_wakeup { struct acpi_subtable_header header; - u16 mailbox_version; + u16 version; u32 reserved; /* reserved - must be zero */ - u64 base_address; + u64 mailbox_address; }; =20 #define ACPI_MULTIPROC_WAKEUP_MB_OS_SIZE 2032 --=20 2.43.0 From nobody Sun Feb 8 00:11:49 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBB3A12DDAB for ; Tue, 9 Apr 2024 11:30:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662233; cv=none; b=AqiKhtQT0FoxXZ1XoPa2HxWkUoAetMp51MMzi8q+6/vyq6yzqjeWVRuDY6ZPUPupyVFqvNzR0CrNbcm4i373VYQunIEkizNymAz5AOE/ogVfp9yrp1onAux7pYxJAVfgWT6qOe3x9LhMQDdK6btJSGeIqcNU1shOQNkYZPrlms0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662233; c=relaxed/simple; bh=hHQ9KRFxDt369JBke8P/ZWEer7oQx7aWq4kGcpCYmms=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dtllA4cknNW2EbAhJTwPCwS2dkBKgKpQPFrJKOkC8LqxVziFbM7pud0IaSJZ1W4dK/QeVmgKhwqB1RcGLf+6ZwNZFdc541zvPR7d/asdks20WUtvzHaqq1KK6LFZKMneTE/L57Pci8kc8EMhZ1h3WoPqjd4D5ZybnknxfVf5Dw4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.helo=mgamail.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=BPFpW4zG; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.helo=mgamail.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="BPFpW4zG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712662233; x=1744198233; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hHQ9KRFxDt369JBke8P/ZWEer7oQx7aWq4kGcpCYmms=; b=BPFpW4zGMCn25SxQqnVifv9PaXPssosxt4DQXqSv/pqWLYX/Tv0G/UhN Lu+cXx8tnCkfgSVTVhQOUrv/xFZ4YViPO3OLIuUNm3XPct0MXqb/XvGsF Gm3lmhWg1SANqQ3b6f/IZwJH0egJakBc8+Mh/Zm3okhK4Q1zLlHLr5Dmj nVlltqMV0DcYx99O/ECY42Z2zpU7jJa/9WXLG9CO+3gojdDcEAD/2hqh1 75hX6TYIBllq9a/prYQJe0B3zBAWjREHTy5/jgcoQSrlpo02Sx7dYYXtl OQDhXliA57roGEjjqyBd2iTfQ2VTuqkjdv+o+JPNr0Bz50WNRDieQyObs Q==; X-CSE-ConnectionGUID: 3j5Bhcd/Qlis5cJUsK3BSg== X-CSE-MsgGUID: x/OJsDemS92l9tAd0L/pCA== X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="30460413" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="30460413" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Apr 2024 04:30:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="937093339" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="937093339" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 09 Apr 2024 04:30:24 -0700 Received: by black.fi.intel.com (Postfix, from userid 1000) id 312BA1010; Tue, 9 Apr 2024 14:30:18 +0300 (EEST) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" , Tao Liu Subject: [PATCHv10 14/18] x86/acpi: Do not attempt to bring up secondary CPUs in kexec case Date: Tue, 9 Apr 2024 14:30:06 +0300 Message-ID: <20240409113010.465412-15-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> References: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" ACPI MADT doesn't allow to offline a CPU after it was onlined. This limits kexec: the second kernel won't be able to use more than one CPU. To prevent a kexec kernel from onlining secondary CPUs invalidate the mailbox address in the ACPI MADT wakeup structure which prevents a kexec kernel to use it. This is safe as the booting kernel has the mailbox address cached already and acpi_wakeup_cpu() uses the cached value to bring up the secondary CPUs. Note: This is a Linux specific convention and not covered by the ACPI specification. Signed-off-by: Kirill A. Shutemov Reviewed-by: Kai Huang Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Thomas Gleixner Tested-by: Tao Liu --- arch/x86/kernel/acpi/madt_wakeup.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/acpi/madt_wakeup.c b/arch/x86/kernel/acpi/madt= _wakeup.c index 004801b9b151..30820f9de5af 100644 --- a/arch/x86/kernel/acpi/madt_wakeup.c +++ b/arch/x86/kernel/acpi/madt_wakeup.c @@ -14,6 +14,11 @@ static struct acpi_madt_multiproc_wakeup_mailbox *acpi_m= p_wake_mailbox __ro_afte =20 static int acpi_wakeup_cpu(u32 apicid, unsigned long start_ip) { + if (!acpi_mp_wake_mailbox_paddr) { + pr_warn_once("No MADT mailbox: cannot bringup secondary CPUs. Booting wi= th kexec?\n"); + return -EOPNOTSUPP; + } + /* * Remap mailbox memory only for the first call to acpi_wakeup_cpu(). * @@ -64,6 +69,28 @@ static int acpi_wakeup_cpu(u32 apicid, unsigned long sta= rt_ip) return 0; } =20 +static void acpi_mp_disable_offlining(struct acpi_madt_multiproc_wakeup *m= p_wake) +{ + cpu_hotplug_disable_offlining(); + + /* + * ACPI MADT doesn't allow to offline a CPU after it was onlined. This + * limits kexec: the second kernel won't be able to use more than one CPU. + * + * To prevent a kexec kernel from onlining secondary CPUs invalidate the + * mailbox address in the ACPI MADT wakeup structure which prevents a + * kexec kernel to use it. + * + * This is safe as the booting kernel has the mailbox address cached + * already and acpi_wakeup_cpu() uses the cached value to bring up the + * secondary CPUs. + * + * Note: This is a Linux specific convention and not covered by the + * ACPI specification. + */ + mp_wake->mailbox_address =3D 0; +} + int __init acpi_parse_mp_wake(union acpi_subtable_headers *header, const unsigned long end) { @@ -77,7 +104,7 @@ int __init acpi_parse_mp_wake(union acpi_subtable_header= s *header, =20 acpi_mp_wake_mailbox_paddr =3D mp_wake->mailbox_address; =20 - cpu_hotplug_disable_offlining(); + acpi_mp_disable_offlining(mp_wake); =20 apic_update_callback(wakeup_secondary_cpu_64, acpi_wakeup_cpu); =20 --=20 2.43.0 From nobody Sun Feb 8 00:11:49 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF22C12F586 for ; Tue, 9 Apr 2024 11:30:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662236; cv=none; b=UX7sOEWwI4ODxbZi7JQgOC52Q32fv2ghKK3W2b+sCe5PuvJ3KFmgA9Qi25d9XJbXjd4LwXrhO4bmFVpOsakf81t8U/xypzv60l8w4B1N3JoxdOxd/azdWRlTULp9WEi8iMA6//KKhBcCtn9rbvRij0EzF4R0XHb0RGJv9cRORJQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662236; c=relaxed/simple; bh=H/0XoETYjiBwKYOVVwyFe+gG1mMRMbLkWrG5a87I6pg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pSqi0tjITCMosNhNfEDnFujCCJa0EGBj9inXcxDPN9SmCtU3qlKR77RpyUcrSUcXTDbS5VF/HAqqm96Nf+sautVy9Bb6jGMQR/XVaMimDnNpqbsljPRwV4htnAPJT3OYWmvZ6PDSWNAQ0gSHgGQV0fuDy7aRIZe0vQNcJ5PKOFA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.helo=mgamail.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=TiXzvowx; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.helo=mgamail.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="TiXzvowx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712662235; x=1744198235; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=H/0XoETYjiBwKYOVVwyFe+gG1mMRMbLkWrG5a87I6pg=; b=TiXzvowxLtWe3x1LScse8D0NTCRHoMSUr9gQW0OYyEJV5kGgZ1GrFPU3 +rzpTdmi18E9NCOohbdk4ISh3yiHUjICwgm9vpzIBB1Tntfvip21rzK/Z Qtotk2R1sdzkL7jZ20Wz5EhAH39S2lkq87SkYWpVkSU6Q8ztVnLP0TR3f sBxFTyhcTulKYgRfx5G53NxKP0HCVM60PBs29YehoKi7SsTrt2IjIdKlr Nx54fndsDYePJRM20dmF24JF6s9dG1u33hP4FY3GHdq1Ap4VER+8KKAqA 9N18lsVfclBFQJIPcCf21IcVpxqcFYaJgrQYDTns73ikbIGvKFDg8l1tn Q==; X-CSE-ConnectionGUID: U+sUfOG9Rzm+PJ998NmoMg== X-CSE-MsgGUID: dlVko5BvSbKA+gl7rGeAOg== X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="30460461" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="30460461" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Apr 2024 04:30:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="937093351" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="937093351" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 09 Apr 2024 04:30:29 -0700 Received: by black.fi.intel.com (Postfix, from userid 1000) id 3D2FA1090; Tue, 9 Apr 2024 14:30:18 +0300 (EEST) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" , Tao Liu Subject: [PATCHv10 15/18] x86/smp: Add smp_ops.stop_this_cpu() callback Date: Tue, 9 Apr 2024 14:30:07 +0300 Message-ID: <20240409113010.465412-16-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> References: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If the helper is defined, it is called instead of halt() to stop the CPU at the end of stop_this_cpu() and on crash CPU shutdown. ACPI MADT will use it to hand over the CPU to BIOS in order to be able to wake it up again after kexec. Signed-off-by: Kirill A. Shutemov Acked-by: Kai Huang Reviewed-by: Thomas Gleixner Tested-by: Tao Liu --- arch/x86/include/asm/smp.h | 1 + arch/x86/kernel/process.c | 7 +++++++ arch/x86/kernel/reboot.c | 6 ++++++ 3 files changed, 14 insertions(+) diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h index a35936b512fe..ca073f40698f 100644 --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -35,6 +35,7 @@ struct smp_ops { int (*cpu_disable)(void); void (*cpu_die)(unsigned int cpu); void (*play_dead)(void); + void (*stop_this_cpu)(void); =20 void (*send_call_func_ipi)(const struct cpumask *mask); void (*send_call_func_single_ipi)(int cpu); diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index b8441147eb5e..f63f8fd00a91 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -835,6 +835,13 @@ void __noreturn stop_this_cpu(void *dummy) */ cpumask_clear_cpu(cpu, &cpus_stop_mask); =20 +#ifdef CONFIG_SMP + if (smp_ops.stop_this_cpu) { + smp_ops.stop_this_cpu(); + unreachable(); + } +#endif + for (;;) { /* * Use native_halt() so that memory contents don't change diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c index 1ec478f40963..293ded05a4b0 100644 --- a/arch/x86/kernel/reboot.c +++ b/arch/x86/kernel/reboot.c @@ -880,6 +880,12 @@ static int crash_nmi_callback(unsigned int val, struct= pt_regs *regs) cpu_emergency_disable_virtualization(); =20 atomic_dec(&waiting_for_crash_ipi); + + if (smp_ops.stop_this_cpu) { + smp_ops.stop_this_cpu(); + unreachable(); + } + /* Assume hlt works */ halt(); for (;;) --=20 2.43.0 From nobody Sun Feb 8 00:11:49 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1F9B12F5BD for ; Tue, 9 Apr 2024 11:30:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662238; cv=none; b=ZTRyDFEshH7a+qeE+SZochpHa8Vjt9rlwDVboUyTW9WrAqUEVU43aex8zVq8RSJTwp2sFspgjb74azad9i0loPEu4NCV2vWtpL8H14viiY7skN80Zlxs38Gr7zDQOfQiyhjSU5Zvcz810UwZwDIHkyN60DJPaTTlR0xPnlGeYlA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712662238; c=relaxed/simple; bh=GSg67xlVUPvLYDL37C9OUEs7HbwzTLSXgJBxYPbO+3w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FckhnIsTyAGS7rIoL6XPtpTmEZGiLSeyN9fcX8lvmNDXbFORM8ctfPAxKbBr/eOyJgtvM61naThKIG3Ws+zq7nDF3kel4k8wZUCIxBLqVpCobGYnD8Y/695Thz67TzGdEKIW2kEBuh1jz2fO2u8GFzT2btTf3GNubYJtBWoVEf0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.helo=mgamail.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MEFvKD+H; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.helo=mgamail.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MEFvKD+H" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712662236; x=1744198236; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GSg67xlVUPvLYDL37C9OUEs7HbwzTLSXgJBxYPbO+3w=; b=MEFvKD+HMjoilF+TGSle7uFT2p78kDaJIUjZzOWgiXgEZMRQzRZcMS3S Yg1fhObxRIcgBSS6dUIOjqf1FKpD9EXg8mG8ly0IdbRVU3899swKiWkbj ymwXjvKRS61zhrZPZ6/xc5J4Ps9u8dnRDej/VMNVpcHbU0Kw9jg5BcVY1 LZCHnOiPnpwGM1DF2CMNPuCoIflThbLqAc4iyiYBvTvBAZpX7LYbNyLjv tQ74aSThBqfQCAwmtbalPmxaK0GoEjjlkhUo5mgIOFH+EpQASpX+6v5TS 1sgaCMHiz0i9BXcbFZXXPYhnXx2gyYBJWWQAW/vcwf4TPGc1S5W4BWYE4 Q==; X-CSE-ConnectionGUID: iynFaZHERYudGfOa06T9Og== X-CSE-MsgGUID: esFIDl6QSK2pNriJ+8StVQ== X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="30460472" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="30460472" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Apr 2024 04:30:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="937093353" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="937093353" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 09 Apr 2024 04:30:28 -0700 Received: by black.fi.intel.com (Postfix, from userid 1000) id 43614F46; Tue, 9 Apr 2024 14:30:18 +0300 (EEST) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" , Tao Liu Subject: [PATCHv10 16/18] x86/mm: Introduce kernel_ident_mapping_free() Date: Tue, 9 Apr 2024 14:30:08 +0300 Message-ID: <20240409113010.465412-17-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> References: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The helper complements kernel_ident_mapping_init(): it frees the identity mapping that was previously allocated. It will be used in the error path to free a partially allocated mapping or if the mapping is no longer needed. The caller provides a struct x86_mapping_info with the free_pgd_page() callback hooked up and the pgd_t to free. Signed-off-by: Kirill A. Shutemov Acked-by: Kai Huang Tested-by: Tao Liu --- arch/x86/include/asm/init.h | 3 ++ arch/x86/mm/ident_map.c | 73 +++++++++++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+) diff --git a/arch/x86/include/asm/init.h b/arch/x86/include/asm/init.h index cc9ccf61b6bd..14d72727d7ee 100644 --- a/arch/x86/include/asm/init.h +++ b/arch/x86/include/asm/init.h @@ -6,6 +6,7 @@ =20 struct x86_mapping_info { void *(*alloc_pgt_page)(void *); /* allocate buf for page table */ + void (*free_pgt_page)(void *, void *); /* free buf for page table */ void *context; /* context for alloc_pgt_page */ unsigned long page_flag; /* page flag for PMD or PUD entry */ unsigned long offset; /* ident mapping offset */ @@ -16,4 +17,6 @@ struct x86_mapping_info { int kernel_ident_mapping_init(struct x86_mapping_info *info, pgd_t *pgd_pa= ge, unsigned long pstart, unsigned long pend); =20 +void kernel_ident_mapping_free(struct x86_mapping_info *info, pgd_t *pgd); + #endif /* _ASM_X86_INIT_H */ diff --git a/arch/x86/mm/ident_map.c b/arch/x86/mm/ident_map.c index 968d7005f4a7..3996af7b4abf 100644 --- a/arch/x86/mm/ident_map.c +++ b/arch/x86/mm/ident_map.c @@ -4,6 +4,79 @@ * included by both the compressed kernel and the regular kernel. */ =20 +static void free_pte(struct x86_mapping_info *info, pmd_t *pmd) +{ + pte_t *pte =3D pte_offset_kernel(pmd, 0); + + info->free_pgt_page(pte, info->context); +} + +static void free_pmd(struct x86_mapping_info *info, pud_t *pud) +{ + pmd_t *pmd =3D pmd_offset(pud, 0); + int i; + + for (i =3D 0; i < PTRS_PER_PMD; i++) { + if (!pmd_present(pmd[i])) + continue; + + if (pmd_leaf(pmd[i])) + continue; + + free_pte(info, &pmd[i]); + } + + info->free_pgt_page(pmd, info->context); +} + +static void free_pud(struct x86_mapping_info *info, p4d_t *p4d) +{ + pud_t *pud =3D pud_offset(p4d, 0); + int i; + + for (i =3D 0; i < PTRS_PER_PUD; i++) { + if (!pud_present(pud[i])) + continue; + + if (pud_leaf(pud[i])) + continue; + + free_pmd(info, &pud[i]); + } + + info->free_pgt_page(pud, info->context); +} + +static void free_p4d(struct x86_mapping_info *info, pgd_t *pgd) +{ + p4d_t *p4d =3D p4d_offset(pgd, 0); + int i; + + for (i =3D 0; i < PTRS_PER_P4D; i++) { + if (!p4d_present(p4d[i])) + continue; + + free_pud(info, &p4d[i]); + } + + if (pgtable_l5_enabled()) + info->free_pgt_page(pgd, info->context); +} + +void kernel_ident_mapping_free(struct x86_mapping_info *info, pgd_t *pgd) +{ + int i; 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a="937093357" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="937093357" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 09 Apr 2024 04:30:29 -0700 Received: by black.fi.intel.com (Postfix, from userid 1000) id 545DC160A; Tue, 9 Apr 2024 14:30:18 +0300 (EEST) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" , Tao Liu Subject: [PATCHv10 17/18] x86/acpi: Add support for CPU offlining for ACPI MADT wakeup method Date: Tue, 9 Apr 2024 14:30:09 +0300 Message-ID: <20240409113010.465412-18-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> References: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MADT Multiprocessor Wakeup structure version 1 brings support of CPU offlining: BIOS provides a reset vector where the CPU has to jump to for offlining itself. The new TEST mailbox command can be used to test whether the CPU offlined itself which means the BIOS has control over the CPU and can online it again via the ACPI MADT wakeup method. Add CPU offling support for the ACPI MADT wakeup method by implementing custom cpu_die(), play_dead() and stop_this_cpu() SMP operations. CPU offlining makes is possible to hand over secondary CPUs over kexec, not limiting the second kernel to a single CPU. The change conforms to the approved ACPI spec change proposal. See the Link. Signed-off-by: Kirill A. Shutemov Link: https://lore.kernel.org/all/13356251.uLZWGnKmhe@kreacher Acked-by: Kai Huang Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Thomas Gleixner Tested-by: Tao Liu --- arch/x86/include/asm/acpi.h | 2 + arch/x86/kernel/acpi/Makefile | 2 +- arch/x86/kernel/acpi/madt_playdead.S | 28 ++++ arch/x86/kernel/acpi/madt_wakeup.c | 184 ++++++++++++++++++++++++++- include/acpi/actbl2.h | 15 ++- 5 files changed, 227 insertions(+), 4 deletions(-) create mode 100644 arch/x86/kernel/acpi/madt_playdead.S diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h index 2625b915ae7f..021cafa214c2 100644 --- a/arch/x86/include/asm/acpi.h +++ b/arch/x86/include/asm/acpi.h @@ -81,6 +81,8 @@ union acpi_subtable_headers; int __init acpi_parse_mp_wake(union acpi_subtable_headers *header, const unsigned long end); =20 +void asm_acpi_mp_play_dead(u64 reset_vector, u64 pgd_pa); + /* * Check if the CPU can handle C2 and deeper */ diff --git a/arch/x86/kernel/acpi/Makefile b/arch/x86/kernel/acpi/Makefile index 8c7329c88a75..37b1f28846de 100644 --- a/arch/x86/kernel/acpi/Makefile +++ b/arch/x86/kernel/acpi/Makefile @@ -4,7 +4,7 @@ obj-$(CONFIG_ACPI) +=3D boot.o obj-$(CONFIG_ACPI_SLEEP) +=3D sleep.o wakeup_$(BITS).o obj-$(CONFIG_ACPI_APEI) +=3D apei.o obj-$(CONFIG_ACPI_CPPC_LIB) +=3D cppc.o -obj-$(CONFIG_X86_ACPI_MADT_WAKEUP) +=3D madt_wakeup.o +obj-$(CONFIG_X86_ACPI_MADT_WAKEUP) +=3D madt_wakeup.o madt_playdead.o =20 ifneq ($(CONFIG_ACPI_PROCESSOR),) obj-y +=3D cstate.o diff --git a/arch/x86/kernel/acpi/madt_playdead.S b/arch/x86/kernel/acpi/ma= dt_playdead.S new file mode 100644 index 000000000000..4e498d28cdc8 --- /dev/null +++ b/arch/x86/kernel/acpi/madt_playdead.S @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include +#include +#include +#include + + .text + .align PAGE_SIZE + +/* + * asm_acpi_mp_play_dead() - Hand over control of the CPU to the BIOS + * + * rdi: Address of the ACPI MADT MPWK ResetVector + * rsi: PGD of the identity mapping + */ +SYM_FUNC_START(asm_acpi_mp_play_dead) + /* Turn off global entries. Following CR3 write will flush them. */ + movq %cr4, %rdx + andq $~(X86_CR4_PGE), %rdx + movq %rdx, %cr4 + + /* Switch to identity mapping */ + movq %rsi, %cr3 + + /* Jump to reset vector */ + ANNOTATE_RETPOLINE_SAFE + jmp *%rdi +SYM_FUNC_END(asm_acpi_mp_play_dead) diff --git a/arch/x86/kernel/acpi/madt_wakeup.c b/arch/x86/kernel/acpi/madt= _wakeup.c index 30820f9de5af..6cfe762be28b 100644 --- a/arch/x86/kernel/acpi/madt_wakeup.c +++ b/arch/x86/kernel/acpi/madt_wakeup.c @@ -1,10 +1,19 @@ // SPDX-License-Identifier: GPL-2.0-or-later #include #include +#include #include +#include +#include +#include +#include #include #include +#include +#include +#include #include +#include =20 /* Physical address of the Multiprocessor Wakeup Structure mailbox */ static u64 acpi_mp_wake_mailbox_paddr __ro_after_init; @@ -12,6 +21,154 @@ static u64 acpi_mp_wake_mailbox_paddr __ro_after_init; /* Virtual address of the Multiprocessor Wakeup Structure mailbox */ static struct acpi_madt_multiproc_wakeup_mailbox *acpi_mp_wake_mailbox __r= o_after_init; =20 +static u64 acpi_mp_pgd __ro_after_init; +static u64 acpi_mp_reset_vector_paddr __ro_after_init; + +static void acpi_mp_stop_this_cpu(void) +{ + asm_acpi_mp_play_dead(acpi_mp_reset_vector_paddr, acpi_mp_pgd); +} + +static void acpi_mp_play_dead(void) +{ + play_dead_common(); + asm_acpi_mp_play_dead(acpi_mp_reset_vector_paddr, acpi_mp_pgd); +} + +static void acpi_mp_cpu_die(unsigned int cpu) +{ + u32 apicid =3D per_cpu(x86_cpu_to_apicid, cpu); + unsigned long timeout; + + /* + * Use TEST mailbox command to prove that BIOS got control over + * the CPU before declaring it dead. + * + * BIOS has to clear 'command' field of the mailbox. + */ + acpi_mp_wake_mailbox->apic_id =3D apicid; + smp_store_release(&acpi_mp_wake_mailbox->command, + ACPI_MP_WAKE_COMMAND_TEST); + + /* Don't wait longer than a second. */ + timeout =3D USEC_PER_SEC; + while (READ_ONCE(acpi_mp_wake_mailbox->command) && --timeout) + udelay(1); + + if (!timeout) + pr_err("Failed to hand over CPU %d to BIOS\n", cpu); +} + +/* The argument is required to match type of x86_mapping_info::alloc_pgt_p= age */ +static void __init *alloc_pgt_page(void *dummy) +{ + return memblock_alloc(PAGE_SIZE, PAGE_SIZE); +} + +static void __init free_pgt_page(void *pgt, void *dummy) +{ + return memblock_free(pgt, PAGE_SIZE); +} + +/* + * Make sure asm_acpi_mp_play_dead() is present in the identity mapping at + * the same place as in the kernel page tables. asm_acpi_mp_play_dead() sw= itches + * to the identity mapping and the function has be present at the same spo= t in + * the virtual address space before and after switching page tables. + */ +static int __init init_transition_pgtable(pgd_t *pgd) +{ + pgprot_t prot =3D PAGE_KERNEL_EXEC_NOENC; + unsigned long vaddr, paddr; + p4d_t *p4d; + pud_t *pud; + pmd_t *pmd; + pte_t *pte; + + vaddr =3D (unsigned long)asm_acpi_mp_play_dead; + pgd +=3D pgd_index(vaddr); + if (!pgd_present(*pgd)) { + p4d =3D (p4d_t *)alloc_pgt_page(NULL); + if (!p4d) + return -ENOMEM; + set_pgd(pgd, __pgd(__pa(p4d) | _KERNPG_TABLE)); + } + p4d =3D p4d_offset(pgd, vaddr); + if (!p4d_present(*p4d)) { + pud =3D (pud_t *)alloc_pgt_page(NULL); + if (!pud) + return -ENOMEM; + set_p4d(p4d, __p4d(__pa(pud) | _KERNPG_TABLE)); + } + pud =3D pud_offset(p4d, vaddr); + if (!pud_present(*pud)) { + pmd =3D (pmd_t *)alloc_pgt_page(NULL); + if (!pmd) + return -ENOMEM; + set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE)); + } + pmd =3D pmd_offset(pud, vaddr); + if (!pmd_present(*pmd)) { + pte =3D (pte_t *)alloc_pgt_page(NULL); + if (!pte) + return -ENOMEM; + set_pmd(pmd, __pmd(__pa(pte) | _KERNPG_TABLE)); + } + pte =3D pte_offset_kernel(pmd, vaddr); + + paddr =3D __pa(vaddr); + set_pte(pte, pfn_pte(paddr >> PAGE_SHIFT, prot)); + + return 0; +} + +static int __init acpi_mp_setup_reset(u64 reset_vector) +{ + struct x86_mapping_info info =3D { + .alloc_pgt_page =3D alloc_pgt_page, + .free_pgt_page =3D free_pgt_page, + .page_flag =3D __PAGE_KERNEL_LARGE_EXEC, + .kernpg_flag =3D _KERNPG_TABLE_NOENC, + }; + pgd_t *pgd; + + pgd =3D alloc_pgt_page(NULL); + if (!pgd) + return -ENOMEM; + + for (int i =3D 0; i < nr_pfn_mapped; i++) { + unsigned long mstart, mend; + + mstart =3D pfn_mapped[i].start << PAGE_SHIFT; + mend =3D pfn_mapped[i].end << PAGE_SHIFT; + if (kernel_ident_mapping_init(&info, pgd, mstart, mend)) { + kernel_ident_mapping_free(&info, pgd); + return -ENOMEM; + } + } + + if (kernel_ident_mapping_init(&info, pgd, + PAGE_ALIGN_DOWN(reset_vector), + PAGE_ALIGN(reset_vector + 1))) { + kernel_ident_mapping_free(&info, pgd); + return -ENOMEM; + } + + if (init_transition_pgtable(pgd)) { + kernel_ident_mapping_free(&info, pgd); + return -ENOMEM; + } + + smp_ops.play_dead =3D acpi_mp_play_dead; + smp_ops.stop_this_cpu =3D acpi_mp_stop_this_cpu; + smp_ops.cpu_die =3D acpi_mp_cpu_die; + + acpi_mp_reset_vector_paddr =3D reset_vector; + acpi_mp_pgd =3D __pa(pgd); + + return 0; +} + static int acpi_wakeup_cpu(u32 apicid, unsigned long start_ip) { if (!acpi_mp_wake_mailbox_paddr) { @@ -97,14 +254,37 @@ int __init acpi_parse_mp_wake(union acpi_subtable_head= ers *header, struct acpi_madt_multiproc_wakeup *mp_wake; =20 mp_wake =3D (struct acpi_madt_multiproc_wakeup *)header; - if (BAD_MADT_ENTRY(mp_wake, end)) + + /* + * Cannot use the standard BAD_MADT_ENTRY() to sanity check the @mp_wake + * entry. 'sizeof (struct acpi_madt_multiproc_wakeup)' can be larger + * than the actual size of the MP wakeup entry in ACPI table because the + * 'reset_vector' is only available in the V1 MP wakeup structure. + */ + if (!mp_wake) + return -EINVAL; + if (end - (unsigned long)mp_wake < ACPI_MADT_MP_WAKEUP_SIZE_V0) + return -EINVAL; + if (mp_wake->header.length < ACPI_MADT_MP_WAKEUP_SIZE_V0) return -EINVAL; =20 acpi_table_print_madt_entry(&header->common); =20 acpi_mp_wake_mailbox_paddr =3D mp_wake->mailbox_address; =20 - acpi_mp_disable_offlining(mp_wake); + if (mp_wake->version >=3D ACPI_MADT_MP_WAKEUP_VERSION_V1 && + mp_wake->header.length >=3D ACPI_MADT_MP_WAKEUP_SIZE_V1) { + if (acpi_mp_setup_reset(mp_wake->reset_vector)) { + pr_warn("Failed to setup MADT reset vector\n"); + acpi_mp_disable_offlining(mp_wake); + } + } else { + /* + * CPU offlining requires version 1 of the ACPI MADT wakeup + * structure. + */ + acpi_mp_disable_offlining(mp_wake); + } =20 apic_update_callback(wakeup_secondary_cpu_64, acpi_wakeup_cpu); =20 diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index e1a395af7591..2aedda70ef88 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -1120,8 +1120,20 @@ struct acpi_madt_multiproc_wakeup { u16 version; u32 reserved; /* reserved - must be zero */ u64 mailbox_address; + u64 reset_vector; }; =20 +/* Values for Version field above */ + +enum acpi_madt_multiproc_wakeup_version { + ACPI_MADT_MP_WAKEUP_VERSION_NONE =3D 0, + ACPI_MADT_MP_WAKEUP_VERSION_V1 =3D 1, + ACPI_MADT_MP_WAKEUP_VERSION_RESERVED =3D 2, /* 2 and greater are reserved= */ +}; + +#define ACPI_MADT_MP_WAKEUP_SIZE_V0 16 +#define ACPI_MADT_MP_WAKEUP_SIZE_V1 24 + #define ACPI_MULTIPROC_WAKEUP_MB_OS_SIZE 2032 #define ACPI_MULTIPROC_WAKEUP_MB_FIRMWARE_SIZE 2048 =20 @@ -1134,7 +1146,8 @@ struct acpi_madt_multiproc_wakeup_mailbox { u8 reserved_firmware[ACPI_MULTIPROC_WAKEUP_MB_FIRMWARE_SIZE]; /* reserved= for firmware use */ }; =20 -#define ACPI_MP_WAKE_COMMAND_WAKEUP 1 +#define ACPI_MP_WAKE_COMMAND_WAKEUP 1 +#define ACPI_MP_WAKE_COMMAND_TEST 2 =20 /* 17: CPU Core Interrupt Controller (ACPI 6.5) */ =20 --=20 2.43.0 From nobody Sun Feb 8 00:11:49 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B50B12FB23 for ; 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a="30460483" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="30460483" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Apr 2024 04:30:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,11038"; a="937093355" X-IronPort-AV: E=Sophos;i="6.07,189,1708416000"; d="scan'208";a="937093355" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 09 Apr 2024 04:30:29 -0700 Received: by black.fi.intel.com (Postfix, from userid 1000) id 5F96C16F4; Tue, 9 Apr 2024 14:30:18 +0300 (EEST) From: "Kirill A. Shutemov" To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: "Rafael J. Wysocki" , Peter Zijlstra , Adrian Hunter , Kuppuswamy Sathyanarayanan , Elena Reshetova , Jun Nakajima , Rick Edgecombe , Tom Lendacky , "Kalra, Ashish" , Sean Christopherson , "Huang, Kai" , Baoquan He , kexec@lists.infradead.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" , Tao Liu Subject: [PATCHv10 18/18] ACPI: tables: Print MULTIPROC_WAKEUP when MADT is parsed Date: Tue, 9 Apr 2024 14:30:10 +0300 Message-ID: <20240409113010.465412-19-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> References: <20240409113010.465412-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When MADT is parsed, print MULTIPROC_WAKEUP information: ACPI: MP Wakeup (version[1], mailbox[0x7fffd000], reset[0x7fffe068]) This debug information will be very helpful during bring up. Signed-off-by: Kirill A. Shutemov Reviewed-by: Baoquan He Reviewed-by: Kuppuswamy Sathyanarayanan Acked-by: Kai Huang Tested-by: Tao Liu --- drivers/acpi/tables.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/acpi/tables.c b/drivers/acpi/tables.c index b976e5fc3fbc..9e1b01c35070 100644 --- a/drivers/acpi/tables.c +++ b/drivers/acpi/tables.c @@ -198,6 +198,20 @@ void acpi_table_print_madt_entry(struct acpi_subtable_= header *header) } break; =20 + case ACPI_MADT_TYPE_MULTIPROC_WAKEUP: + { + struct acpi_madt_multiproc_wakeup *p =3D + (struct acpi_madt_multiproc_wakeup *)header; + u64 reset_vector =3D 0; + + if (p->version >=3D ACPI_MADT_MP_WAKEUP_VERSION_V1) + reset_vector =3D p->reset_vector; + + pr_debug("MP Wakeup (version[%d], mailbox[%#llx], reset[%#llx])\n", + p->version, p->mailbox_address, reset_vector); + } + break; + case ACPI_MADT_TYPE_CORE_PIC: { struct acpi_madt_core_pic *p =3D (struct acpi_madt_core_pic *)header; --=20 2.43.0