From nobody Mon Feb 9 02:10:03 2026 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C478C25570; Mon, 8 Apr 2024 22:51:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712616674; cv=none; b=rp13k4IZHOQScLO4P0rMXFpTlUS20IU1th43EKP27rZnB++qGD8I8BWUXo0xBaTuTMrglhYtO12gScBgSA3zkAqUC2eSJM/vA9tn7iZXO5NsVA11qa/piuNhQN2iJivGENGNd1PiXAsg5ukFP+hiqn1/fc8Gi2Jii4eOdDIMi5M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712616674; c=relaxed/simple; bh=ev+tQTr8gTQ2A1HrDcPurjzutrjaEUDxOmoQnwQqNLg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tfcJCPVD9eXYYTdgKDC8H/qNnzRXqjgEBIv39vEMwv34CV3bVLdsVBXs1XV3sdiYP/Oc6CMruo+fHvBghSvgHGPI7rihB0W90ONP6etY3RypggIa4WPDPHcv5jvWQWy7MsTdfJ2WqQjizJK431su4hW+d7IqJz2ChA8i+/IC32Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=P1ruVL0s; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="P1ruVL0s" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1712616670; bh=ev+tQTr8gTQ2A1HrDcPurjzutrjaEUDxOmoQnwQqNLg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=P1ruVL0slV7WpN8Hw7KU5BRFqHZL1ahW6UdWeDRtk0aIQOr9+HB95bpMWTdUPWLX7 VBLn3meCDKSiKDww7vnjElKojLHFFXKEzur66Zt+yrLXLpszhDrW+E3e5xl5OEHLgF QIXRgYb4DiTSlszmQFrfqXiXVO98HO1CM7X+saBXxvELOlY2kyK1J/uj2fa3CAYsa0 ZuN9kBCHaM3zmpim190HU1SAWC4fteVNuhfAJESUjHptjX4tGlTz7tpiTakoSpmkis DZrT32VLbM2cthgcHNpmQmQcHbFvTKVxq+kRsHUt6oUTccrFKsjjQTUoeQOFhLcMPF Yh16fI2H1T5pQ== Received: from jupiter.universe (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 9E5AB37820A4; Mon, 8 Apr 2024 22:51:10 +0000 (UTC) Received: by jupiter.universe (Postfix, from userid 1000) id 3B3534800CB; Tue, 9 Apr 2024 00:51:10 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , linux-rockchip@lists.infradead.org, linux-phy@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Wang , Kever Yang , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com, Conor Dooley Subject: [PATCH v5 01/10] dt-bindings: phy: add rockchip usbdp combo phy document Date: Tue, 9 Apr 2024 00:50:28 +0200 Message-ID: <20240408225109.128953-2-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240408225109.128953-1-sebastian.reichel@collabora.com> References: <20240408225109.128953-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree binding document for Rockchip USBDP Combo PHY with Samsung IP block. Co-developed-by: Frank Wang Signed-off-by: Frank Wang Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner Signed-off-by: Sebastian Reichel --- .../bindings/phy/phy-rockchip-usbdp.yaml | 148 ++++++++++++++++++ 1 file changed, 148 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-usbd= p.yaml diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml = b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml new file mode 100644 index 000000000000..1f1f8863b80d --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip USBDP Combo PHY with Samsung IP block + +maintainers: + - Frank Wang + - Zhang Yubing + +properties: + compatible: + enum: + - rockchip,rk3588-usbdp-phy + + reg: + maxItems: 1 + + "#phy-cells": + description: | + Cell allows setting the type of the PHY. Possible values are: + - PHY_TYPE_USB3 + - PHY_TYPE_DP + const: 1 + + clocks: + maxItems: 4 + + clock-names: + items: + - const: refclk + - const: immortal + - const: pclk + - const: utmi + + resets: + maxItems: 5 + + reset-names: + items: + - const: init + - const: cmn + - const: lane + - const: pcs_apb + - const: pma_apb + + rockchip,dp-lane-mux: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 4 + items: + maximum: 3 + description: + An array of physical Type-C lanes indexes. Position of an entry + determines the DisplayPort (DP) lane index, while the value of an en= try + indicates physical Type-C lane. The supported DP lanes number are 2 = or 4. + e.g. for 2 lanes DP lanes map, we could have "rockchip,dp-lane-mux = =3D <2, + 3>;", assuming DP lane0 on Type-C phy lane2, DP lane1 on Type-C phy + lane3. For 4 lanes DP lanes map, we could have "rockchip,dp-lane-mux= =3D + <0, 1, 2, 3>;", assuming DP lane0 on Type-C phy lane0, DP lane1 on T= ype-C + phy lane1, DP lane2 on Type-C phy lane2, DP lane3 on Type-C phy lane= 3. If + DP lanes are mapped by DisplayPort Alt mode, this property is not ne= eded. + + rockchip,u2phy-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the 'usb2 phy general register files'. + + rockchip,usb-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the 'usb general register files'. + + rockchip,usbdpphy-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the 'usbdp phy general register files= '. + + rockchip,vo-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the 'video output general register fi= les'. + When select the DP lane mapping will request its phandle. + + sbu1-dc-gpios: + description: + GPIO connected to the SBU1 line of the USB-C connector via a big res= istor + (~100K) to apply a DC offset for signalling the connector orientatio= n. + maxItems: 1 + + sbu2-dc-gpios: + description: + GPIO connected to the SBU2 line of the USB-C connector via a big res= istor + (~100K) to apply a DC offset for signalling the connector orientatio= n. + maxItems: 1 + + orientation-switch: + description: Flag the port as possible handler of orientation switching + type: boolean + + mode-switch: + description: Flag the port as possible handler of altmode switching + type: boolean + + port: + $ref: /schemas/graph.yaml#/properties/port + description: + A port node to link the PHY to a TypeC controller for the purpose of + handling orientation switching. + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + usbdp_phy0: phy@fed80000 { + compatible =3D "rockchip,rk3588-usbdp-phy"; + reg =3D <0xfed80000 0x10000>; + #phy-cells =3D <1>; + clocks =3D <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY0_IMMORTAL>, + <&cru PCLK_USBDPPHY0>, + <&u2phy0>; + clock-names =3D "refclk", "immortal", "pclk", "utmi"; + resets =3D <&cru SRST_USBDP_COMBO_PHY0_INIT>, + <&cru SRST_USBDP_COMBO_PHY0_CMN>, + <&cru SRST_USBDP_COMBO_PHY0_LANE>, + <&cru SRST_USBDP_COMBO_PHY0_PCS>, + <&cru SRST_P_USBDPPHY0>; + reset-names =3D "init", "cmn", "lane", "pcs_apb", "pma_apb"; + rockchip,u2phy-grf =3D <&usb2phy0_grf>; + rockchip,usb-grf =3D <&usb_grf>; + rockchip,usbdpphy-grf =3D <&usbdpphy0_grf>; + rockchip,vo-grf =3D <&vo0_grf>; + }; --=20 2.43.0 From nobody Mon Feb 9 02:10:03 2026 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48EE52744B; Mon, 8 Apr 2024 22:51:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 8 Apr 2024 22:51:10 +0000 (UTC) Received: by jupiter.universe (Postfix, from userid 1000) id 3DE794800CF; Tue, 9 Apr 2024 00:51:10 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , linux-rockchip@lists.infradead.org, linux-phy@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Wang , Kever Yang , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com, Zhang Yubing Subject: [PATCH v5 02/10] phy: rockchip: add usbdp combo phy driver Date: Tue, 9 Apr 2024 00:50:29 +0200 Message-ID: <20240408225109.128953-3-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240408225109.128953-1-sebastian.reichel@collabora.com> References: <20240408225109.128953-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds a new USBDP combo PHY with Samsung IP block driver. The driver get lane mux and mapping info in 2 ways, supporting DisplayPort alternate mode or parsing from DT. When parsing from DT, the property "rockchip,dp-lane-mux" provide the DP mux and mapping info. This is needed when the PHY is not used with TypeC Alt-Mode. For example if the USB3 interface of the PHY is connected to a USB Type A connector and the DP interface is connected to a DisplayPort connector. When do DP link training, need to set lane number, link rate, swing, and pre-emphasis via PHY configure interface. Co-developed-by: Heiko Stuebner Signed-off-by: Heiko Stuebner Co-developed-by: Zhang Yubing Signed-off-by: Zhang Yubing Co-developed-by: Frank Wang Signed-off-by: Frank Wang Signed-off-by: Sebastian Reichel --- drivers/phy/rockchip/Kconfig | 12 + drivers/phy/rockchip/Makefile | 1 + drivers/phy/rockchip/phy-rockchip-usbdp.c | 1608 +++++++++++++++++++++ 3 files changed, 1621 insertions(+) create mode 100644 drivers/phy/rockchip/phy-rockchip-usbdp.c diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index a34f67bb7e61..c3d62243b474 100644 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig @@ -115,3 +115,15 @@ config PHY_ROCKCHIP_USB select GENERIC_PHY help Enable this to support the Rockchip USB 2.0 PHY. + +config PHY_ROCKCHIP_USBDP + tristate "Rockchip USBDP COMBO PHY Driver" + depends on ARCH_ROCKCHIP && OF + select GENERIC_PHY + select TYPEC + help + Enable this to support the Rockchip USB3.0/DP combo PHY with + Samsung IP block. This is required for USB3 support on RK3588. + + To compile this driver as a module, choose M here: the module + will be called phy-rockchip-usbdp diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile index 3d911304e654..010a824e32ce 100644 --- a/drivers/phy/rockchip/Makefile +++ b/drivers/phy/rockchip/Makefile @@ -12,3 +12,4 @@ obj-$(CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX) +=3D phy-rockchi= p-samsung-hdptx.o obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) +=3D phy-rockchip-snps-pcie3.o obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) +=3D phy-rockchip-typec.o obj-$(CONFIG_PHY_ROCKCHIP_USB) +=3D phy-rockchip-usb.o +obj-$(CONFIG_PHY_ROCKCHIP_USBDP) +=3D phy-rockchip-usbdp.o diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockch= ip/phy-rockchip-usbdp.c new file mode 100644 index 000000000000..32f306459182 --- /dev/null +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c @@ -0,0 +1,1608 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Rockchip USBDP Combo PHY with Samsung IP block driver + * + * Copyright (C) 2021-2024 Rockchip Electronics Co., Ltd + * Copyright (C) 2024 Collabora Ltd + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* USBDP PHY Register Definitions */ +#define UDPHY_PCS 0x4000 +#define UDPHY_PMA 0x8000 + +/* VO0 GRF Registers */ +#define DP_SINK_HPD_CFG BIT(11) +#define DP_SINK_HPD_SEL BIT(10) +#define DP_AUX_DIN_SEL BIT(9) +#define DP_AUX_DOUT_SEL BIT(8) +#define DP_LANE_SEL_N(n) GENMASK(2 * (n) + 1, 2 * (n)) +#define DP_LANE_SEL_ALL GENMASK(7, 0) + +/* PMA CMN Registers */ +#define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */ +#define CMN_DP_LANE_MUX_N(n) BIT((n) + 4) +#define CMN_DP_LANE_EN_N(n) BIT(n) +#define CMN_DP_LANE_MUX_ALL GENMASK(7, 4) +#define CMN_DP_LANE_EN_ALL GENMASK(3, 0) + +#define CMN_DP_LINK_OFFSET 0x28c /* cmn_reg00A3 */ +#define CMN_DP_TX_LINK_BW GENMASK(6, 5) +#define CMN_DP_TX_LANE_SWAP_EN BIT(2) + +#define CMN_SSC_EN_OFFSET 0x2d0 /* cmn_reg00B4 */ +#define CMN_ROPLL_SSC_EN BIT(1) +#define CMN_LCPLL_SSC_EN BIT(0) + +#define CMN_ANA_LCPLL_DONE_OFFSET 0x0350 /* cmn_reg00D4 */ +#define CMN_ANA_LCPLL_LOCK_DONE BIT(7) +#define CMN_ANA_LCPLL_AFC_DONE BIT(6) + +#define CMN_ANA_ROPLL_DONE_OFFSET 0x0354 /* cmn_reg00D5 */ +#define CMN_ANA_ROPLL_LOCK_DONE BIT(1) +#define CMN_ANA_ROPLL_AFC_DONE BIT(0) + +#define CMN_DP_RSTN_OFFSET 0x038c /* cmn_reg00E3 */ +#define CMN_DP_INIT_RSTN BIT(3) +#define CMN_DP_CMN_RSTN BIT(2) +#define CMN_CDR_WTCHDG_EN BIT(1) +#define CMN_CDR_WTCHDG_MSK_CDR_EN BIT(0) + +#define TRSV_ANA_TX_CLK_OFFSET_N(n) (0x854 + (n) * 0x800) /* trsv_reg0215= */ +#define LN_ANA_TX_SER_TXCLK_INV BIT(1) + +#define TRSV_LN0_MON_RX_CDR_DONE_OFFSET 0x0b84 /* trsv_reg02E1 */ +#define TRSV_LN0_MON_RX_CDR_LOCK_DONE BIT(0) + +#define TRSV_LN2_MON_RX_CDR_DONE_OFFSET 0x1b84 /* trsv_reg06E1 */ +#define TRSV_LN2_MON_RX_CDR_LOCK_DONE BIT(0) + +#define BIT_WRITEABLE_SHIFT 16 +#define PHY_AUX_DP_DATA_POL_NORMAL 0 +#define PHY_AUX_DP_DATA_POL_INVERT 1 +#define PHY_LANE_MUX_USB 0 +#define PHY_LANE_MUX_DP 1 + +enum { + DP_BW_RBR, + DP_BW_HBR, + DP_BW_HBR2, + DP_BW_HBR3, +}; + +enum { + UDPHY_MODE_NONE =3D 0, + UDPHY_MODE_USB =3D BIT(0), + UDPHY_MODE_DP =3D BIT(1), + UDPHY_MODE_DP_USB =3D BIT(1) | BIT(0), +}; + +struct rk_udphy_grf_reg { + unsigned int offset; + unsigned int disable; + unsigned int enable; +}; + +#define _RK_UDPHY_GEN_GRF_REG(offset, mask, disable, enable) \ +{\ + offset, \ + FIELD_PREP_CONST(mask, disable) | (mask << BIT_WRITEABLE_SHIFT), \ + FIELD_PREP_CONST(mask, enable) | (mask << BIT_WRITEABLE_SHIFT), \ +} + +#define RK_UDPHY_GEN_GRF_REG(offset, bitend, bitstart, disable, enable) \ + _RK_UDPHY_GEN_GRF_REG(offset, GENMASK(bitend, bitstart), disable, enable) + +struct rk_udphy_grf_cfg { + /* u2phy-grf */ + struct rk_udphy_grf_reg bvalid_phy_con; + struct rk_udphy_grf_reg bvalid_grf_con; + + /* usb-grf */ + struct rk_udphy_grf_reg usb3otg0_cfg; + struct rk_udphy_grf_reg usb3otg1_cfg; + + /* usbdpphy-grf */ + struct rk_udphy_grf_reg low_pwrn; + struct rk_udphy_grf_reg rx_lfps; +}; + +struct rk_udphy_vogrf_cfg { + /* vo-grf */ + struct rk_udphy_grf_reg hpd_trigger; + u32 dp_lane_reg; +}; + +struct rk_udphy_dp_tx_drv_ctrl { + u32 trsv_reg0204; + u32 trsv_reg0205; + u32 trsv_reg0206; + u32 trsv_reg0207; +}; + +struct rk_udphy_cfg { + unsigned int num_phys; + unsigned int phy_ids[2]; + /* resets to be requested */ + const char * const *rst_list; + int num_rsts; + + struct rk_udphy_grf_cfg grfcfg; + struct rk_udphy_vogrf_cfg vogrfcfg[2]; + const struct rk_udphy_dp_tx_drv_ctrl (*dp_tx_ctrl_cfg[4])[4]; + const struct rk_udphy_dp_tx_drv_ctrl (*dp_tx_ctrl_cfg_typec[4])[4]; +}; + +struct rk_udphy { + struct device *dev; + struct regmap *pma_regmap; + struct regmap *u2phygrf; + struct regmap *udphygrf; + struct regmap *usbgrf; + struct regmap *vogrf; + struct typec_switch_dev *sw; + struct typec_mux_dev *mux; + struct mutex mutex; /* mutex to protect access to individual PHYs */ + + /* clocks and rests */ + int num_clks; + struct clk_bulk_data *clks; + struct clk *refclk; + int num_rsts; + struct reset_control_bulk_data *rsts; + + /* PHY status management */ + bool flip; + bool mode_change; + u8 mode; + u8 status; + + /* utilized for USB */ + bool hs; /* flag for high-speed */ + + /* utilized for DP */ + struct gpio_desc *sbu1_dc_gpio; + struct gpio_desc *sbu2_dc_gpio; + u32 lane_mux_sel[4]; + u32 dp_lane_sel[4]; + u32 dp_aux_dout_sel; + u32 dp_aux_din_sel; + bool dp_sink_hpd_sel; + bool dp_sink_hpd_cfg; + u8 bw; + int id; + + bool dp_in_use; + + /* PHY const config */ + const struct rk_udphy_cfg *cfgs; + + /* PHY devices */ + struct phy *phy_dp; + struct phy *phy_u3; +}; + +static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr[= 4][4] =3D { + /* voltage swing 0, pre-emphasis 0->3 */ + { + { 0x20, 0x10, 0x42, 0xe5 }, + { 0x26, 0x14, 0x42, 0xe5 }, + { 0x29, 0x18, 0x42, 0xe5 }, + { 0x2b, 0x1c, 0x43, 0xe7 }, + }, + + /* voltage swing 1, pre-emphasis 0->2 */ + { + { 0x23, 0x10, 0x42, 0xe7 }, + { 0x2a, 0x17, 0x43, 0xe7 }, + { 0x2b, 0x1a, 0x43, 0xe7 }, + }, + + /* voltage swing 2, pre-emphasis 0->1 */ + { + { 0x27, 0x10, 0x42, 0xe7 }, + { 0x2b, 0x17, 0x43, 0xe7 }, + }, + + /* voltage swing 3, pre-emphasis 0 */ + { + { 0x29, 0x10, 0x43, 0xe7 }, + }, +}; + +static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr_= typec[4][4] =3D { + /* voltage swing 0, pre-emphasis 0->3 */ + { + { 0x20, 0x10, 0x42, 0xe5 }, + { 0x26, 0x14, 0x42, 0xe5 }, + { 0x29, 0x18, 0x42, 0xe5 }, + { 0x2b, 0x1c, 0x43, 0xe7 }, + }, + + /* voltage swing 1, pre-emphasis 0->2 */ + { + { 0x23, 0x10, 0x42, 0xe7 }, + { 0x2a, 0x17, 0x43, 0xe7 }, + { 0x2b, 0x1a, 0x43, 0xe7 }, + }, + + /* voltage swing 2, pre-emphasis 0->1 */ + { + { 0x27, 0x10, 0x43, 0x67 }, + { 0x2b, 0x17, 0x43, 0xe7 }, + }, + + /* voltage swing 3, pre-emphasis 0 */ + { + { 0x29, 0x10, 0x43, 0xe7 }, + }, +}; + +static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr2[4][= 4] =3D { + /* voltage swing 0, pre-emphasis 0->3 */ + { + { 0x21, 0x10, 0x42, 0xe5 }, + { 0x26, 0x14, 0x42, 0xe5 }, + { 0x26, 0x16, 0x43, 0xe5 }, + { 0x2a, 0x19, 0x43, 0xe7 }, + }, + + /* voltage swing 1, pre-emphasis 0->2 */ + { + { 0x24, 0x10, 0x42, 0xe7 }, + { 0x2a, 0x17, 0x43, 0xe7 }, + { 0x2b, 0x1a, 0x43, 0xe7 }, + }, + + /* voltage swing 2, pre-emphasis 0->1 */ + { + { 0x28, 0x10, 0x42, 0xe7 }, + { 0x2b, 0x17, 0x43, 0xe7 }, + }, + + /* voltage swing 3, pre-emphasis 0 */ + { + { 0x28, 0x10, 0x43, 0xe7 }, + }, +}; + +static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr3[4][= 4] =3D { + /* voltage swing 0, pre-emphasis 0->3 */ + { + { 0x21, 0x10, 0x42, 0xe5 }, + { 0x26, 0x14, 0x42, 0xe5 }, + { 0x26, 0x16, 0x43, 0xe5 }, + { 0x29, 0x18, 0x43, 0xe7 }, + }, + + /* voltage swing 1, pre-emphasis 0->2 */ + { + { 0x24, 0x10, 0x42, 0xe7 }, + { 0x2a, 0x18, 0x43, 0xe7 }, + { 0x2b, 0x1b, 0x43, 0xe7 } + }, + + /* voltage swing 2, pre-emphasis 0->1 */ + { + { 0x27, 0x10, 0x42, 0xe7 }, + { 0x2b, 0x18, 0x43, 0xe7 } + }, + + /* voltage swing 3, pre-emphasis 0 */ + { + { 0x28, 0x10, 0x43, 0xe7 }, + }, +}; + +static const struct reg_sequence rk_udphy_24m_refclk_cfg[] =3D { + {0x0090, 0x68}, {0x0094, 0x68}, + {0x0128, 0x24}, {0x012c, 0x44}, + {0x0130, 0x3f}, {0x0134, 0x44}, + {0x015c, 0xa9}, {0x0160, 0x71}, + {0x0164, 0x71}, {0x0168, 0xa9}, + {0x0174, 0xa9}, {0x0178, 0x71}, + {0x017c, 0x71}, {0x0180, 0xa9}, + {0x018c, 0x41}, {0x0190, 0x00}, + {0x0194, 0x05}, {0x01ac, 0x2a}, + {0x01b0, 0x17}, {0x01b4, 0x17}, + {0x01b8, 0x2a}, {0x01c8, 0x04}, + {0x01cc, 0x08}, {0x01d0, 0x08}, + {0x01d4, 0x04}, {0x01d8, 0x20}, + {0x01dc, 0x01}, {0x01e0, 0x09}, + {0x01e4, 0x03}, {0x01f0, 0x29}, + {0x01f4, 0x02}, {0x01f8, 0x02}, + {0x01fc, 0x29}, {0x0208, 0x2a}, + {0x020c, 0x17}, {0x0210, 0x17}, + {0x0214, 0x2a}, {0x0224, 0x20}, + {0x03f0, 0x0a}, {0x03f4, 0x07}, + {0x03f8, 0x07}, {0x03fc, 0x0c}, + {0x0404, 0x12}, {0x0408, 0x1a}, + {0x040c, 0x1a}, {0x0410, 0x3f}, + {0x0ce0, 0x68}, {0x0ce8, 0xd0}, + {0x0cf0, 0x87}, {0x0cf8, 0x70}, + {0x0d00, 0x70}, {0x0d08, 0xa9}, + {0x1ce0, 0x68}, {0x1ce8, 0xd0}, + {0x1cf0, 0x87}, {0x1cf8, 0x70}, + {0x1d00, 0x70}, {0x1d08, 0xa9}, + {0x0a3c, 0xd0}, {0x0a44, 0xd0}, + {0x0a48, 0x01}, {0x0a4c, 0x0d}, + {0x0a54, 0xe0}, {0x0a5c, 0xe0}, + {0x0a64, 0xa8}, {0x1a3c, 0xd0}, + {0x1a44, 0xd0}, {0x1a48, 0x01}, + {0x1a4c, 0x0d}, {0x1a54, 0xe0}, + {0x1a5c, 0xe0}, {0x1a64, 0xa8} +}; + +static const struct reg_sequence rk_udphy_26m_refclk_cfg[] =3D { + {0x0830, 0x07}, {0x085c, 0x80}, + {0x1030, 0x07}, {0x105c, 0x80}, + {0x1830, 0x07}, {0x185c, 0x80}, + {0x2030, 0x07}, {0x205c, 0x80}, + {0x0228, 0x38}, {0x0104, 0x44}, + {0x0248, 0x44}, {0x038c, 0x02}, + {0x0878, 0x04}, {0x1878, 0x04}, + {0x0898, 0x77}, {0x1898, 0x77}, + {0x0054, 0x01}, {0x00e0, 0x38}, + {0x0060, 0x24}, {0x0064, 0x77}, + {0x0070, 0x76}, {0x0234, 0xe8}, + {0x0af4, 0x15}, {0x1af4, 0x15}, + {0x081c, 0xe5}, {0x181c, 0xe5}, + {0x099c, 0x48}, {0x199c, 0x48}, + {0x09a4, 0x07}, {0x09a8, 0x22}, + {0x19a4, 0x07}, {0x19a8, 0x22}, + {0x09b8, 0x3e}, {0x19b8, 0x3e}, + {0x09e4, 0x02}, {0x19e4, 0x02}, + {0x0a34, 0x1e}, {0x1a34, 0x1e}, + {0x0a98, 0x2f}, {0x1a98, 0x2f}, + {0x0c30, 0x0e}, {0x0c48, 0x06}, + {0x1c30, 0x0e}, {0x1c48, 0x06}, + {0x028c, 0x18}, {0x0af0, 0x00}, + {0x1af0, 0x00} +}; + +static const struct reg_sequence rk_udphy_init_sequence[] =3D { + {0x0104, 0x44}, {0x0234, 0xe8}, + {0x0248, 0x44}, {0x028c, 0x18}, + {0x081c, 0xe5}, {0x0878, 0x00}, + {0x0994, 0x1c}, {0x0af0, 0x00}, + {0x181c, 0xe5}, {0x1878, 0x00}, + {0x1994, 0x1c}, {0x1af0, 0x00}, + {0x0428, 0x60}, {0x0d58, 0x33}, + {0x1d58, 0x33}, {0x0990, 0x74}, + {0x0d64, 0x17}, {0x08c8, 0x13}, + {0x1990, 0x74}, {0x1d64, 0x17}, + {0x18c8, 0x13}, {0x0d90, 0x40}, + {0x0da8, 0x40}, {0x0dc0, 0x40}, + {0x0dd8, 0x40}, {0x1d90, 0x40}, + {0x1da8, 0x40}, {0x1dc0, 0x40}, + {0x1dd8, 0x40}, {0x03c0, 0x30}, + {0x03c4, 0x06}, {0x0e10, 0x00}, + {0x1e10, 0x00}, {0x043c, 0x0f}, + {0x0d2c, 0xff}, {0x1d2c, 0xff}, + {0x0d34, 0x0f}, {0x1d34, 0x0f}, + {0x08fc, 0x2a}, {0x0914, 0x28}, + {0x0a30, 0x03}, {0x0e38, 0x03}, + {0x0ecc, 0x27}, {0x0ed0, 0x22}, + {0x0ed4, 0x26}, {0x18fc, 0x2a}, + {0x1914, 0x28}, {0x1a30, 0x03}, + {0x1e38, 0x03}, {0x1ecc, 0x27}, + {0x1ed0, 0x22}, {0x1ed4, 0x26}, + {0x0048, 0x0f}, {0x0060, 0x3c}, + {0x0064, 0xf7}, {0x006c, 0x20}, + {0x0070, 0x7d}, {0x0074, 0x68}, + {0x0af4, 0x1a}, {0x1af4, 0x1a}, + {0x0440, 0x3f}, {0x10d4, 0x08}, + {0x20d4, 0x08}, {0x00d4, 0x30}, + {0x0024, 0x6e}, +}; + +static inline int rk_udphy_grfreg_write(struct regmap *base, + const struct rk_udphy_grf_reg *reg, bool en) +{ + return regmap_write(base, reg->offset, en ? reg->enable : reg->disable); +} + +static int rk_udphy_clk_init(struct rk_udphy *udphy, struct device *dev) +{ + int i; + + udphy->num_clks =3D devm_clk_bulk_get_all(dev, &udphy->clks); + if (udphy->num_clks < 1) + return -ENODEV; + + /* used for configure phy reference clock frequency */ + for (i =3D 0; i < udphy->num_clks; i++) { + if (!strncmp(udphy->clks[i].id, "refclk", 6)) { + udphy->refclk =3D udphy->clks[i].clk; + break; + } + } + + if (!udphy->refclk) + return dev_err_probe(udphy->dev, -EINVAL, "no refclk found\n"); + + return 0; +} + +static int rk_udphy_reset_assert_all(struct rk_udphy *udphy) +{ + return reset_control_bulk_assert(udphy->num_rsts, udphy->rsts); +} + +static int rk_udphy_reset_deassert_all(struct rk_udphy *udphy) +{ + return reset_control_bulk_deassert(udphy->num_rsts, udphy->rsts); +} + +static int rk_udphy_reset_deassert(struct rk_udphy *udphy, char *name) +{ + struct reset_control_bulk_data *list =3D udphy->rsts; + int idx; + + for (idx =3D 0; idx < udphy->num_rsts; idx++) { + if (!strcmp(list[idx].id, name)) + return reset_control_deassert(list[idx].rstc); + } + + return -EINVAL; +} + +static int rk_udphy_reset_init(struct rk_udphy *udphy, struct device *dev) +{ + const struct rk_udphy_cfg *cfg =3D udphy->cfgs; + int idx; + + udphy->num_rsts =3D cfg->num_rsts; + udphy->rsts =3D devm_kcalloc(dev, udphy->num_rsts, + sizeof(*udphy->rsts), GFP_KERNEL); + if (!udphy->rsts) + return -ENOMEM; + + for (idx =3D 0; idx < cfg->num_rsts; idx++) + udphy->rsts[idx].id =3D cfg->rst_list[idx]; + + return devm_reset_control_bulk_get_exclusive(dev, cfg->num_rsts, + udphy->rsts); +} + +static void rk_udphy_u3_port_disable(struct rk_udphy *udphy, u8 disable) +{ + const struct rk_udphy_cfg *cfg =3D udphy->cfgs; + const struct rk_udphy_grf_reg *preg; + + preg =3D udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cf= g; + rk_udphy_grfreg_write(udphy->usbgrf, preg, disable); +} + +static void rk_udphy_usb_bvalid_enable(struct rk_udphy *udphy, u8 enable) +{ + const struct rk_udphy_cfg *cfg =3D udphy->cfgs; + + rk_udphy_grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enabl= e); + rk_udphy_grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enabl= e); +} + +/* + * In usb/dp combo phy driver, here are 2 ways to mapping lanes. + * + * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping) + * -----------------------------------------------------------------------= ---- + * Type-C Pin B11-B10 A2-A3 A11-A10 B2-B3 + * PHY Pad ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) + * C/E(Normal) dpln3 dpln2 dpln0 dpln1 + * C/E(Flip ) dpln0 dpln1 dpln3 dpln2 + * D/F(Normal) usbrx usbtx dpln0 dpln1 + * D/F(Flip ) dpln0 dpln1 usbrx usbtx + * A(Normal ) dpln3 dpln1 dpln2 dpln0 + * A(Flip ) dpln2 dpln0 dpln3 dpln1 + * B(Normal ) usbrx usbtx dpln1 dpln0 + * B(Flip ) dpln1 dpln0 usbrx usbtx + * -----------------------------------------------------------------------= ---- + * + * 2 Mapping the lanes in dtsi + * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = =3D ; + * sample as follow: + * -----------------------------------------------------------------------= ---- + * B11-B10 A2-A3 A11-A10 B2-B3 + * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) + * <0 1 2 3> dpln0 dpln1 dpln2 dpln3 + * <2 3 0 1> dpln2 dpln3 dpln0 dpln1 + * -----------------------------------------------------------------------= ---- + * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-= lane-mux =3D ; + * sample as follow: + * -----------------------------------------------------------------------= ---- + * B11-B10 A2-A3 A11-A10 B2-B3 + * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) + * <0 1> dpln0 dpln1 usbrx usbtx + * <2 3> usbrx usbtx dpln0 dpln1 + * -----------------------------------------------------------------------= ---- + */ + +static void rk_udphy_dplane_select(struct rk_udphy *udphy) +{ + const struct rk_udphy_cfg *cfg =3D udphy->cfgs; + u32 value =3D 0; + + switch (udphy->mode) { + case UDPHY_MODE_DP: + value |=3D 2 << udphy->dp_lane_sel[2] * 2; + value |=3D 3 << udphy->dp_lane_sel[3] * 2; + fallthrough; + + case UDPHY_MODE_DP_USB: + value |=3D 0 << udphy->dp_lane_sel[0] * 2; + value |=3D 1 << udphy->dp_lane_sel[1] * 2; + break; + + case UDPHY_MODE_USB: + break; + + default: + break; + } + + regmap_write(udphy->vogrf, cfg->vogrfcfg[udphy->id].dp_lane_reg, + ((DP_AUX_DIN_SEL | DP_AUX_DOUT_SEL | DP_LANE_SEL_ALL) << 16) | + FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) | + FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value); +} + +static int rk_udphy_dplane_get(struct rk_udphy *udphy) +{ + int dp_lanes; + + switch (udphy->mode) { + case UDPHY_MODE_DP: + dp_lanes =3D 4; + break; + + case UDPHY_MODE_DP_USB: + dp_lanes =3D 2; + break; + + case UDPHY_MODE_USB: + default: + dp_lanes =3D 0; + break; + } + + return dp_lanes; +} + +static void rk_udphy_dplane_enable(struct rk_udphy *udphy, int dp_lanes) +{ + u32 val =3D 0; + int i; + + for (i =3D 0; i < dp_lanes; i++) + val |=3D BIT(udphy->dp_lane_sel[i]); + + regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, CMN_DP_= LANE_EN_ALL, + FIELD_PREP(CMN_DP_LANE_EN_ALL, val)); + + if (!dp_lanes) + regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, + CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); +} + +static void rk_udphy_dp_hpd_event_trigger(struct rk_udphy *udphy, bool hpd) +{ + const struct rk_udphy_cfg *cfg =3D udphy->cfgs; + + udphy->dp_sink_hpd_sel =3D true; + udphy->dp_sink_hpd_cfg =3D hpd; + + if (!udphy->dp_in_use) + return; + + rk_udphy_grfreg_write(udphy->vogrf, &cfg->vogrfcfg[udphy->id].hpd_trigger= , hpd); +} + +static void rk_udphy_set_typec_default_mapping(struct rk_udphy *udphy) +{ + if (udphy->flip) { + udphy->dp_lane_sel[0] =3D 0; + udphy->dp_lane_sel[1] =3D 1; + udphy->dp_lane_sel[2] =3D 3; + udphy->dp_lane_sel[3] =3D 2; + udphy->lane_mux_sel[0] =3D PHY_LANE_MUX_DP; + udphy->lane_mux_sel[1] =3D PHY_LANE_MUX_DP; + udphy->lane_mux_sel[2] =3D PHY_LANE_MUX_USB; + udphy->lane_mux_sel[3] =3D PHY_LANE_MUX_USB; + udphy->dp_aux_dout_sel =3D PHY_AUX_DP_DATA_POL_INVERT; + udphy->dp_aux_din_sel =3D PHY_AUX_DP_DATA_POL_INVERT; + gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 1); + gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0); + } else { + udphy->dp_lane_sel[0] =3D 2; + udphy->dp_lane_sel[1] =3D 3; + udphy->dp_lane_sel[2] =3D 1; + udphy->dp_lane_sel[3] =3D 0; + udphy->lane_mux_sel[0] =3D PHY_LANE_MUX_USB; + udphy->lane_mux_sel[1] =3D PHY_LANE_MUX_USB; + udphy->lane_mux_sel[2] =3D PHY_LANE_MUX_DP; + udphy->lane_mux_sel[3] =3D PHY_LANE_MUX_DP; + udphy->dp_aux_dout_sel =3D PHY_AUX_DP_DATA_POL_NORMAL; + udphy->dp_aux_din_sel =3D PHY_AUX_DP_DATA_POL_NORMAL; + gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0); + gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 1); + } + + udphy->mode =3D UDPHY_MODE_DP_USB; +} + +static int rk_udphy_orien_sw_set(struct typec_switch_dev *sw, + enum typec_orientation orien) +{ + struct rk_udphy *udphy =3D typec_switch_get_drvdata(sw); + + mutex_lock(&udphy->mutex); + + if (orien =3D=3D TYPEC_ORIENTATION_NONE) { + gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0); + gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0); + /* unattached */ + rk_udphy_usb_bvalid_enable(udphy, false); + goto unlock_ret; + } + + udphy->flip =3D (orien =3D=3D TYPEC_ORIENTATION_REVERSE) ? true : false; + rk_udphy_set_typec_default_mapping(udphy); + rk_udphy_usb_bvalid_enable(udphy, true); + +unlock_ret: + mutex_unlock(&udphy->mutex); + return 0; +} + +static void rk_udphy_orien_switch_unregister(void *data) +{ + struct rk_udphy *udphy =3D data; + + typec_switch_unregister(udphy->sw); +} + +static int rk_udphy_setup_orien_switch(struct rk_udphy *udphy) +{ + struct typec_switch_desc sw_desc =3D { }; + + sw_desc.drvdata =3D udphy; + sw_desc.fwnode =3D dev_fwnode(udphy->dev); + sw_desc.set =3D rk_udphy_orien_sw_set; + + udphy->sw =3D typec_switch_register(udphy->dev, &sw_desc); + if (IS_ERR(udphy->sw)) { + dev_err(udphy->dev, "Error register typec orientation switch: %ld\n", + PTR_ERR(udphy->sw)); + return PTR_ERR(udphy->sw); + } + + return devm_add_action_or_reset(udphy->dev, + rk_udphy_orien_switch_unregister, udphy); +} + +static int rk_udphy_refclk_set(struct rk_udphy *udphy) +{ + unsigned long rate; + int ret; + + /* configure phy reference clock */ + rate =3D clk_get_rate(udphy->refclk); + dev_dbg(udphy->dev, "refclk freq %ld\n", rate); + + switch (rate) { + case 24000000: + ret =3D regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_24m_refclk_cf= g, + ARRAY_SIZE(rk_udphy_24m_refclk_cfg)); + if (ret) + return ret; + break; + + case 26000000: + /* register default is 26MHz */ + ret =3D regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_26m_refclk_cf= g, + ARRAY_SIZE(rk_udphy_26m_refclk_cfg)); + if (ret) + return ret; + break; + + default: + dev_err(udphy->dev, "unsupported refclk freq %ld\n", rate); + return -EINVAL; + } + + return 0; +} + +static int rk_udphy_status_check(struct rk_udphy *udphy) +{ + unsigned int val; + int ret; + + /* LCPLL check */ + if (udphy->mode & UDPHY_MODE_USB) { + ret =3D regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_LCPLL_DONE_O= FFSET, + val, (val & CMN_ANA_LCPLL_AFC_DONE) && + (val & CMN_ANA_LCPLL_LOCK_DONE), 200, 100000); + if (ret) { + dev_err(udphy->dev, "cmn ana lcpll lock timeout\n"); + /* + * If earlier software (U-Boot) enabled USB once already + * the PLL may have problems locking on the first try. + * It will be successful on the second try, so for the + * time being a -EPROBE_DEFER will solve the issue. + * + * This requires further investigation to understand the + * root cause, especially considering that the driver is + * asserting all reset lines at probe time. + */ + return -EPROBE_DEFER; + } + + if (!udphy->flip) { + ret =3D regmap_read_poll_timeout(udphy->pma_regmap, + TRSV_LN0_MON_RX_CDR_DONE_OFFSET, val, + val & TRSV_LN0_MON_RX_CDR_LOCK_DONE, + 200, 100000); + if (ret) + dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n"); + } else { + ret =3D regmap_read_poll_timeout(udphy->pma_regmap, + TRSV_LN2_MON_RX_CDR_DONE_OFFSET, val, + val & TRSV_LN2_MON_RX_CDR_LOCK_DONE, + 200, 100000); + if (ret) + dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n"); + } + } + + return 0; +} + +static int rk_udphy_init(struct rk_udphy *udphy) +{ + const struct rk_udphy_cfg *cfg =3D udphy->cfgs; + int ret; + + rk_udphy_reset_assert_all(udphy); + usleep_range(10000, 11000); + + /* enable rx lfps for usb */ + if (udphy->mode & UDPHY_MODE_USB) + rk_udphy_grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true); + + /* Step 1: power on pma and deassert apb rstn */ + rk_udphy_grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true); + + rk_udphy_reset_deassert(udphy, "pma_apb"); + rk_udphy_reset_deassert(udphy, "pcs_apb"); + + /* Step 2: set init sequence and phy refclk */ + ret =3D regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_init_sequence, + ARRAY_SIZE(rk_udphy_init_sequence)); + if (ret) { + dev_err(udphy->dev, "init sequence set error %d\n", ret); + goto assert_resets; + } + + ret =3D rk_udphy_refclk_set(udphy); + if (ret) { + dev_err(udphy->dev, "refclk set error %d\n", ret); + goto assert_resets; + } + + /* Step 3: configure lane mux */ + regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, + CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL, + FIELD_PREP(CMN_DP_LANE_MUX_N(3), udphy->lane_mux_sel[3]) | + FIELD_PREP(CMN_DP_LANE_MUX_N(2), udphy->lane_mux_sel[2]) | + FIELD_PREP(CMN_DP_LANE_MUX_N(1), udphy->lane_mux_sel[1]) | + FIELD_PREP(CMN_DP_LANE_MUX_N(0), udphy->lane_mux_sel[0]) | + FIELD_PREP(CMN_DP_LANE_EN_ALL, 0)); + + /* Step 4: deassert init rstn and wait for 200ns from datasheet */ + if (udphy->mode & UDPHY_MODE_USB) + rk_udphy_reset_deassert(udphy, "init"); + + if (udphy->mode & UDPHY_MODE_DP) { + regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, + CMN_DP_INIT_RSTN, + FIELD_PREP(CMN_DP_INIT_RSTN, 0x1)); + } + + udelay(1); + + /* Step 5: deassert cmn/lane rstn */ + if (udphy->mode & UDPHY_MODE_USB) { + rk_udphy_reset_deassert(udphy, "cmn"); + rk_udphy_reset_deassert(udphy, "lane"); + } + + /* Step 6: wait for lock done of pll */ + ret =3D rk_udphy_status_check(udphy); + if (ret) + goto assert_resets; + + return 0; + +assert_resets: + rk_udphy_reset_assert_all(udphy); + return ret; +} + +static int rk_udphy_setup(struct rk_udphy *udphy) +{ + int ret; + + ret =3D clk_bulk_prepare_enable(udphy->num_clks, udphy->clks); + if (ret) { + dev_err(udphy->dev, "failed to enable clk\n"); + return ret; + } + + ret =3D rk_udphy_init(udphy); + if (ret) { + dev_err(udphy->dev, "failed to init combophy\n"); + clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks); + return ret; + } + + return 0; +} + +static void rk_udphy_disable(struct rk_udphy *udphy) +{ + clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks); + rk_udphy_reset_assert_all(udphy); +} + +static int rk_udphy_parse_lane_mux_data(struct rk_udphy *udphy) +{ + int ret, i, num_lanes; + + num_lanes =3D device_property_count_u32(udphy->dev, "rockchip,dp-lane-mux= "); + if (num_lanes < 0) { + dev_dbg(udphy->dev, "no dp-lane-mux, following dp alt mode\n"); + udphy->mode =3D UDPHY_MODE_USB; + return 0; + } + + if (num_lanes !=3D 2 && num_lanes !=3D 4) + return dev_err_probe(udphy->dev, -EINVAL, + "invalid number of lane mux\n"); + + ret =3D device_property_read_u32_array(udphy->dev, "rockchip,dp-lane-mux", + udphy->dp_lane_sel, num_lanes); + if (ret) + return dev_err_probe(udphy->dev, ret, "get dp lane mux failed\n"); + + for (i =3D 0; i < num_lanes; i++) { + int j; + + if (udphy->dp_lane_sel[i] > 3) + return dev_err_probe(udphy->dev, -EINVAL, + "lane mux between 0 and 3, exceeding the range\n"); + + udphy->lane_mux_sel[udphy->dp_lane_sel[i]] =3D PHY_LANE_MUX_DP; + + for (j =3D i + 1; j < num_lanes; j++) { + if (udphy->dp_lane_sel[i] =3D=3D udphy->dp_lane_sel[j]) + return dev_err_probe(udphy->dev, -EINVAL, + "set repeat lane mux value\n"); + } + } + + udphy->mode =3D UDPHY_MODE_DP; + if (num_lanes =3D=3D 2) { + udphy->mode |=3D UDPHY_MODE_USB; + udphy->flip =3D (udphy->lane_mux_sel[0] =3D=3D PHY_LANE_MUX_DP); + } + + return 0; +} + +static int rk_udphy_get_initial_status(struct rk_udphy *udphy) +{ + int ret; + u32 value; + + ret =3D clk_bulk_prepare_enable(udphy->num_clks, udphy->clks); + if (ret) { + dev_err(udphy->dev, "failed to enable clk\n"); + return ret; + } + + rk_udphy_reset_deassert_all(udphy); + + regmap_read(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, &value); + if (FIELD_GET(CMN_DP_LANE_MUX_ALL, value) && FIELD_GET(CMN_DP_LANE_EN_ALL= , value)) + udphy->status =3D UDPHY_MODE_DP; + else + rk_udphy_disable(udphy); + + return 0; +} + +static int rk_udphy_parse_dt(struct rk_udphy *udphy) +{ + struct device *dev =3D udphy->dev; + struct device_node *np =3D dev_of_node(dev); + enum usb_device_speed maximum_speed; + int ret; + + udphy->u2phygrf =3D syscon_regmap_lookup_by_phandle(np, "rockchip,u2phy-g= rf"); + if (IS_ERR(udphy->u2phygrf)) + return dev_err_probe(dev, PTR_ERR(udphy->u2phygrf), "failed to get u2phy= -grf\n"); + + udphy->udphygrf =3D syscon_regmap_lookup_by_phandle(np, "rockchip,usbdpph= y-grf"); + if (IS_ERR(udphy->udphygrf)) + return dev_err_probe(dev, PTR_ERR(udphy->udphygrf), "failed to get usbdp= phy-grf\n"); + + udphy->usbgrf =3D syscon_regmap_lookup_by_phandle(np, "rockchip,usb-grf"); + if (IS_ERR(udphy->usbgrf)) + return dev_err_probe(dev, PTR_ERR(udphy->usbgrf), "failed to get usb-grf= \n"); + + udphy->vogrf =3D syscon_regmap_lookup_by_phandle(np, "rockchip,vo-grf"); + if (IS_ERR(udphy->vogrf)) + return dev_err_probe(dev, PTR_ERR(udphy->vogrf), "failed to get vo-grf\n= "); + + ret =3D rk_udphy_parse_lane_mux_data(udphy); + if (ret) + return ret; + + udphy->sbu1_dc_gpio =3D devm_gpiod_get_optional(dev, "sbu1-dc", GPIOD_OUT= _LOW); + if (IS_ERR(udphy->sbu1_dc_gpio)) + return PTR_ERR(udphy->sbu1_dc_gpio); + + udphy->sbu2_dc_gpio =3D devm_gpiod_get_optional(dev, "sbu2-dc", GPIOD_OUT= _LOW); + if (IS_ERR(udphy->sbu2_dc_gpio)) + return PTR_ERR(udphy->sbu2_dc_gpio); + + if (device_property_present(dev, "maximum-speed")) { + maximum_speed =3D usb_get_maximum_speed(dev); + udphy->hs =3D maximum_speed <=3D USB_SPEED_HIGH ? true : false; + } + + ret =3D rk_udphy_clk_init(udphy, dev); + if (ret) + return ret; + + return rk_udphy_reset_init(udphy, dev); +} + +static int rk_udphy_power_on(struct rk_udphy *udphy, u8 mode) +{ + int ret; + + if (!(udphy->mode & mode)) { + dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); + return 0; + } + + if (udphy->status =3D=3D UDPHY_MODE_NONE) { + udphy->mode_change =3D false; + ret =3D rk_udphy_setup(udphy); + if (ret) + return ret; + + if (udphy->mode & UDPHY_MODE_USB) + rk_udphy_u3_port_disable(udphy, false); + } else if (udphy->mode_change) { + udphy->mode_change =3D false; + udphy->status =3D UDPHY_MODE_NONE; + if (udphy->mode =3D=3D UDPHY_MODE_DP) + rk_udphy_u3_port_disable(udphy, true); + + rk_udphy_disable(udphy); + ret =3D rk_udphy_setup(udphy); + if (ret) + return ret; + } + + udphy->status |=3D mode; + + return 0; +} + +static void rk_udphy_power_off(struct rk_udphy *udphy, u8 mode) +{ + if (!(udphy->mode & mode)) { + dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); + return; + } + + if (!udphy->status) + return; + + udphy->status &=3D ~mode; + + if (udphy->status =3D=3D UDPHY_MODE_NONE) + rk_udphy_disable(udphy); +} + +static int rk_udphy_dp_phy_init(struct phy *phy) +{ + struct rk_udphy *udphy =3D phy_get_drvdata(phy); + + mutex_lock(&udphy->mutex); + + udphy->dp_in_use =3D true; + rk_udphy_dp_hpd_event_trigger(udphy, udphy->dp_sink_hpd_cfg); + + mutex_unlock(&udphy->mutex); + + return 0; +} + +static int rk_udphy_dp_phy_exit(struct phy *phy) +{ + struct rk_udphy *udphy =3D phy_get_drvdata(phy); + + mutex_lock(&udphy->mutex); + udphy->dp_in_use =3D false; + mutex_unlock(&udphy->mutex); + return 0; +} + +static int rk_udphy_dp_phy_power_on(struct phy *phy) +{ + struct rk_udphy *udphy =3D phy_get_drvdata(phy); + int ret, dp_lanes; + + mutex_lock(&udphy->mutex); + + dp_lanes =3D rk_udphy_dplane_get(udphy); + phy_set_bus_width(phy, dp_lanes); + + ret =3D rk_udphy_power_on(udphy, UDPHY_MODE_DP); + if (ret) + goto unlock; + + rk_udphy_dplane_enable(udphy, dp_lanes); + + rk_udphy_dplane_select(udphy); + +unlock: + mutex_unlock(&udphy->mutex); + /* + * If data send by aux channel too fast after phy power on, + * the aux may be not ready which will cause aux error. Adding + * delay to avoid this issue. + */ + usleep_range(10000, 11000); + return ret; +} + +static int rk_udphy_dp_phy_power_off(struct phy *phy) +{ + struct rk_udphy *udphy =3D phy_get_drvdata(phy); + + mutex_lock(&udphy->mutex); + rk_udphy_dplane_enable(udphy, 0); + rk_udphy_power_off(udphy, UDPHY_MODE_DP); + mutex_unlock(&udphy->mutex); + + return 0; +} + +static int rk_udphy_dp_phy_verify_link_rate(unsigned int link_rate) +{ + switch (link_rate) { + case 1620: + case 2700: + case 5400: + case 8100: + break; + + default: + return -EINVAL; + } + + return 0; +} + +static int rk_udphy_dp_phy_verify_config(struct rk_udphy *udphy, + struct phy_configure_opts_dp *dp) +{ + int i, ret; + + /* If changing link rate was required, verify it's supported. */ + ret =3D rk_udphy_dp_phy_verify_link_rate(dp->link_rate); + if (ret) + return ret; + + /* Verify lane count. */ + switch (dp->lanes) { + case 1: + case 2: + case 4: + /* valid lane count. */ + break; + + default: + return -EINVAL; + } + + /* + * If changing voltages is required, check swing and pre-emphasis + * levels, per-lane. + */ + if (dp->set_voltages) { + /* Lane count verified previously. */ + for (i =3D 0; i < dp->lanes; i++) { + if (dp->voltage[i] > 3 || dp->pre[i] > 3) + return -EINVAL; + + /* + * Sum of voltage swing and pre-emphasis levels cannot + * exceed 3. + */ + if (dp->voltage[i] + dp->pre[i] > 3) + return -EINVAL; + } + } + + return 0; +} + +static void rk_udphy_dp_set_voltage(struct rk_udphy *udphy, u8 bw, + u32 voltage, u32 pre, u32 lane) +{ + const struct rk_udphy_cfg *cfg =3D udphy->cfgs; + const struct rk_udphy_dp_tx_drv_ctrl (*dp_ctrl)[4]; + u32 offset =3D 0x800 * lane; + u32 val; + + if (udphy->mux) + dp_ctrl =3D cfg->dp_tx_ctrl_cfg_typec[bw]; + else + dp_ctrl =3D cfg->dp_tx_ctrl_cfg[bw]; + + val =3D dp_ctrl[voltage][pre].trsv_reg0204; + regmap_write(udphy->pma_regmap, 0x0810 + offset, val); + + val =3D dp_ctrl[voltage][pre].trsv_reg0205; + regmap_write(udphy->pma_regmap, 0x0814 + offset, val); + + val =3D dp_ctrl[voltage][pre].trsv_reg0206; + regmap_write(udphy->pma_regmap, 0x0818 + offset, val); + + val =3D dp_ctrl[voltage][pre].trsv_reg0207; + regmap_write(udphy->pma_regmap, 0x081c + offset, val); +} + +static int rk_udphy_dp_phy_configure(struct phy *phy, + union phy_configure_opts *opts) +{ + struct rk_udphy *udphy =3D phy_get_drvdata(phy); + struct phy_configure_opts_dp *dp =3D &opts->dp; + u32 i, val, lane; + int ret; + + ret =3D rk_udphy_dp_phy_verify_config(udphy, dp); + if (ret) + return ret; + + if (dp->set_rate) { + regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, + CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); + + switch (dp->link_rate) { + case 1620: + udphy->bw =3D DP_BW_RBR; + break; + + case 2700: + udphy->bw =3D DP_BW_HBR; + break; + + case 5400: + udphy->bw =3D DP_BW_HBR2; + break; + + case 8100: + udphy->bw =3D DP_BW_HBR3; + break; + + default: + return -EINVAL; + } + + regmap_update_bits(udphy->pma_regmap, CMN_DP_LINK_OFFSET, CMN_DP_TX_LINK= _BW, + FIELD_PREP(CMN_DP_TX_LINK_BW, udphy->bw)); + regmap_update_bits(udphy->pma_regmap, CMN_SSC_EN_OFFSET, CMN_ROPLL_SSC_E= N, + FIELD_PREP(CMN_ROPLL_SSC_EN, dp->ssc)); + regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, CMN_DP_CMN_RST= N, + FIELD_PREP(CMN_DP_CMN_RSTN, 0x1)); + + ret =3D regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_ROPLL_DONE_O= FFSET, val, + FIELD_GET(CMN_ANA_ROPLL_LOCK_DONE, val) && + FIELD_GET(CMN_ANA_ROPLL_AFC_DONE, val), + 0, 1000); + if (ret) { + dev_err(udphy->dev, "ROPLL is not lock, set_rate failed\n"); + return ret; + } + } + + if (dp->set_voltages) { + for (i =3D 0; i < dp->lanes; i++) { + lane =3D udphy->dp_lane_sel[i]; + switch (dp->link_rate) { + case 1620: + case 2700: + regmap_update_bits(udphy->pma_regmap, + TRSV_ANA_TX_CLK_OFFSET_N(lane), + LN_ANA_TX_SER_TXCLK_INV, + FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, + udphy->lane_mux_sel[lane])); + break; + + case 5400: + case 8100: + regmap_update_bits(udphy->pma_regmap, + TRSV_ANA_TX_CLK_OFFSET_N(lane), + LN_ANA_TX_SER_TXCLK_INV, + FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, 0x0)); + break; + } + + rk_udphy_dp_set_voltage(udphy, udphy->bw, dp->voltage[i], + dp->pre[i], lane); + } + } + + return 0; +} + +static const struct phy_ops rk_udphy_dp_phy_ops =3D { + .init =3D rk_udphy_dp_phy_init, + .exit =3D rk_udphy_dp_phy_exit, + .power_on =3D rk_udphy_dp_phy_power_on, + .power_off =3D rk_udphy_dp_phy_power_off, + .configure =3D rk_udphy_dp_phy_configure, + .owner =3D THIS_MODULE, +}; + +static int rk_udphy_usb3_phy_init(struct phy *phy) +{ + struct rk_udphy *udphy =3D phy_get_drvdata(phy); + int ret; + + mutex_lock(&udphy->mutex); + /* DP only or high-speed, disable U3 port */ + if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { + rk_udphy_u3_port_disable(udphy, true); + goto unlock; + } + + ret =3D rk_udphy_power_on(udphy, UDPHY_MODE_USB); + +unlock: + mutex_unlock(&udphy->mutex); + return ret; +} + +static int rk_udphy_usb3_phy_exit(struct phy *phy) +{ + struct rk_udphy *udphy =3D phy_get_drvdata(phy); + + mutex_lock(&udphy->mutex); + /* DP only or high-speed */ + if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) + goto unlock; + + rk_udphy_power_off(udphy, UDPHY_MODE_USB); + +unlock: + mutex_unlock(&udphy->mutex); + return 0; +} + +static const struct phy_ops rk_udphy_usb3_phy_ops =3D { + .init =3D rk_udphy_usb3_phy_init, + .exit =3D rk_udphy_usb3_phy_exit, + .owner =3D THIS_MODULE, +}; + +static int rk_udphy_typec_mux_set(struct typec_mux_dev *mux, + struct typec_mux_state *state) +{ + struct rk_udphy *udphy =3D typec_mux_get_drvdata(mux); + u8 mode; + + mutex_lock(&udphy->mutex); + + switch (state->mode) { + case TYPEC_DP_STATE_C: + case TYPEC_DP_STATE_E: + udphy->lane_mux_sel[0] =3D PHY_LANE_MUX_DP; + udphy->lane_mux_sel[1] =3D PHY_LANE_MUX_DP; + udphy->lane_mux_sel[2] =3D PHY_LANE_MUX_DP; + udphy->lane_mux_sel[3] =3D PHY_LANE_MUX_DP; + mode =3D UDPHY_MODE_DP; + break; + + case TYPEC_DP_STATE_D: + default: + if (udphy->flip) { + udphy->lane_mux_sel[0] =3D PHY_LANE_MUX_DP; + udphy->lane_mux_sel[1] =3D PHY_LANE_MUX_DP; + udphy->lane_mux_sel[2] =3D PHY_LANE_MUX_USB; + udphy->lane_mux_sel[3] =3D PHY_LANE_MUX_USB; + } else { + udphy->lane_mux_sel[0] =3D PHY_LANE_MUX_USB; + udphy->lane_mux_sel[1] =3D PHY_LANE_MUX_USB; + udphy->lane_mux_sel[2] =3D PHY_LANE_MUX_DP; + udphy->lane_mux_sel[3] =3D PHY_LANE_MUX_DP; + } + mode =3D UDPHY_MODE_DP_USB; + break; + } + + if (state->alt && state->alt->svid =3D=3D USB_TYPEC_DP_SID) { + struct typec_displayport_data *data =3D state->data; + + if (!data) { + rk_udphy_dp_hpd_event_trigger(udphy, false); + } else if (data->status & DP_STATUS_IRQ_HPD) { + rk_udphy_dp_hpd_event_trigger(udphy, false); + usleep_range(750, 800); + rk_udphy_dp_hpd_event_trigger(udphy, true); + } else if (data->status & DP_STATUS_HPD_STATE) { + if (udphy->mode !=3D mode) { + udphy->mode =3D mode; + udphy->mode_change =3D true; + } + rk_udphy_dp_hpd_event_trigger(udphy, true); + } else { + rk_udphy_dp_hpd_event_trigger(udphy, false); + } + } + + mutex_unlock(&udphy->mutex); + return 0; +} + +static void rk_udphy_typec_mux_unregister(void *data) +{ + struct rk_udphy *udphy =3D data; + + typec_mux_unregister(udphy->mux); +} + +static int rk_udphy_setup_typec_mux(struct rk_udphy *udphy) +{ + struct typec_mux_desc mux_desc =3D {}; + + mux_desc.drvdata =3D udphy; + mux_desc.fwnode =3D dev_fwnode(udphy->dev); + mux_desc.set =3D rk_udphy_typec_mux_set; + + udphy->mux =3D typec_mux_register(udphy->dev, &mux_desc); + if (IS_ERR(udphy->mux)) { + dev_err(udphy->dev, "Error register typec mux: %ld\n", + PTR_ERR(udphy->mux)); + return PTR_ERR(udphy->mux); + } + + return devm_add_action_or_reset(udphy->dev, rk_udphy_typec_mux_unregister, + udphy); +} + +static const struct regmap_config rk_udphy_pma_regmap_cfg =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .fast_io =3D true, + .max_register =3D 0x20dc, +}; + +static struct phy *rk_udphy_phy_xlate(struct device *dev, const struct of_= phandle_args *args) +{ + struct rk_udphy *udphy =3D dev_get_drvdata(dev); + + if (args->args_count =3D=3D 0) + return ERR_PTR(-EINVAL); + + switch (args->args[0]) { + case PHY_TYPE_USB3: + return udphy->phy_u3; + case PHY_TYPE_DP: + return udphy->phy_dp; + } + + return ERR_PTR(-EINVAL); +} + +static int rk_udphy_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct phy_provider *phy_provider; + struct resource *res; + struct rk_udphy *udphy; + void __iomem *base; + int id, ret; + + udphy =3D devm_kzalloc(dev, sizeof(*udphy), GFP_KERNEL); + if (!udphy) + return -ENOMEM; + + udphy->cfgs =3D device_get_match_data(dev); + if (!udphy->cfgs) + return dev_err_probe(dev, -EINVAL, "missing match data\n"); + + base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(base)) + return PTR_ERR(base); + + /* find the phy-id from the io address */ + udphy->id =3D -ENODEV; + for (id =3D 0; id < udphy->cfgs->num_phys; id++) { + if (res->start =3D=3D udphy->cfgs->phy_ids[id]) { + udphy->id =3D id; + break; + } + } + + if (udphy->id < 0) + return dev_err_probe(dev, -ENODEV, "no matching device found\n"); + + udphy->pma_regmap =3D devm_regmap_init_mmio(dev, base + UDPHY_PMA, + &rk_udphy_pma_regmap_cfg); + if (IS_ERR(udphy->pma_regmap)) + return PTR_ERR(udphy->pma_regmap); + + udphy->dev =3D dev; + ret =3D rk_udphy_parse_dt(udphy); + if (ret) + return ret; + + ret =3D rk_udphy_get_initial_status(udphy); + if (ret) + return ret; + + mutex_init(&udphy->mutex); + platform_set_drvdata(pdev, udphy); + + if (device_property_present(dev, "orientation-switch")) { + ret =3D rk_udphy_setup_orien_switch(udphy); + if (ret) + return ret; + } + + if (device_property_present(dev, "mode-switch")) { + ret =3D rk_udphy_setup_typec_mux(udphy); + if (ret) + return ret; + } + + udphy->phy_u3 =3D devm_phy_create(dev, dev->of_node, &rk_udphy_usb3_phy_o= ps); + if (IS_ERR(udphy->phy_u3)) { + ret =3D PTR_ERR(udphy->phy_u3); + return dev_err_probe(dev, ret, "failed to create USB3 phy\n"); + } + phy_set_drvdata(udphy->phy_u3, udphy); + + udphy->phy_dp =3D devm_phy_create(dev, dev->of_node, &rk_udphy_dp_phy_ops= ); + if (IS_ERR(udphy->phy_dp)) { + ret =3D PTR_ERR(udphy->phy_dp); + return dev_err_probe(dev, ret, "failed to create DP phy\n"); + } + phy_set_bus_width(udphy->phy_dp, rk_udphy_dplane_get(udphy)); + udphy->phy_dp->attrs.max_link_rate =3D 8100; + phy_set_drvdata(udphy->phy_dp, udphy); + + phy_provider =3D devm_of_phy_provider_register(dev, rk_udphy_phy_xlate); + if (IS_ERR(phy_provider)) { + ret =3D PTR_ERR(phy_provider); + return dev_err_probe(dev, ret, "failed to register phy provider\n"); + } + + return 0; +} + +static int __maybe_unused rk_udphy_resume(struct device *dev) +{ + struct rk_udphy *udphy =3D dev_get_drvdata(dev); + + if (udphy->dp_sink_hpd_sel) + rk_udphy_dp_hpd_event_trigger(udphy, udphy->dp_sink_hpd_cfg); + + return 0; +} + +static const struct dev_pm_ops rk_udphy_pm_ops =3D { + SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, rk_udphy_resume) +}; + +static const char * const rk_udphy_rst_list[] =3D { + "init", "cmn", "lane", "pcs_apb", "pma_apb" +}; + +static const struct rk_udphy_cfg rk3588_udphy_cfgs =3D { + .num_phys =3D 2, + .phy_ids =3D { + 0xfed80000, + 0xfed90000, + }, + .num_rsts =3D ARRAY_SIZE(rk_udphy_rst_list), + .rst_list =3D rk_udphy_rst_list, + .grfcfg =3D { + /* u2phy-grf */ + .bvalid_phy_con =3D RK_UDPHY_GEN_GRF_REG(0x0008, 1, 0, 0x2, 0x3), + .bvalid_grf_con =3D RK_UDPHY_GEN_GRF_REG(0x0010, 3, 2, 0x2, 0x3), + + /* usb-grf */ + .usb3otg0_cfg =3D RK_UDPHY_GEN_GRF_REG(0x001c, 15, 0, 0x1100, 0x0188), + .usb3otg1_cfg =3D RK_UDPHY_GEN_GRF_REG(0x0034, 15, 0, 0x1100, 0x0188), + + /* usbdpphy-grf */ + .low_pwrn =3D RK_UDPHY_GEN_GRF_REG(0x0004, 13, 13, 0, 1), + .rx_lfps =3D RK_UDPHY_GEN_GRF_REG(0x0004, 14, 14, 0, 1), + }, + .vogrfcfg =3D { + { + .hpd_trigger =3D RK_UDPHY_GEN_GRF_REG(0x0000, 11, 10, 1, 3), + .dp_lane_reg =3D 0x0000, + }, + { + .hpd_trigger =3D RK_UDPHY_GEN_GRF_REG(0x0008, 11, 10, 1, 3), + .dp_lane_reg =3D 0x0008, + }, + }, + .dp_tx_ctrl_cfg =3D { + rk3588_dp_tx_drv_ctrl_rbr_hbr, + rk3588_dp_tx_drv_ctrl_rbr_hbr, + rk3588_dp_tx_drv_ctrl_hbr2, + rk3588_dp_tx_drv_ctrl_hbr3, + }, + .dp_tx_ctrl_cfg_typec =3D { + rk3588_dp_tx_drv_ctrl_rbr_hbr_typec, + rk3588_dp_tx_drv_ctrl_rbr_hbr_typec, + rk3588_dp_tx_drv_ctrl_hbr2, + rk3588_dp_tx_drv_ctrl_hbr3, + }, +}; + +static const struct of_device_id rk_udphy_dt_match[] =3D { + { + .compatible =3D "rockchip,rk3588-usbdp-phy", + .data =3D &rk3588_udphy_cfgs + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rk_udphy_dt_match); + +static struct platform_driver rk_udphy_driver =3D { + .probe =3D rk_udphy_probe, + .driver =3D { + .name =3D "rockchip-usbdp-phy", + .of_match_table =3D rk_udphy_dt_match, + .pm =3D &rk_udphy_pm_ops, + }, +}; +module_platform_driver(rk_udphy_driver); + +MODULE_AUTHOR("Frank Wang "); +MODULE_AUTHOR("Zhang Yubing "); +MODULE_DESCRIPTION("Rockchip USBDP Combo PHY driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Mon Feb 9 02:10:03 2026 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2CB91D558; Mon, 8 Apr 2024 22:51:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 8 Apr 2024 22:51:10 +0000 (UTC) Received: by jupiter.universe (Postfix, from userid 1000) id 3FAC14800D0; Tue, 9 Apr 2024 00:51:10 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , linux-rockchip@lists.infradead.org, linux-phy@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Wang , Kever Yang , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v5 03/10] arm64: defconfig: enable Rockchip Samsung USBDP PHY Date: Tue, 9 Apr 2024 00:50:30 +0200 Message-ID: <20240408225109.128953-4-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240408225109.128953-1-sebastian.reichel@collabora.com> References: <20240408225109.128953-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The USBDP Phy is used by RK3588 to handle the Dual-Role USB3 controllers. The Phy also supports Displayport Alt-Mode, but the necessary DRM driver has not yet been merged. Signed-off-by: Sebastian Reichel --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 2c30d617e180..364795edb94b 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1517,6 +1517,7 @@ CONFIG_PHY_ROCKCHIP_PCIE=3Dm CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=3Dm CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=3Dy CONFIG_PHY_ROCKCHIP_TYPEC=3Dy +CONFIG_PHY_ROCKCHIP_USBDP=3Dm CONFIG_PHY_SAMSUNG_UFS=3Dy CONFIG_PHY_UNIPHIER_USB2=3Dy CONFIG_PHY_UNIPHIER_USB3=3Dy --=20 2.43.0 From nobody Mon Feb 9 02:10:03 2026 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E517E26ACE; Mon, 8 Apr 2024 22:51:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712616674; cv=none; b=U0FXxBgaI1IniWybwKSJpeIKJgoZPV4aOikSAmdu77bkoKmiTU6WwMZK8nnbelWUh6UCwuJNQhGr0aBafQw1fvmrbGGd7dk0OdvvYdFoQXAg0tn/qupBPLSc6Va721FLTV6fJiQeIfFjyKt/KrUYvJ0YoXPTS8vRR//b0fmdz5Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712616674; c=relaxed/simple; bh=T9MvklJg6UVFRQrF868mATr8p8Rs4R1YsfG32amYaZw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=vDk+lgyRfGXfKLUgRQ0ynIjO+jwT8u48qhA9SNC+1AhsPfDhdBwbk+GB+RSdnznndvEJO+QPI1xLTfHdbLg9yMMA4HDcE2LuGFMhiSYSv+uou9S/F7u0Ug/JbWE4FsJNo+Ts+oIFgV7FHvCP0x87MQb19nm6Dx8X9ndWWqXYQj8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=I2ejRLU1; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="I2ejRLU1" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1712616671; bh=T9MvklJg6UVFRQrF868mATr8p8Rs4R1YsfG32amYaZw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I2ejRLU13wcmnddPrg5UBm+VBx9/zQOCXH4x1NIlyiNcYvdYPpizilQvr4ETSqs4j 3Zh13fJk84Kgms4ZDi4pJPWfrftmYJzp4Us04EVD6oF3nQ+98eP7/0IBRzjtZTBZXb PEmjWYTcVLfE8SMYod7VZeHbFkMc7efou2L/lg+Vkx7dKlcheGzAIshICUk4FECK/Y QgyyqMKPJ0WweIK6l/Z/+erE/nzdryscesam+s2h17Z+IdItAinFKQiOt3RzpNbf2L 8v5B040uj+0ni1cihUidQaWEp11NjL392mMKOHVqy3VIlLyIV+mp44Q9tvFzEUzHzV 6wu8PSEkxGzSQ== Received: from jupiter.universe (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by madrid.collaboradmins.com (Postfix) with ESMTPSA id C03F137820CD; Mon, 8 Apr 2024 22:51:10 +0000 (UTC) Received: by jupiter.universe (Postfix, from userid 1000) id 41AC84800D1; Tue, 9 Apr 2024 00:51:10 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , linux-rockchip@lists.infradead.org, linux-phy@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Wang , Kever Yang , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v5 04/10] arm64: dts: rockchip: fix usb2phy nodename for rk3588 Date: Tue, 9 Apr 2024 00:50:31 +0200 Message-ID: <20240408225109.128953-5-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240408225109.128953-1-sebastian.reichel@collabora.com> References: <20240408225109.128953-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" usb2-phy should be named usb2phy according to the DT binding, so let's fix it up accordingly. Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi index 87b83c87bd55..5ed0d8c95427 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -543,7 +543,7 @@ usb2phy2_grf: syscon@fd5d8000 { #address-cells =3D <1>; #size-cells =3D <1>; =20 - u2phy2: usb2-phy@8000 { + u2phy2: usb2phy@8000 { compatible =3D "rockchip,rk3588-usb2phy"; reg =3D <0x8000 0x10>; interrupts =3D ; @@ -568,7 +568,7 @@ usb2phy3_grf: syscon@fd5dc000 { #address-cells =3D <1>; #size-cells =3D <1>; =20 - u2phy3: usb2-phy@c000 { + u2phy3: usb2phy@c000 { compatible =3D "rockchip,rk3588-usb2phy"; reg =3D <0xc000 0x10>; interrupts =3D ; --=20 2.43.0 From nobody Mon Feb 9 02:10:03 2026 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02461149DF1; Mon, 8 Apr 2024 22:51:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712616677; cv=none; b=BpX7VrulMGBaXHTYE96spwul6IdKecfoCX1XEahmM8jQPgz1trDmE6RMR2zZ5DP2H+3aIiehxdKOChNtOSZIWdT1bveBDWbydVcVespGNU2P884zcgaGtnDL76oSHgGqZ/rNdFOIiIC/Uk7mfKQgyerdDHHJQCTN75YAX1QJotw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712616677; c=relaxed/simple; bh=t+Zps2/0vSceUv6LE6EZiuGiX/pPNy+d+dQxryQePbw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FI605ArLXbRkQU+eJb9XRZKcs5cW71pwMYndOsmia4jNjsF3Qrq0Ey1N9AOkRAGc4zJegox1654XAcFPb3rDeXO0aW+HMOMnsa8uj42cqaga+NmchHM5SdW4G5gLlLzqEVHhCRmUUzi+mEc+H4NE3QdDE4hbBKaRfLCbIEGTGYM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=AdnYUIiI; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="AdnYUIiI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1712616671; bh=t+Zps2/0vSceUv6LE6EZiuGiX/pPNy+d+dQxryQePbw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AdnYUIiIwrFjQk/eDnCGN2QxRXAWvmB3n1Fy4JwLAQnR5RrIOLYtF8YdTmFHm7jot Q2SDAYtIqpr/otygM3lr+1iF28lYHeVKkOMc+rzrYV+wtoLtOhVBdaVpeGofCoMRMV Szt/aeWY0IpbnivCyh/VKrWu0LJGWMhIePOryQKfFZjkG3VlIEYW1zSy7ieIovOFXf e1HwYeQi4dRZm7gbCU/OzLF1bxvOT9DVc//X/QlFAuiNctXevlUo/M4pCqkgCoqH+o oVUakNn6lNxPGeUidStr4fQEmDPXoNfTLutSBtM/CWq9cijGUhGUbPZI1jizcS9dtX UM0QXFq9qU5Ug== Received: from jupiter.universe (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 2348A37820E2; Mon, 8 Apr 2024 22:51:11 +0000 (UTC) Received: by jupiter.universe (Postfix, from userid 1000) id 436164800D2; Tue, 9 Apr 2024 00:51:10 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , linux-rockchip@lists.infradead.org, linux-phy@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Wang , Kever Yang , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v5 05/10] arm64: dts: rockchip: reorder usb2phy properties for rk3588 Date: Tue, 9 Apr 2024 00:50:32 +0200 Message-ID: <20240408225109.128953-6-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240408225109.128953-1-sebastian.reichel@collabora.com> References: <20240408225109.128953-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Reorder common DT properties alphabetically for usb2phy, according to latest DT style rules. Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi index 5ed0d8c95427..36e0f198f6bd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -546,13 +546,13 @@ usb2phy2_grf: syscon@fd5d8000 { u2phy2: usb2phy@8000 { compatible =3D "rockchip,rk3588-usb2phy"; reg =3D <0x8000 0x10>; - interrupts =3D ; - resets =3D <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; - reset-names =3D "phy", "apb"; + #clock-cells =3D <0>; clocks =3D <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; clock-names =3D "phyclk"; clock-output-names =3D "usb480m_phy2"; - #clock-cells =3D <0>; + interrupts =3D ; + resets =3D <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; + reset-names =3D "phy", "apb"; status =3D "disabled"; =20 u2phy2_host: host-port { @@ -571,13 +571,13 @@ usb2phy3_grf: syscon@fd5dc000 { u2phy3: usb2phy@c000 { compatible =3D "rockchip,rk3588-usb2phy"; reg =3D <0xc000 0x10>; - interrupts =3D ; - resets =3D <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; - reset-names =3D "phy", "apb"; + #clock-cells =3D <0>; clocks =3D <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; clock-names =3D "phyclk"; clock-output-names =3D "usb480m_phy3"; - #clock-cells =3D <0>; + interrupts =3D ; + resets =3D <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; + reset-names =3D "phy", "apb"; status =3D "disabled"; =20 u2phy3_host: host-port { --=20 2.43.0 From nobody Mon Feb 9 02:10:03 2026 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5BD2149C70; Mon, 8 Apr 2024 22:51:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712616677; cv=none; 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Mon, 8 Apr 2024 22:51:11 +0000 (UTC) Received: by jupiter.universe (Postfix, from userid 1000) id 452624800D3; Tue, 9 Apr 2024 00:51:10 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , linux-rockchip@lists.infradead.org, linux-phy@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Wang , Kever Yang , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v5 06/10] arm64: dts: rockchip: add USBDP phys on rk3588 Date: Tue, 9 Apr 2024 00:50:33 +0200 Message-ID: <20240408225109.128953-7-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240408225109.128953-1-sebastian.reichel@collabora.com> References: <20240408225109.128953-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add both USB3-DisplayPort PHYs to RK3588 SoC DT. Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 52 +++++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 63 +++++++++++++++++++++++ 2 files changed, 115 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts= /rockchip/rk3588.dtsi index 5519c1430cb7..4fdd047c9eb9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -17,6 +17,36 @@ pipe_phy1_grf: syscon@fd5c0000 { reg =3D <0x0 0xfd5c0000 0x0 0x100>; }; =20 + usbdpphy1_grf: syscon@fd5cc000 { + compatible =3D "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg =3D <0x0 0xfd5cc000 0x0 0x4000>; + }; + + usb2phy1_grf: syscon@fd5d4000 { + compatible =3D "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg =3D <0x0 0xfd5d4000 0x0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + u2phy1: usb2phy@4000 { + compatible =3D "rockchip,rk3588-usb2phy"; + reg =3D <0x4000 0x10>; + #clock-cells =3D <0>; + clocks =3D <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names =3D "phyclk"; + clock-output-names =3D "usb480m_phy1"; + interrupts =3D ; + resets =3D <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; + reset-names =3D "phy", "apb"; + status =3D "disabled"; + + u2phy1_otg: otg-port { + #phy-cells =3D <0>; + status =3D "disabled"; + }; + }; + }; + i2s8_8ch: i2s@fddc8000 { compatible =3D "rockchip,rk3588-i2s-tdm"; reg =3D <0x0 0xfddc8000 0x0 0x1000>; @@ -310,6 +340,28 @@ sata-port@0 { }; }; =20 + usbdp_phy1: phy@fed90000 { + compatible =3D "rockchip,rk3588-usbdp-phy"; + reg =3D <0x0 0xfed90000 0x0 0x10000>; + #phy-cells =3D <1>; + clocks =3D <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY1_IMMORTAL>, + <&cru PCLK_USBDPPHY1>, + <&u2phy1>; + clock-names =3D "refclk", "immortal", "pclk", "utmi"; + resets =3D <&cru SRST_USBDP_COMBO_PHY1_INIT>, + <&cru SRST_USBDP_COMBO_PHY1_CMN>, + <&cru SRST_USBDP_COMBO_PHY1_LANE>, + <&cru SRST_USBDP_COMBO_PHY1_PCS>, + <&cru SRST_P_USBDPPHY1>; + reset-names =3D "init", "cmn", "lane", "pcs_apb", "pma_apb"; + rockchip,u2phy-grf =3D <&usb2phy1_grf>; + rockchip,usb-grf =3D <&usb_grf>; + rockchip,usbdpphy-grf =3D <&usbdpphy1_grf>; + rockchip,vo-grf =3D <&vo0_grf>; + status =3D "disabled"; + }; + combphy1_ps: phy@fee10000 { compatible =3D "rockchip,rk3588-naneng-combphy"; reg =3D <0x0 0xfee10000 0x0 0x100>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi index 36e0f198f6bd..3a4f433cef5c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -516,12 +516,23 @@ vop_grf: syscon@fd5a4000 { reg =3D <0x0 0xfd5a4000 0x0 0x2000>; }; =20 + vo0_grf: syscon@fd5a6000 { + compatible =3D "rockchip,rk3588-vo-grf", "syscon"; + reg =3D <0x0 0xfd5a6000 0x0 0x2000>; + clocks =3D <&cru PCLK_VO0GRF>; + }; + vo1_grf: syscon@fd5a8000 { compatible =3D "rockchip,rk3588-vo-grf", "syscon"; reg =3D <0x0 0xfd5a8000 0x0 0x100>; clocks =3D <&cru PCLK_VO1GRF>; }; =20 + usb_grf: syscon@fd5ac000 { + compatible =3D "rockchip,rk3588-usb-grf", "syscon"; + reg =3D <0x0 0xfd5ac000 0x0 0x4000>; + }; + php_grf: syscon@fd5b0000 { compatible =3D "rockchip,rk3588-php-grf", "syscon"; reg =3D <0x0 0xfd5b0000 0x0 0x1000>; @@ -537,6 +548,36 @@ pipe_phy2_grf: syscon@fd5c4000 { reg =3D <0x0 0xfd5c4000 0x0 0x100>; }; =20 + usbdpphy0_grf: syscon@fd5c8000 { + compatible =3D "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg =3D <0x0 0xfd5c8000 0x0 0x4000>; + }; + + usb2phy0_grf: syscon@fd5d0000 { + compatible =3D "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg =3D <0x0 0xfd5d0000 0x0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + u2phy0: usb2phy@0 { + compatible =3D "rockchip,rk3588-usb2phy"; + reg =3D <0x0 0x10>; + #clock-cells =3D <0>; + clocks =3D <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names =3D "phyclk"; + clock-output-names =3D "usb480m_phy0"; + interrupts =3D ; + resets =3D <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; + reset-names =3D "phy", "apb"; + status =3D "disabled"; + + u2phy0_otg: otg-port { + #phy-cells =3D <0>; + status =3D "disabled"; + }; + }; + }; + usb2phy2_grf: syscon@fd5d8000 { compatible =3D "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; reg =3D <0x0 0xfd5d8000 0x0 0x4000>; @@ -2380,6 +2421,28 @@ hdptxphy_hdmi0: phy@fed60000 { status =3D "disabled"; }; =20 + usbdp_phy0: phy@fed80000 { + compatible =3D "rockchip,rk3588-usbdp-phy"; + reg =3D <0x0 0xfed80000 0x0 0x10000>; + #phy-cells =3D <1>; + clocks =3D <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY0_IMMORTAL>, + <&cru PCLK_USBDPPHY0>, + <&u2phy0>; + clock-names =3D "refclk", "immortal", "pclk", "utmi"; + resets =3D <&cru SRST_USBDP_COMBO_PHY0_INIT>, + <&cru SRST_USBDP_COMBO_PHY0_CMN>, + <&cru SRST_USBDP_COMBO_PHY0_LANE>, + <&cru SRST_USBDP_COMBO_PHY0_PCS>, + <&cru SRST_P_USBDPPHY0>; + reset-names =3D "init", "cmn", "lane", "pcs_apb", "pma_apb"; + rockchip,u2phy-grf =3D <&usb2phy0_grf>; + rockchip,usb-grf =3D <&usb_grf>; + rockchip,usbdpphy-grf =3D <&usbdpphy0_grf>; + rockchip,vo-grf =3D <&vo0_grf>; + status =3D "disabled"; + }; + combphy0_ps: phy@fee00000 { compatible =3D "rockchip,rk3588-naneng-combphy"; reg =3D <0x0 0xfee00000 0x0 0x100>; --=20 2.43.0 From nobody Mon Feb 9 02:10:03 2026 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E46ED149DED; Mon, 8 Apr 2024 22:51:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712616677; cv=none; b=a4ZFQcx4HnWoCAyCdouT69fjMpn0fo6lSrTIWrANO06RJMLXxpT45Wog1fiY2tbOvkVAP5P8QgeztHfNndXtkoWNUiBDi7VznxpjtISd3/jWYwATmKp78i3PwKnDvAQfogogH2AzhCwhfkpHa0N6gYESdjHVzyLLAFTAaaIAPEo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712616677; c=relaxed/simple; bh=wiEnxwe82TmRvgNDZ6E4uS/rMyY8NbaFBv7UCAOXX94=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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charset="utf-8" Add both USB3 dual-role controllers to the RK3588 devicetree. Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 20 ++++++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 22 ++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts= /rockchip/rk3588.dtsi index 4fdd047c9eb9..5984016b5f96 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -7,6 +7,26 @@ #include "rk3588-pinctrl.dtsi" =20 / { + usb_host1_xhci: usb@fc400000 { + compatible =3D "rockchip,rk3588-dwc3", "snps,dwc3"; + reg =3D <0x0 0xfc400000 0x0 0x400000>; + interrupts =3D ; + clocks =3D <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, + <&cru ACLK_USB3OTG1>; + clock-names =3D "ref_clk", "suspend_clk", "bus_clk"; + dr_mode =3D "otg"; + phys =3D <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; + phy-names =3D "usb2-phy", "usb3-phy"; + phy_type =3D "utmi_wide"; + power-domains =3D <&power RK3588_PD_USB>; + resets =3D <&cru SRST_A_USB3OTG1>; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + status =3D "disabled"; + }; + pcie30_phy_grf: syscon@fd5b8000 { compatible =3D "rockchip,rk3588-pcie3-phy-grf", "syscon"; reg =3D <0x0 0xfd5b8000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi index 3a4f433cef5c..a8f14a74d471 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -436,6 +436,28 @@ scmi_shmem: sram@0 { }; }; =20 + usb_host0_xhci: usb@fc000000 { + compatible =3D "rockchip,rk3588-dwc3", "snps,dwc3"; + reg =3D <0x0 0xfc000000 0x0 0x400000>; + interrupts =3D ; + clocks =3D <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, + <&cru ACLK_USB3OTG0>; + clock-names =3D "ref_clk", "suspend_clk", "bus_clk"; + dr_mode =3D "otg"; + phys =3D <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; + phy-names =3D "usb2-phy", "usb3-phy"; + phy_type =3D "utmi_wide"; + power-domains =3D <&power RK3588_PD_USB>; + resets =3D <&cru SRST_A_USB3OTG0>; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + status =3D "disabled"; + }; + usb_host0_ehci: usb@fc800000 { compatible =3D "rockchip,rk3588-ehci", "generic-ehci"; reg =3D <0x0 0xfc800000 0x0 0x40000>; --=20 2.43.0 From nobody Mon Feb 9 02:10:03 2026 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C56D149E1F; Mon, 8 Apr 2024 22:51:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712616678; cv=none; b=MCwzjSR7srHTEZMW/SPS13b/p5aEIGWwskhWzY+z0pUPwAN5IcesgEM7+Cax40WdTswvGwmZRm36OqyhclgPFBTFMnVs2fWFAyPyRLQCdqIalsKTdNNMlkooOTzhz7u4fcf+gx5zEeOKdyntDZ68oTUPrv/Uwr6MsH//zRY3PYI= ARC-Message-Signature: i=1; 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charset="utf-8" Add support for the board's USB3 connectors. It has 1x USB Type-A and 1x USB Type-C. Signed-off-by: Sebastian Reichel --- .../boot/dts/rockchip/rk3588-evb1-v10.dts | 143 ++++++++++++++++++ 1 file changed, 143 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/= boot/dts/rockchip/rk3588-evb1-v10.dts index de30c2632b8e..c3746d3a9b1d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -9,6 +9,7 @@ #include #include #include +#include #include "rk3588.dtsi" =20 / { @@ -224,6 +225,18 @@ vcc5v0_usb: vcc5v0-usb-regulator { regulator-max-microvolt =3D <5000000>; vin-supply =3D <&vcc5v0_usbdcin>; }; + + vbus5v0_typec: vbus5v0-typec { + compatible =3D "regulator-fixed"; + regulator-name =3D "vbus5v0_typec"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&vcc5v0_usb>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&typec5v_pwren>; + }; }; =20 &combphy0_ps { @@ -284,6 +297,56 @@ &gmac0_rgmii_clk &i2c2 { status =3D "okay"; =20 + usbc0: usb-typec@22 { + compatible =3D "fcs,fusb302"; + reg =3D <0x22>; + interrupt-parent =3D <&gpio3>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usbc0_int>; + vbus-supply =3D <&vbus5v0_typec>; + status =3D "okay"; + + usb_con: connector { + compatible =3D "usb-c-connector"; + label =3D "USB-C"; + data-role =3D "dual"; + power-role =3D "dual"; + try-power-role =3D "source"; + op-sink-microwatt =3D <1000000>; + sink-pdos =3D + ; + source-pdos =3D + ; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + usbc0_orien_sw: endpoint { + remote-endpoint =3D <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg =3D <1>; + usbc0_role_sw: endpoint { + remote-endpoint =3D <&dwc3_0_role_switch>; + }; + }; + + port@2 { + reg =3D <2>; + dp_altmode_mux: endpoint { + remote-endpoint =3D <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + hym8563: rtc@51 { compatible =3D "haoyu,hym8563"; reg =3D <0x51>; @@ -410,6 +473,16 @@ vcc5v0_host_en: vcc5v0-host-en { rockchip,pins =3D <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins =3D <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins =3D <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; =20 &pwm2 { @@ -1041,6 +1114,22 @@ &sata0 { status =3D "okay"; }; =20 +&u2phy0 { + status =3D "okay"; +}; + +&u2phy0_otg { + status =3D "okay"; +}; + +&u2phy1 { + status =3D "okay"; +}; + +&u2phy1_otg { + status =3D "okay"; +}; + &u2phy2 { status =3D "okay"; }; @@ -1079,3 +1168,57 @@ &usb_host1_ehci { &usb_host1_ohci { status =3D "okay"; }; + +&usbdp_phy0 { + orientation-switch; + mode-switch; + sbu1-dc-gpios =3D <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios =3D <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + status =3D "okay"; + + port { + #address-cells =3D <1>; + #size-cells =3D <0>; + + usbdp_phy0_orientation_switch: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy1 { + /* + * USBDP PHY1 is wired to a female USB3 Type-A connector. Additionally + * the differential pairs 2+3 and the aux channel are wired to a RTD2166, + * which converts the DP signal into VGA. This is exposed on the + * board via a female VGA connector. + */ + rockchip,dp-lane-mux =3D <2 3>; + status =3D "okay"; +}; + +&usb_host0_xhci { + dr_mode =3D "otg"; + usb-role-switch; + status =3D "okay"; + + port { + #address-cells =3D <1>; + #size-cells =3D <0>; + dwc3_0_role_switch: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&usbc0_role_sw>; + }; + }; +}; + +&usb_host1_xhci { + dr_mode =3D "host"; + status =3D "okay"; +}; --=20 2.43.0 From nobody Mon Feb 9 02:10:03 2026 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02407149DEF; Mon, 8 Apr 2024 22:51:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712616677; cv=none; b=gN0jmV6eQxTLzO/5m8zOv4n6w2Ajd36dhBa0vzCqULBHiMLKXlxobqtcVqQIMUXogh6TmFJ2u9EQ9JGtIo2YrTAaWqwf72Qa6tR8p1hu4LgnJU8nORjDeDLREi1L8qwipGUPJn9Ol+rylLNT5bFxNDyFzZLAyhfM7OhKkpbjTZ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712616677; c=relaxed/simple; bh=czCfbCIPjGP9pvjr6UIUI+9KpI2JwNoa8jr1BZd0FOw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Y05rYwn7ybmsJHHSXWaH4kvcFsf1EvT50gknExYwfWOjekuE7rnMjGb5xCbr5QZkwf3/WXUVx0uw/rJZ0RvL/N/28X2v3iLWgPe7ymF64I6dR4NYDmPKvH25UuCIeXyKYrmSYT/Hnsno4bP6dPNBIuAkgMVD5YAJ2Man7ZJW3MM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=grA6DCAd; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="grA6DCAd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1712616671; bh=czCfbCIPjGP9pvjr6UIUI+9KpI2JwNoa8jr1BZd0FOw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=grA6DCAd81R08RrZfoAPZ2CHrphx0CmPZWcEy7Ax4cpp5yUkc0FxffrJcDFiI1a2O iqotO08/6QM4anRXSvgSZzY/mnUdqzIXtEyR2zYm4Pu55di7p1dk4xQJe48YL1Fpr6 Q0g8pRefm72qUZdzYXmVHxw1LvB9Jh68Fc5ZIVhhEzyJ2xJi1qmvcuTmQpaTqOZH9R hvk+5sJcYryfT79X7eCtCv/50fdukaHmXV+BDb9iqIrYvufATrON6JBFdycB+D+Wa2 zl8iyf9SFhUgDO7bIZQdwA/oRbYNOwXxdYev2NL0Qc4LqxeUL/5Q2oOd7Sp3bBuexO /Ml3XKIX8gm9Q== Received: from jupiter.universe (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 5246A37820F8; Mon, 8 Apr 2024 22:51:11 +0000 (UTC) Received: by jupiter.universe (Postfix, from userid 1000) id 4A71C4800DC; Tue, 9 Apr 2024 00:51:10 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , linux-rockchip@lists.infradead.org, linux-phy@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Wang , Kever Yang , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v5 09/10] arm64: dts: rockchip: add upper USB3 port to rock-5a Date: Tue, 9 Apr 2024 00:50:36 +0200 Message-ID: <20240408225109.128953-10-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240408225109.128953-1-sebastian.reichel@collabora.com> References: <20240408225109.128953-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable full support (XHCI, EHCI, OHCI) for the upper USB3 port from Radxa Rock 5 Model A. The lower one is already supported. Signed-off-by: Sebastian Reichel --- .../boot/dts/rockchip/rk3588s-rock-5a.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/= boot/dts/rockchip/rk3588s-rock-5a.dts index 00afb90d4eb1..b8ca3ee4c89a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts @@ -697,6 +697,14 @@ regulator-state-mem { }; }; =20 +&u2phy0 { + status =3D "okay"; +}; + +&u2phy0_otg { + status =3D "okay"; +}; + &u2phy2 { status =3D "okay"; }; @@ -720,6 +728,11 @@ &uart2 { status =3D "okay"; }; =20 +&usbdp_phy0 { + status =3D "okay"; + rockchip,dp-lane-mux =3D <2 3>; +}; + &usb_host0_ehci { status =3D "okay"; pinctrl-names =3D "default"; @@ -730,6 +743,11 @@ &usb_host0_ohci { status =3D "okay"; }; =20 +&usb_host0_xhci { + dr_mode =3D "host"; + status =3D "okay"; +}; + &usb_host1_ehci { status =3D "okay"; }; --=20 2.43.0 From nobody Mon Feb 9 02:10:03 2026 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2AB49149E1E; Mon, 8 Apr 2024 22:51:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712616678; cv=none; b=pbSiyr3YfhghPpM+4M8bmC4C6e1O30fVW/GZs6j6pyFdvg12GjDQxVsQXSQ5FegfM+tlN+1fF++UStp+YXHks4ykWV2boj5oCH1mqtbsvIYbGINAt6JXA7Ss9reLLAPxb+QrshPcBFbHwuXKW/RjSO66z0BSXipbCxtu+qpkh4A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712616678; c=relaxed/simple; bh=kN13aI2AEdhhdrsFLGGnxSDLilufbiwke7JxdqO0vzw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XTY1StogPRqv16yANqczWJueWVNfhBMUC0gAbtTVNFYey6UrrQ8uXKeypKjk2IM5R7LPszan4nccEWIJN7CxcXmyOVLDnXsrCR9drQmd4GYik5Pgc0Z3gYMtN1FAwDpANeXqbjbdAxfFTcCpKPVOik3TqFOBU6wpDD5nV9GavZA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=ygbU97j6; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="ygbU97j6" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1712616671; bh=kN13aI2AEdhhdrsFLGGnxSDLilufbiwke7JxdqO0vzw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ygbU97j669pbCnniitafPFFYpYhGemIMdl+4eBCRUB8J3nmFJqgQfLVIXCqw7R/Gp W1FrcLikox7jVGCERz5TwBC4hzfdj8wMlapQ6kS1ah0nuRniAJ6Sf1FVBAMW3ec8Ht ttyHHTrxMmhYnDZLT/NmpbgB9xGnb1dArY5oZtPrrFmZhLRW0wAXTgSbnaX0xZ1DhS pOE8aR/XvcT6dX/N183dbDC26jReHDkUr7i69asUn9lb4cp/cKMqMpV32dMfdBXRX/ tXuVjbvlaqGOqf55SZJYZf3X9Z4lmJAcpQ+lVmEay7a99IFC7iSdOvuHP3kiSnE/Td a3MUTrNIQSRNw== Received: from jupiter.universe (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 584B337820FD; Mon, 8 Apr 2024 22:51:11 +0000 (UTC) Received: by jupiter.universe (Postfix, from userid 1000) id 4C2314800DD; Tue, 9 Apr 2024 00:51:10 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , linux-rockchip@lists.infradead.org, linux-phy@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Wang , Kever Yang , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v5 10/10] arm64: dts: rockchip: add lower USB3 port to rock-5b Date: Tue, 9 Apr 2024 00:50:37 +0200 Message-ID: <20240408225109.128953-11-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240408225109.128953-1-sebastian.reichel@collabora.com> References: <20240408225109.128953-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable full support (XHCI, EHCI, OHCI) for the lower USB3 port from Radxa Rock 5 Model B. The upper one is already supported. Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/b= oot/dts/rockchip/rk3588-rock-5b.dts index 1fe8b2a0ed75..bb09d0e1e20c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -742,6 +742,14 @@ &uart2 { status =3D "okay"; }; =20 +&u2phy1 { + status =3D "okay"; +}; + +&u2phy1_otg { + status =3D "okay"; +}; + &u2phy2 { status =3D "okay"; }; @@ -761,6 +769,10 @@ &u2phy3_host { status =3D "okay"; }; =20 +&usbdp_phy1 { + status =3D "okay"; +}; + &usb_host0_ehci { status =3D "okay"; }; @@ -777,6 +789,11 @@ &usb_host1_ohci { status =3D "okay"; }; =20 +&usb_host1_xhci { + dr_mode =3D "host"; + status =3D "okay"; +}; + &usb_host2_xhci { status =3D "okay"; }; --=20 2.43.0