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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240408-dispcc-dp-clocks-v1-1-f9e44902c28d@linaro.org> References: <20240408-dispcc-dp-clocks-v1-0-f9e44902c28d@linaro.org> In-Reply-To: <20240408-dispcc-dp-clocks-v1-0-f9e44902c28d@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Konrad Dybcio , Konrad Dybcio , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3066; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=JEEcZ7GT4m842B7HDSa1gs6t5sncwlWhVy9ppSIiaIw=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmE9k9tcMAUMKUHJNNPHZnqDs/qTZ3VWTBd0n2i fafY7QDhhqJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZhPZPQAKCRCLPIo+Aiko 1XIfB/4kyD9Ash8QTxO2U1slDgEC6Zst91dV2SrsOfjSQfodYgvtIi0DIYikJyMoNSEf2j5pH7z AmsrZuna+oYnHu93FXhbYBeXGE19J5BKrhKgfy2eKUsZo1sA2c15HXrdGOOeIGAi9o/rE26LwWj Ifg9g5154EOEPVsUxx59wgDYCOQ+0+S9PXHGtGoDRq33Da1IHOGfIuSjlu78mnvqDHyldV/xDL6 omC7299WD21kaB5nEQ5x+CDKGs3MoHZ2W+a6JmxPWu4nppLjb+WEjM0yU7sDTbPz0HwGj/yJ0Pq ZdBgwj+64oxGAVrQfKSD6ujPWp4QZNv8K5sP0ieS4/P0vOkL X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A On SM8450 DisplayPort link clocks use frequency tables inherited from the vendor kernel, it is not applicable in the upstream kernel. Drop frequency tables and use clk_byte2_ops for those clocks. Fixes: 16fb89f92ec4 ("clk: qcom: Add support for Display Clock Controller o= n SM8450") Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong --- drivers/clk/qcom/dispcc-sm8450.c | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8= 450.c index 92e9c4e7b13d..49bb4f58c391 100644 --- a/drivers/clk/qcom/dispcc-sm8450.c +++ b/drivers/clk/qcom/dispcc-sm8450.c @@ -309,26 +309,17 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src= =3D { }, }; =20 -static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] =3D { - F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - { } -}; - static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src =3D { .cmd_rcgr =3D 0x819c, .mnd_width =3D 0, .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_3, - .freq_tbl =3D ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init =3D &(struct clk_init_data) { .name =3D "disp_cc_mdss_dptx0_link_clk_src", .parent_data =3D disp_cc_parent_data_3, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_byte2_ops, }, }; =20 @@ -382,13 +373,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_sr= c =3D { .mnd_width =3D 0, .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_3, - .freq_tbl =3D ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init =3D &(struct clk_init_data) { .name =3D "disp_cc_mdss_dptx1_link_clk_src", .parent_data =3D disp_cc_parent_data_3, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_byte2_ops, }, }; =20 @@ -442,13 +432,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_sr= c =3D { .mnd_width =3D 0, .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_3, - .freq_tbl =3D ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init =3D &(struct clk_init_data) { .name =3D "disp_cc_mdss_dptx2_link_clk_src", .parent_data =3D disp_cc_parent_data_3, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_byte2_ops, }, }; =20 @@ -502,13 +491,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_sr= c =3D { .mnd_width =3D 0, .hid_width =3D 5, .parent_map =3D disp_cc_parent_map_3, - .freq_tbl =3D ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init =3D &(struct clk_init_data) { .name =3D "disp_cc_mdss_dptx3_link_clk_src", .parent_data =3D disp_cc_parent_data_3, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_3), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_byte2_ops, }, }; =20 --=20 2.39.2