From nobody Thu Dec 18 08:07:41 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20209374CB for ; Sat, 6 Apr 2024 11:35:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712403327; cv=none; b=iOI1FN4FApQ8H9cJ77kZMS6G9fxwM34bJvREqtpubHJ1qH93UQuBu2xOKyB/gu3lDsGCJjQPi7JpA3kFaiy4YL532Wv9ha16QB0v2FZ1AbQh+Vq4i0K0m4/cvL1OMvynLnVprhRn2/T5aaHulv/3y/36MM2E+yZGoZrfFbik3g4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712403327; c=relaxed/simple; bh=R97Q2QZSx04EEg2PLja5HX11nqpX6+6Z/tNLhIWtFfk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZMmtgzcYrqr9dzT5WLZWIyAT0R/m/Rhl5fxfH3nZZJcE3AK1OQZVn68pEkuzmEsnHnh13RAI58941RayZDzA0V9xsXGVjbR4YpTZlAZYi+yiYJUIRGUaxtH8fme/kytfUAn+qhkLdw1VMrOeKPQyJl8fXvT7o4ptUYJmX3UsAeU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GBDDrChk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GBDDrChk" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0DD54C433C7; Sat, 6 Apr 2024 11:35:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1712403326; bh=R97Q2QZSx04EEg2PLja5HX11nqpX6+6Z/tNLhIWtFfk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GBDDrChk1RUq4DtnWONvFCFXv1lrG6pW0ZHR2l8oUKM0hzrs63WR0FLoz0PP9FwEB fUzdWpR9hmpGQAl/Jc94fGxDJRBr6VNV9g/FVmcXpYcEjVHpXlBOKXGBf2KhgfNbwd 2mGvpKF/07K0hb1i2zLkobtmewHREGYShNg3IfLOUpYI5a0cwPfV0vSBgFg7CO3TLa 5E4HPquhMzxBoAxRlOvzr4A/pHviHN5HPHwaOzxeo1u4ihNyKjf/SNfxHiHEzklIf0 fUlWKp5vYZ9Pbh05QW2A/5xEY1ARe9jicwbtDx43kWjHuNqJnvti9S2skkgT5foVJG +Ip4WtUlN8iZw== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Samuel Holland Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/3] clocksource/drivers/timer-clint: Add T-Head C9xx clint Date: Sat, 6 Apr 2024 19:21:59 +0800 Message-ID: <20240406112159.1634-4-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240406112159.1634-1-jszhang@kernel.org> References: <20240406112159.1634-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The mtimecmp in T-Head C9xx clint only supports 32bit read/write, implement such support. Signed-off-by: Jisheng Zhang --- drivers/clocksource/timer-clint.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-= clint.c index 0d3890e00b75..655ea81071ff 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -39,6 +39,7 @@ static u64 __iomem *clint_timer_cmp; static u64 __iomem *clint_timer_val; static unsigned long clint_timer_freq; static unsigned int clint_timer_irq; +static bool is_c900_clint; =20 #ifdef CONFIG_RISCV_M_MODE u64 __iomem *clint_time_val; @@ -135,6 +136,19 @@ static int clint_clock_shutdown(struct clock_event_dev= ice *evt) return 0; } =20 +static int c900_clint_clock_next_event(unsigned long delta, + struct clock_event_device *ce) +{ + void __iomem *r =3D clint_timer_cmp + + cpuid_to_hartid_map(smp_processor_id()); + u64 val =3D clint_get_cycles64() + delta; + + csr_set(CSR_IE, IE_TIE); + writel_relaxed(val, r); + writel_relaxed(val >> 32, r + 4); + return 0; +} + static DEFINE_PER_CPU(struct clock_event_device, clint_clock_event) =3D { .name =3D "clint_clockevent", .features =3D CLOCK_EVT_FEAT_ONESHOT, @@ -148,6 +162,9 @@ static int clint_timer_starting_cpu(unsigned int cpu) { struct clock_event_device *ce =3D per_cpu_ptr(&clint_clock_event, cpu); =20 + if (is_c900_clint) + ce->set_next_event =3D c900_clint_clock_next_event; + ce->cpumask =3D cpumask_of(cpu); clockevents_config_and_register(ce, clint_timer_freq, 100, ULONG_MAX); =20 @@ -291,5 +308,12 @@ static int __init clint_timer_init_dt(struct device_no= de *np) return rc; } =20 +static int __init c900_clint_timer_init_dt(struct device_node *np) +{ + is_c900_clint =3D true; + return clint_timer_init_dt(np); +} + TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt); TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt); +TIMER_OF_DECLARE(clint_timer2, "thead,c900-clint", c900_clint_timer_init_d= t); --=20 2.43.0