From nobody Sat Feb 7 18:46:43 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A762732C96 for ; Sat, 6 Apr 2024 11:31:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712403082; cv=none; b=DO0BPjcDaMb2oN61tCC5WqJQLDmv7iWnvIz4kLgplMx4W2S+d0SzNVShBasrCfPAIl1urKgc4seRrGotdvcb+pqKX+Pexl45aIiL7/rzpRI4x4T+q4EIaa2JApCApJJlCVSHM30OFUXXikxIIrcLzCadsqHSS/6luHO0Bn5rJNA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712403082; c=relaxed/simple; bh=66gmc8NYeVWAyoDrDcv4Y+x0uF90S93OHXhD2YCJ+6Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RqHtA0BPHFGREYj1LXe1SADsveePxRE8Fd+wSu5FJ8L0nioeyH++kuFQshR3w1CoeXwa80+H1Cp6xh/wXUqpkdtze/Jnf22+6Yq1QoRkw+wro183IzGSIIn4cUzQRR1hliOMEdAn0GsKRJMsNC1crTVx1oF8+zsQaDdDOvBgbaI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ORp0hN7U; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ORp0hN7U" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D956BC43141; Sat, 6 Apr 2024 11:31:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1712403082; bh=66gmc8NYeVWAyoDrDcv4Y+x0uF90S93OHXhD2YCJ+6Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ORp0hN7UO4eAFVjTVf+j76i3KDprQYwqJpkNxvDrt+iPdVVS6f0JuqH2XGji5lexO VMgDm9Bm7R1z1XzoynU/F8vM/ab82da/na0x9fdYRATW5wtdBxEgqs2ueta2Wn1r6Y kenWH0Xtfzq4OppuuLViU5DSllzVe1rMeN332aV+AcqgyZ/tyNr0UyN222Nz8VlgGi xCVAAraEpdqZc/56/nku3IRctwH2c9uid1h4GtwLQ+5tSFSsD0/HrGGssaMTeb6LL4 hCqSEkaNErssRXqLItMqPpvkhkj/w7jRvglqDVMz818h7r4fNWOH4zZ3RZrUQqmjV1 skUKAikVI+gVg== From: Jisheng Zhang To: Daniel Lezcano , Thomas Gleixner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v2 2/3] clocksource/drivers/timer-clint: Add set_state_shutdown Date: Sat, 6 Apr 2024 19:17:56 +0800 Message-ID: <20240406111757.1597-3-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240406111757.1597-1-jszhang@kernel.org> References: <20240406111757.1597-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add clocksource detach/shutdown callback to disable RISC-V timer interrupt = when switching out clockevent from clint timer to another timer. Signed-off-by: Jisheng Zhang --- drivers/clocksource/timer-clint.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-= clint.c index 09fd292eb83d..1c17eff9861e 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -119,11 +119,21 @@ static int clint_clock_next_event(unsigned long delta, return 0; } =20 +static int clint_clock_shutdown(struct clock_event_device *evt) +{ + void __iomem *r =3D clint_timer_cmp + + cpuid_to_hartid_map(smp_processor_id()); + + writeq_relaxed(U64_MAX, r); + return 0; +} + static DEFINE_PER_CPU(struct clock_event_device, clint_clock_event) =3D { - .name =3D "clint_clockevent", - .features =3D CLOCK_EVT_FEAT_ONESHOT, - .rating =3D 100, - .set_next_event =3D clint_clock_next_event, + .name =3D "clint_clockevent", + .features =3D CLOCK_EVT_FEAT_ONESHOT, + .rating =3D 100, + .set_next_event =3D clint_clock_next_event, + .set_state_shutdown =3D clint_clock_shutdown, }; =20 static int clint_timer_starting_cpu(unsigned int cpu) --=20 2.43.0