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charset="utf-8" Add devicetree binding to describe the PWM for Sophgo CV1800 SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jingbao Qiu --- .../bindings/pwm/sophgo,cv1800-pwm.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/sophgo,cv1800-pwm= .yaml diff --git a/Documentation/devicetree/bindings/pwm/sophgo,cv1800-pwm.yaml b= /Documentation/devicetree/bindings/pwm/sophgo,cv1800-pwm.yaml new file mode 100644 index 000000000000..b5b819d780f1 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/sophgo,cv1800-pwm.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/sophgo,cv1800-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo CV1800 PWM controller + +maintainers: + - Jingbao Qiu + +description: + The chip provides a set of four independent PWM channel outputs. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: sophgo,cv1800-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + +unevaluatedProperties: false + +examples: + - | + pwm0: pwm@3060000 { + compatible =3D "sophgo,cv1800-pwm"; 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charset="utf-8" Implement the PWM driver for CV1800. Signed-off-by: Jingbao Qiu --- drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-cv1800.c | 296 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 307 insertions(+) create mode 100644 drivers/pwm/pwm-cv1800.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 1dd7921194f5..3869ca022aeb 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -182,6 +182,16 @@ config PWM_CROS_EC PWM driver for exposing a PWM attached to the ChromeOS Embedded Controller. =20 +config PWM_CV1800 + tristate "Sophgo CV1800 PWM driver" + depends on ARCH_SOPHGO || COMPILE_TEST + help + Generic PWM framework driver for the Sophgo CV1800 series + SoCs. + + To compile this driver as a module, build the dependecies + as modules, this will be called pwm-cv1800. + config PWM_DWC_CORE tristate depends on HAS_IOMEM diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 90913519f11a..6295e2259efc 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_PWM_CLK) +=3D pwm-clk.o obj-$(CONFIG_PWM_CLPS711X) +=3D pwm-clps711x.o obj-$(CONFIG_PWM_CRC) +=3D pwm-crc.o obj-$(CONFIG_PWM_CROS_EC) +=3D pwm-cros-ec.o +obj-$(CONFIG_PWM_CV1800) +=3D pwm-cv1800.o obj-$(CONFIG_PWM_DWC_CORE) +=3D pwm-dwc-core.o obj-$(CONFIG_PWM_DWC) +=3D pwm-dwc.o obj-$(CONFIG_PWM_EP93XX) +=3D pwm-ep93xx.o diff --git a/drivers/pwm/pwm-cv1800.c b/drivers/pwm/pwm-cv1800.c new file mode 100644 index 000000000000..37a6be3f63aa --- /dev/null +++ b/drivers/pwm/pwm-cv1800.c @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Sophgo CV1800 PWM driver + * Author: Jingbao Qiu + * + * Limitations: + * - It output low when PWM channel disabled. + * - This pwm device supports dynamic loading of PWM parameters. When PWMS= TART + * is written from 0 to 1, the register value (HLPERIODn, PERIODn) will = be + * temporarily stored inside the PWM. If you want to dynamically change = the + * waveform during PWM output, after writing the new value to HLPERIODn = and + * PERIODn, write 1 and then 0 to PWMUPDATE[n] to make the new value eff= ective. + * - Supports up to Rate/2 output, and the lowest is about Rate/(2^30-1). + * - By setting HLPERIODn to 0, can produce 100% duty cycle. + * - This hardware could support inverted polarity. By default, the value = of the + * POLARITY register is 0x0. This means that HLPERIOD represents the num= ber + * of low level beats. + * - This hardware supports input mode and output mode, implemented throug= h the + * Output-Enable/OE register. However, this driver has not yet implement= ed + * capture callback. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define PWM_CV1800_HLPERIOD_BASE 0x00 +#define PWM_CV1800_PERIOD_BASE 0x04 +#define PWM_CV1800_POLARITY 0x40 +#define PWM_CV1800_START 0x44 +#define PWM_CV1800_DONE 0x48 +#define PWM_CV1800_UPDATE 0x4c +#define PWM_CV1800_OE 0xd0 + +#define PWM_CV1800_HLPERIOD(n) (PWM_CV1800_HLPERIOD_BASE + ((n)*0x08)) +#define PWM_CV1800_PERIOD(n) (PWM_CV1800_PERIOD_BASE + ((n)*0x08)) + +#define PWM_CV1800_UPDATE_MASK(n) (BIT(0) << (n)) +#define PWM_CV1800_OE_MASK(n) (BIT(0) << (n)) +#define PWM_CV1800_START_MASK(n) (BIT(0) << (n)) +#define PWM_CV1800_POLARITY_MASK(n) (BIT(0) << (n)) + +#define PWM_CV1800_MAXPERIOD 0x3fffffff +#define PWM_CV1800_MINPERIOD 2 +#define PWM_CV1800_CHANNELS 4 +#define PWM_CV1800_PERIOD_RESET BIT(1) +#define PWM_CV1800_HLPERIOD_RESET BIT(0) +#define PWM_CV1800_REG_DISABLE 0x00U +#define PWM_CV1800_REG_ENABLE(n) (BIT(0) << (n)) + +struct cv1800_pwm { + struct regmap *map; + struct clk *clk; + unsigned long clk_rate; +}; + +static inline struct cv1800_pwm *to_cv1800_pwm_dev(struct pwm_chip *chip) +{ + return pwmchip_get_drvdata(chip); +} + +static const struct regmap_config cv1800_pwm_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, +}; + +static int cv1800_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm, + bool enable) +{ + struct cv1800_pwm *priv =3D to_cv1800_pwm_dev(chip); + u32 pwm_enable, state; + + regmap_read(priv->map, PWM_CV1800_START, &pwm_enable); + pwm_enable &=3D PWM_CV1800_START_MASK(pwm->hwpwm); + + /* + * If the parameters are changed during runtime, Register needs + * to be updated to take effect. + */ + if (pwm_enable && enable) { + regmap_update_bits(priv->map, PWM_CV1800_UPDATE, + PWM_CV1800_UPDATE_MASK(pwm->hwpwm), + PWM_CV1800_REG_ENABLE(pwm->hwpwm)); + regmap_update_bits(priv->map, PWM_CV1800_UPDATE, + PWM_CV1800_UPDATE_MASK(pwm->hwpwm), + PWM_CV1800_REG_DISABLE); + } else if (!pwm_enable && enable) { + regmap_update_bits(priv->map, PWM_CV1800_START, + PWM_CV1800_START_MASK(pwm->hwpwm), + PWM_CV1800_REG_ENABLE(pwm->hwpwm)); + } else if (pwm_enable && !enable) { + regmap_update_bits(priv->map, PWM_CV1800_START, + PWM_CV1800_START_MASK(pwm->hwpwm), + PWM_CV1800_REG_DISABLE); + } + + /* check and set OE/Output-Enable mode */ + regmap_read(priv->map, PWM_CV1800_OE, &state); + state &=3D PWM_CV1800_OE_MASK(pwm->hwpwm); + + if (state =3D=3D PWM_CV1800_REG_DISABLE && enable) + regmap_update_bits(priv->map, PWM_CV1800_OE, + PWM_CV1800_OE_MASK(pwm->hwpwm), + PWM_CV1800_REG_ENABLE(pwm->hwpwm)); + + return 0; +} + +static void cv1800_pwm_set_polarity(struct pwm_chip *chip, + struct pwm_device *pwm, + enum pwm_polarity polarity) +{ + struct cv1800_pwm *priv =3D to_cv1800_pwm_dev(chip); + u32 config_polarity =3D 0; + + if (pwm->state.enabled) + cv1800_pwm_enable(chip, pwm, !pwm->state.enabled); + + if (polarity =3D=3D PWM_POLARITY_NORMAL) + config_polarity =3D PWM_CV1800_POLARITY_MASK(pwm->hwpwm); + + regmap_update_bits(priv->map, PWM_CV1800_POLARITY, + PWM_CV1800_POLARITY_MASK(pwm->hwpwm), + config_polarity); +} + +static int cv1800_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct cv1800_pwm *priv =3D to_cv1800_pwm_dev(chip); + u32 period_val, hlperiod_val; + u64 ticks; + u32 state; + + if (state->polarity !=3D pwm->state.polarity) + cv1800_pwm_set_polarity(chip, pwm, state->polarity); + + /* + * This hardware use PERIOD and HLPERIOD registers to represent PWM waves. + * + * The meaning of PERIOD is how many clock cycles (from the clock source) + * are used to represent PWM waves. + * PERIOD =3D rate(MHz) / target(MHz) + * PERIOD =3D period(ns) * rate(Hz) / NSEC_PER_SEC + */ + ticks =3D mul_u64_u64_div_u64(state->period, priv->clk_rate, + NSEC_PER_SEC); + if (ticks < PWM_CV1800_MINPERIOD) + return -EINVAL; + + if (ticks > PWM_CV1800_MAXPERIOD) + ticks =3D PWM_CV1800_MAXPERIOD; + period_val =3D (u32)ticks; + + /* + * After mapping, hlperiod represents the same polarity as duty. + * HLPERIOD =3D rate(MHz) / duty(MHz) + * HLPERIOD =3D duty(ns) * rate(Hz) / NSEC_PER_SEC + */ + ticks =3D mul_u64_u64_div_u64(state->duty_cycle, priv->clk_rate, + NSEC_PER_SEC); + if (ticks > period_val) + ticks =3D period_val; + hlperiod_val =3D (u32)ticks; + + regmap_write(priv->map, PWM_CV1800_PERIOD(pwm->hwpwm), period_val); + regmap_write(priv->map, PWM_CV1800_HLPERIOD(pwm->hwpwm), hlperiod_val); + + cv1800_pwm_enable(chip, pwm, state->enabled); + + return 0; +} + +static int cv1800_pwm_get_state(struct pwm_chip *chip, struct pwm_device *= pwm, + struct pwm_state *state) +{ + struct cv1800_pwm *priv =3D to_cv1800_pwm_dev(chip); + u32 period_val, hlperiod_val; + u64 period_ns =3D 0, duty_ns =3D 0; + u32 enable =3D 0, polarity =3D 0; + + regmap_read(priv->map, PWM_CV1800_PERIOD(pwm->hwpwm), &period_val); + regmap_read(priv->map, PWM_CV1800_HLPERIOD(pwm->hwpwm), &hlperiod_val); + + if (period_val !=3D PWM_CV1800_PERIOD_RESET || + hlperiod_val !=3D PWM_CV1800_HLPERIOD_RESET) { + period_ns =3D DIV_ROUND_UP_ULL(period_val * NSEC_PER_SEC, + priv->clk_rate); + duty_ns =3D DIV_ROUND_UP_ULL(hlperiod_val * NSEC_PER_SEC, + priv->clk_rate); + + regmap_read(priv->map, PWM_CV1800_START, &enable); + enable &=3D PWM_CV1800_START_MASK(pwm->hwpwm); + + regmap_read(priv->map, PWM_CV1800_POLARITY, &polarity); + polarity &=3D PWM_CV1800_POLARITY_MASK(pwm->hwpwm); + } + + state->period =3D period_ns; + state->duty_cycle =3D duty_ns; + state->enabled =3D enable; + + /* + * To ensure that duty and hlperiod represent the same polarity + * the following mapping needs to be completed. + * + * |----------|------------|------------|-----------| + * | Linux | register | duty | register | + * | polarity | polarity | | hlperiod | + * |----------|------------|------------|-----------| + * | 1 | 0 | low level | low level | + * |----------|------------|------------|-----------| + * | 0 | 1 | high level | high level| + * |----------|------------|------------|-----------| + */ + state->polarity =3D polarity ? PWM_POLARITY_NORMAL : + PWM_POLARITY_INVERSED; + + return 0; +} + +static const struct pwm_ops cv1800_pwm_ops =3D { + .apply =3D cv1800_pwm_apply, + .get_state =3D cv1800_pwm_get_state, +}; + +static int cv1800_pwm_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct cv1800_pwm *priv; + struct pwm_chip *chip; + void __iomem *base; + int ret; + + chip =3D devm_pwmchip_alloc(dev, PWM_CV1800_CHANNELS, sizeof(*priv)); + if (!chip) + return PTR_ERR(chip); + priv =3D to_cv1800_pwm_dev(chip); + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + priv->map =3D devm_regmap_init_mmio(&pdev->dev, base, + &cv1800_pwm_regmap_config); + if (IS_ERR(priv->map)) + return PTR_ERR(priv->map); + + priv->clk =3D devm_clk_get_enabled(&pdev->dev, NULL); + if (IS_ERR(priv->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk), + "clk not found\n"); + + ret =3D devm_clk_rate_exclusive_get(dev, priv->clk); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "failed to get exclusive rate\n"); + + priv->clk_rate =3D clk_get_rate(priv->clk); + if (!priv->clk_rate) + return dev_err_probe(&pdev->dev, -EINVAL, + "Invalid clock rate: %lu\n", + priv->clk_rate); + + chip->ops =3D &cv1800_pwm_ops; + + ret =3D devm_pwmchip_add(dev, chip); + if (ret) + return dev_err_probe(dev, ret, "Failed to add PWM chip\n"); + + return 0; +} + +static const struct of_device_id cv1800_pwm_dt_ids[] =3D { + { .compatible =3D "sophgo,cv1800-pwm" }, + {}, +}; +MODULE_DEVICE_TABLE(of, cv1800_pwm_dt_ids); + +static struct platform_driver cv1800_pwm_driver =3D { + .probe =3D cv1800_pwm_probe, + .driver =3D { + .name =3D "cv1800-pwm", + .of_match_table =3D cv1800_pwm_dt_ids, + }, +}; +module_platform_driver(cv1800_pwm_driver); + +MODULE_AUTHOR("Jingbao Qiu"); +MODULE_DESCRIPTION("Sophgo cv1800 PWM Driver"); +MODULE_LICENSE("GPL"); --=20 2.25.1