From nobody Thu Feb 12 14:46:32 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AEBF2143C64 for ; Fri, 5 Apr 2024 08:00:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712304025; cv=none; b=QG0b/IpZlYZK+epesuoYjcuDY6f+sQgoKuAFPnkexq517o12QZ7K2PuqJHLwawax9/xHwFujPED+xmpV/GmzX21vC9r2KRecZdO9hbgHDUVaIp2aEAxPibCSK+O0M3fyfQEhBc6Ix5Pgfg1OblZUXOlWbOPNUYMJdTC4KQM+LDU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712304025; c=relaxed/simple; bh=k9DsP+wTogXiq02Ur9V/CNgu2qs7Sc4qPL+MpAclWYQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=OgiL1iG9bokPdy578LSYwjRGH+fxpaIukWlbjf5W+xNHaKGiKXRUv4e4XY/vEg2PP5Yd0ZyxB8POoP4hjHQ58K1R+68VAwgXCSmOargNd3rSKnl33JzB3A7b5SE6zWETwFuBPgH84XfG6/GX5Z/V8G9VBIxloaEWUe+glURKrp0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B30041007; Fri, 5 Apr 2024 01:00:53 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.41.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EA6C63F64C; Fri, 5 Apr 2024 01:00:18 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Jonathan Corbet , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , Mark Rutland , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [RFC 1/8] arm64/sysreg: Add register fields for MDSELR_EL1 Date: Fri, 5 Apr 2024 13:30:01 +0530 Message-Id: <20240405080008.1225223-2-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240405080008.1225223-1-anshuman.khandual@arm.com> References: <20240405080008.1225223-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for MDSELR_EL1 as per the definitions based on DDI0601 2023-12. Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Reviewed-by: Mark Brown --- arch/arm64/tools/sysreg | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a4c1dd4741a4..4c58fd7a70e6 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -93,6 +93,17 @@ Res0 63:32 Field 31:0 DTRTX EndSysreg =20 +Sysreg MDSELR_EL1 2 0 0 4 2 +Res0 63:6 +Enum 5:4 BANK + 0b00 BANK_0 + 0b01 BANK_1 + 0b10 BANK_2 + 0b11 BANK_3 +EndEnum +Res0 3:0 +EndSysreg + Sysreg OSECCR_EL1 2 0 0 6 2 Res0 63:32 Field 31:0 EDECCR --=20 2.25.1 From nobody Thu Feb 12 14:46:32 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 96420143C49 for ; Fri, 5 Apr 2024 08:00:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712304030; cv=none; b=oUgEV8luPcaK728FIkAwKkKhX229qtX8wPPRIJwgjrWsGzchEewmh/085YiUU8xgzUIHX8qrz0rv3xONjKbf4tYa+yF7AzQtg/j5NFLw3llnpjh4kUKNc4sH2gf5lHBMUYCHlRNXDxwKsoCk9k0FdPES42YqWRlZq9cy9KbMwj0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712304030; c=relaxed/simple; bh=Wb6PwvvB2mHY46JfKwKq+HwPzHPME4H5fqXIPpiBc60=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=rqSBSol7SIl8PptopfCSPCA4G5RUci9zX0CnLj9GzoZtUZAfaRVfUXoMQ1zNxk2FK5fiG668Rqi21JCBniijEmGGH4ywvWTdgp+PL6TwXKZzN04NXJpQwA75Lf45YeWperSK1+QI5tWvlStu9V8w5C1aHAuuBcHWWyfByQpKil0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AAAB5FEC; Fri, 5 Apr 2024 01:00:58 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.41.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BCAEF3F64C; Fri, 5 Apr 2024 01:00:23 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Jonathan Corbet , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , Mark Rutland , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [RFC 2/8] arm64/sysreg: Add register fields for HDFGRTR2_EL2 Date: Fri, 5 Apr 2024 13:30:02 +0530 Message-Id: <20240405080008.1225223-3-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240405080008.1225223-1-anshuman.khandual@arm.com> References: <20240405080008.1225223-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for HDFGRTR2_EL2 as per the definitions based on DDI0601 2023-12. Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Reviewed-by: Mark Brown --- arch/arm64/tools/sysreg | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 4c58fd7a70e6..9bcd8a0d55c4 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2444,6 +2444,34 @@ Field 1 ICIALLU Field 0 ICIALLUIS EndSysreg =20 +Sysreg HDFGRTR2_EL2 3 4 3 1 0 +Res0 63:24 +Field 23 nMDSTEPOP_EL1 +Field 22 nTRBMPAM_EL1 +Res0 21 +Field 20 nTRCITECR_EL1 +Field 19 nPMSDSFR_EL1 +Field 18 nSPMDEVAFF_EL1 +Field 17 nSPMID +Field 16 nSPMSCR_EL1 +Field 15 nSPMACCESSR_EL1 +Field 14 nSPMCR_EL0 +Field 13 nSPMOVS +Field 12 nSPMINTEN +Field 11 nSPMCNTEN +Field 10 nSPMSELR_EL0 +Field 9 nSPMEVTYPERn_EL0 +Field 8 nSPMEVCNTRn_EL0 +Field 7 nPMSSCR_EL1 +Field 6 nPMSSDATA +Field 5 nMDSELR_EL1 +Field 4 nPMUACR_EL1 +Field 3 nPMICFILTR_EL0 +Field 2 nPMICNTR_EL0 +Field 1 nPMIAR_EL1 +Field 0 nPMECR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1 --=20 2.25.1 From nobody Thu Feb 12 14:46:32 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E16A91442FB for ; Fri, 5 Apr 2024 08:00:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712304035; cv=none; b=kpwt7tGzepxtFNm2wdu9mdGVtybA1BGhkdLZz+y15jpsVPJfGFUQ+/TpG4tg9J0KM4SnSLkw1Pj6mCQm4OQ3oy5kTgCt6PqXznu41dEcxiqg0Y/Tu+MPI4ZR6nfXLxdl4JOMYdyA2iuBOitY4P96sdWNXvV6dUZTqEev2/QJVXs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712304035; c=relaxed/simple; bh=ppheZXl6aBi7L/wsNMkQtMkZzKI6NHrhQoAZ3CNxhSY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=KfPbk2s30ZUguqcaVFSlmtx/kROaFcdqSySH9wVSoC89bK3uapHoozOBfAi/oEWX5Bq4uKi7rXARC8r0559OPXDIUf4XPzqPgSy1P+NwT2jI2Z1tP1G/MkgrQ1t+ElOStv/PfV1T+n7CbxE5Cm/AXs7a4iz9kF1juLe2kx4iMQo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E00681007; Fri, 5 Apr 2024 01:01:03 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.41.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C1A103F64C; Fri, 5 Apr 2024 01:00:28 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Jonathan Corbet , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , Mark Rutland , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [RFC 3/8] arm64/sysreg: Add register fields for HDFGWTR2_EL2 Date: Fri, 5 Apr 2024 13:30:03 +0530 Message-Id: <20240405080008.1225223-4-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240405080008.1225223-1-anshuman.khandual@arm.com> References: <20240405080008.1225223-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for HDFGWTR2_EL2 as per the definitions based on DDI0601 2023-12. Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Reviewed-by: Mark Brown --- arch/arm64/tools/sysreg | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 9bcd8a0d55c4..c38414352dd8 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2472,6 +2472,33 @@ Field 1 nPMIAR_EL1 Field 0 nPMECR_EL1 EndSysreg =20 +Sysreg HDFGWTR2_EL2 3 4 3 1 1 +Res0 63:24 +Field 23 nMDSTEPOP_EL1 +Field 22 nTRBMPAM_EL1 +Field 21 nPMZR_EL0 +Field 20 nTRCITECR_EL1 +Field 19 nPMSDSFR_EL1 +Res0 18:17 +Field 16 nSPMSCR_EL1 +Field 15 nSPMACCESSR_EL1 +Field 14 nSPMCR_EL0 +Field 13 nSPMOVS +Field 12 nSPMINTEN +Field 11 nSPMCNTEN +Field 10 nSPMSELR_EL0 +Field 9 nSPMEVTYPERn_EL0 +Field 8 nSPMEVCNTRn_EL0 +Field 7 nPMSSCR_EL1 +Res0 6 +Field 5 nMDSELR_EL1 +Field 4 nPMUACR_EL1 +Field 3 nPMICFILTR_EL0 +Field 2 nPMICNTR_EL0 +Field 1 nPMIAR_EL1 +Field 0 nPMECR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1 --=20 2.25.1 From nobody Thu Feb 12 14:46:32 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B5B241448EE for ; Fri, 5 Apr 2024 08:00:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712304040; cv=none; b=erf233+YhX92ExUzYcmRUYU/ZF4clf2nbQ7NlY6++9RFzPq8AciiD0hGW6G3OEHKM9qkPoxHL3ftJK0o5Q74tj0JlhZttBDvQibHNawCspwTYoB8nhriJE5ai+dSm6Uz8luOhsm/M5hk/jr54kpZx1d4UG74hyd7SFLfxWgoYpM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712304040; c=relaxed/simple; bh=qsNETKTdsDLCMPc+pNNCMKJ9Y+lyO+WUhZx/89aqduc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jR47KU/Lz1fREmS/xKSPGJAd4lwXPpiKbKmIvr08NXiRZcp0ozDZCXzrvhiokZ0Z8Rv9DguStwQEx9PWrLu0/N7R+t/r1u35s6l1DJTAtN5l+1yi9bQW7i1Sarm8djspnhDSeM8aWVP9O31l9wkzEHqMCoO7dJIBg4HZ5rfq3Vg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EB565FEC; Fri, 5 Apr 2024 01:01:08 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.41.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 03C113F64C; Fri, 5 Apr 2024 01:00:33 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Jonathan Corbet , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , Mark Rutland , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [RFC 4/8] arm64/sysreg: Update ID_AA64MMFR0_EL1 register Date: Fri, 5 Apr 2024 13:30:04 +0530 Message-Id: <20240405080008.1225223-5-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240405080008.1225223-1-anshuman.khandual@arm.com> References: <20240405080008.1225223-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This updates ID_AA64MMFR0_EL1.FGT and ID_AA64MMFR0_EL1.PARANGE register fields as per the definitions based on DDI0601 2023-12. Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Reviewed-by: Mark Brown --- arch/arm64/tools/sysreg | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index c38414352dd8..7ba4fa99c160 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1567,6 +1567,7 @@ EndEnum UnsignedEnum 59:56 FGT 0b0000 NI 0b0001 IMP + 0b0010 FGT2 EndEnum Res0 55:48 UnsignedEnum 47:44 EXS @@ -1628,6 +1629,7 @@ Enum 3:0 PARANGE 0b0100 44 0b0101 48 0b0110 52 + 0b0111 56 EndEnum EndSysreg =20 --=20 2.25.1 From nobody Thu Feb 12 14:46:32 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C1F0C144D1A for ; Fri, 5 Apr 2024 08:00:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712304045; cv=none; b=aPpn7wxPbSajcQpPE0ivX9f9DODbzO0grd1TVirHZt4d59iLnb2JTjy1jJZoNRmP9UPi+63q8dVidaTH2A5IwNqC1Iiur483oQO99vSPLIVdIwNomDtg3VpdEobL3yfw/AfdbeJS1c+YP5hWDpPqdWgBSxlz1B4f+rcVT1K9W0k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712304045; c=relaxed/simple; bh=oZuhb1s6XFcdK4qhiPqywi4shXCxzFqbwESan+8EU2U=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Wc4iQla1PQONISg955W3ZRMMQNBWcRm0kfgeZWGFMKlb2+bDIokNJ7Z+hKyw73uVU0kJPBzpMtAtv0AnWTxxK6uS6nxx2wH1almDFP6mVTmgk1FRaq42c1u6q0Szld+phDgywd64i2ic80RSaux8joIG/dDTNZZAOcX8eAKf2uA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E87611007; Fri, 5 Apr 2024 01:01:13 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.41.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 076453F64C; Fri, 5 Apr 2024 01:00:38 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Jonathan Corbet , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , Mark Rutland , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [RFC 5/8] KVM: arm64: Explicitly handle MDSELR_EL1 traps as UNDEFINED Date: Fri, 5 Apr 2024 13:30:05 +0530 Message-Id: <20240405080008.1225223-6-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240405080008.1225223-1-anshuman.khandual@arm.com> References: <20240405080008.1225223-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently read_sanitised_id_aa64dfr0_el1() caps the ID_AA64DFR0.DebugVer to ID_AA64DFR0_DebugVer_V8P8, resulting in FEAT_Debugv8p9 not being exposed to the guest. MDSELR_EL1 register access in the guest, is currently trapped by the existing configuration of the fine-grained traps. As the register is not described in sys_reg_descs[] table emulate_sys_reg() will warn that this is unknown access before injecting an UNDEFINED exception into the guest. Any well-behaved guests shouldn't try to use this register, but any badly-behaved guests could, thus resulting in unnecessary warnings. To avoid such warnings, access to MDSELR_EL1 should be explicitly handled as UNDEFINED via updating sys_reg_desc[] as required. Cc: Marc Zyngier Cc: Oliver Upton Cc: James Morse Cc: Suzuki K Poulose Cc: Catalin Marinas Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Cc: kvmarm@lists.linux.dev Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/kvm/sys_regs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c9f4f387155f..2956bdcd358e 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2203,6 +2203,7 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, DBG_BCR_BVR_WCR_WVR_EL1(2), DBG_BCR_BVR_WCR_WVR_EL1(3), + { SYS_DESC(SYS_MDSELR_EL1), undef_access }, DBG_BCR_BVR_WCR_WVR_EL1(4), DBG_BCR_BVR_WCR_WVR_EL1(5), DBG_BCR_BVR_WCR_WVR_EL1(6), --=20 2.25.1 From nobody Thu Feb 12 14:46:32 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D6A4A144D2F for ; Fri, 5 Apr 2024 08:00:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712304050; cv=none; b=a77KmoSt7rtHaX0h0TEjzAYK1QxZtmq74UqvHgZWAqNy4b0SK3NoVAywa8RQiHYsWzYRIgxrB7aELc/GrGhpvxoYw4LTLcqI0gTGx9qvlCs0Orvon07VQ1AGn08tWWBU6qvUBCrSiosaNeUVEIAe8OsrUgpMx062+9aqDljjehc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712304050; c=relaxed/simple; bh=Y8qR5dnBFBqgYwzYwZTZm2OTo1rtvKaQ03sa0h+y3jg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=dYLRTtCDdVviM5tHOGe0X7scRPuQ9hlMgd13aUzN9wEJIhH0De3XyVp2yOKCpXHPgbcbmIBM+FP5cIzX/UR/V4VCPYwAV894+pKkeHmraXe+IP8JyuODBGBGXSesfFP+3dAAQ319ZQQZ9GENyztW3G862VK1WQBDoLGG9e4NlHQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D3D3FFEC; Fri, 5 Apr 2024 01:01:18 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.41.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0C3C23F64C; Fri, 5 Apr 2024 01:00:43 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Jonathan Corbet , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , Mark Rutland , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [RFC 6/8] arm64/cpufeature: Add field details for ID_AA64DFR1_EL1 register Date: Fri, 5 Apr 2024 13:30:06 +0530 Message-Id: <20240405080008.1225223-7-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240405080008.1225223-1-anshuman.khandual@arm.com> References: <20240405080008.1225223-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds required field details for ID_AA64DFR1_EL1, and also drops dummy ftr_raz[] array which is now redundant. These register fields will be used to enable increased breakpoint and watchpoint registers via FEAT_Debugv8p9 later. Cc: Catalin Marinas Cc: Will Deacon cc: Mark Brown Cc: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/kernel/cpufeature.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 56583677c1f2..128f2836fc1e 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -527,6 +527,21 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = =3D { ARM64_FTR_END, }; =20 +static const struct arm64_ftr_bits ftr_id_aa64dfr1[] =3D { + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_AB= L_CMPs_SHIFT, 8, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_DP= FZS_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_EB= EP_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_IT= E_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_AB= LE_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_PM= ICNTR_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_SP= MU_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_CT= X_CMPs_SHIFT, 8, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_WR= Ps_SHIFT, 8, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_BR= Ps_SHIFT, 8, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_SY= SPMUID_SHIFT, 8, 0), + ARM64_FTR_END, +}; + static const struct arm64_ftr_bits ftr_mvfr0[] =3D { ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_= SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_= SHIFT, 4, 0), @@ -705,10 +720,6 @@ static const struct arm64_ftr_bits ftr_single32[] =3D { ARM64_FTR_END, }; =20 -static const struct arm64_ftr_bits ftr_raz[] =3D { - ARM64_FTR_END, -}; - #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ .sys_id =3D id, \ .reg =3D &(struct arm64_ftr_reg){ \ @@ -781,7 +792,7 @@ static const struct __ftr_reg_entry { =20 /* Op1 =3D 0, CRn =3D 0, CRm =3D 5 */ ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), - ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), + ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_id_aa64dfr1), =20 /* Op1 =3D 0, CRn =3D 0, CRm =3D 6 */ ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), --=20 2.25.1 From nobody Thu Feb 12 14:46:32 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D153E142E81; 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dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E3CFC1007; Fri, 5 Apr 2024 01:01:23 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.41.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EB97B3F64C; Fri, 5 Apr 2024 01:00:48 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Jonathan Corbet , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , Mark Rutland , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Subject: [RFC 7/8] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9 Date: Fri, 5 Apr 2024 13:30:07 +0530 Message-Id: <20240405080008.1225223-8-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240405080008.1225223-1-anshuman.khandual@arm.com> References: <20240405080008.1225223-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Fine grained trap control for MDSELR_EL1 register needs to be configured in HDFGRTR2_EL2, and HDFGWTR2_EL2 registers when kernel enters at EL1, but EL2 is also present. This adds a new helper __init_el2_fgt2() initializing this new FEAT_FGT2 based fine grained registers. MDCR_EL2.EBWE needs to be enabled for additional (beyond 16) breakpoint and watchpoint exceptions when kernel enters at EL1, but EL2 is also present. This updates __init_el2_debug() as required for FEAT_Debugv8p9. While here, also update booting.rst with MDCR_EL3 and SCR_EL3 requirements. Cc: Catalin Marinas Cc: Will Deacon Cc: Jonathan Corbet Cc: Marc Zyngier Cc: Oliver Upton Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: kvmarm@lists.linux.dev Signed-off-by: Anshuman Khandual --- Documentation/arch/arm64/booting.rst | 19 +++++++++++++++++++ arch/arm64/include/asm/el2_setup.h | 27 +++++++++++++++++++++++++++ arch/arm64/include/asm/kvm_arm.h | 1 + 3 files changed, 47 insertions(+) diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm6= 4/booting.rst index b57776a68f15..e69d972018cf 100644 --- a/Documentation/arch/arm64/booting.rst +++ b/Documentation/arch/arm64/booting.rst @@ -285,6 +285,12 @@ Before jumping into the kernel, the following conditio= ns must be met: =20 - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1. =20 + For CPUs with the Fine Grained Traps (FEAT_FGT2) extension present: + + - If EL3 is present and the kernel is entered at EL2: + + - SCR_EL3.FGTEn2 (bit 59) must be initialised to 0b1. + For CPUs with support for HCRX_EL2 (FEAT_HCX) present: =20 - If EL3 is present and the kernel is entered at EL2: @@ -319,6 +325,19 @@ Before jumping into the kernel, the following conditio= ns must be met: - ZCR_EL2.LEN must be initialised to the same value for all CPUs the kernel will execute on. =20 + For CPUs with FEAT_Debugv8p9 extension present: + + - If the kernel is entered at EL1 and EL2 is present: + + - HDFGRTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1 + - HDFGWTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1 + - MDCR_EL2.EBWE (bit 43) must be initialized to 0b1 + + - If EL3 is present: + + - MDCR_EL3.TDA (bit 9) must be initialized to 0b0 + - MDCR_EL3.EBWE (bit 43) must be initialized to 0b1 + For CPUs with the Scalable Matrix Extension (FEAT_SME): =20 - If EL3 is present: diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el= 2_setup.h index b7afaa026842..0425067a93d9 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -96,6 +96,14 @@ // to own it. =20 .Lskip_trace_\@: + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #ID_AA64DFR0_EL1_DebugVer_SHIFT, #4 + cmp x1, #ID_AA64DFR0_EL1_DebugVer_V8P9 + b.lt .Lskip_dbg_v8p9_\@ + + mov x0, #MDCR_EL2_EBWE + orr x2, x2, x0 +.Lskip_dbg_v8p9_\@: msr mdcr_el2, x2 // Configure debug traps .endm =20 @@ -203,6 +211,24 @@ .Lskip_fgt_\@: .endm =20 +.macro __init_el2_fgt2 + mrs x1, id_aa64mmfr0_el1 + ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4 + cmp x1, #ID_AA64MMFR0_EL1_FGT_FGT2 + b.lt .Lskip_fgt2_\@ + + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #ID_AA64DFR0_EL1_DebugVer_SHIFT, #4 + cmp x1, #ID_AA64DFR0_EL1_DebugVer_V8P9 + b.lt .Lskip_dbg_v8p9_\@ + + mov_q x0, HDFGWTR2_EL2_nMDSELR_EL1 + msr_s SYS_HDFGWTR2_EL2, x0 + msr_s SYS_HDFGRTR2_EL2, x0 +.Lskip_dbg_v8p9_\@: +.Lskip_fgt2_\@: +.endm + .macro __init_el2_nvhe_prepare_eret mov x0, #INIT_PSTATE_EL1 msr spsr_el2, x0 @@ -228,6 +254,7 @@ __init_el2_nvhe_idregs __init_el2_cptr __init_el2_fgt + __init_el2_fgt2 .endm =20 #ifndef __KVM_NVHE_HYPERVISOR__ diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_= arm.h index e01bb5ca13b7..9d77dfc43e08 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -306,6 +306,7 @@ BIT(11)) =20 /* Hyp Debug Configuration Register bits */ +#define MDCR_EL2_EBWE (UL(1) << 43) #define MDCR_EL2_E2TB_MASK (UL(0x3)) #define MDCR_EL2_E2TB_SHIFT (UL(24)) #define MDCR_EL2_HPMFZS (UL(1) << 36) --=20 2.25.1 From nobody Thu Feb 12 14:46:32 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 55942143876 for ; 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dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4D6DAFEC; Fri, 5 Apr 2024 01:01:28 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.41.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id F05383F64C; Fri, 5 Apr 2024 01:00:53 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Jonathan Corbet , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , Mark Rutland , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [RFC 8/8] arm64/hw_breakpoint: Enable FEAT_Debugv8p9 Date: Fri, 5 Apr 2024 13:30:08 +0530 Message-Id: <20240405080008.1225223-9-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240405080008.1225223-1-anshuman.khandual@arm.com> References: <20240405080008.1225223-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently there can be maximum 16 breakpoints, and 16 watchpoints available on a given platform - as detected from ID_AA64DFR0_EL1.[BRPs|WRPs] register fields. But these breakpoint, and watchpoints can be extended further up to 64 via a new arch feature FEAT_Debugv8p9. This first enables banked access for the breakpoint and watchpoint register set via MDSELR_EL1, extended exceptions via MDSCR_EL1.EMBWE and determining available breakpoints and watchpoints in the platform from ID_AA64DFR1_EL1, when FEAT_Debugv8p9 is enabled. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/debug-monitors.h | 2 +- arch/arm64/include/asm/hw_breakpoint.h | 46 +++++++++++++++++++------ arch/arm64/kernel/debug-monitors.c | 16 ++++++--- arch/arm64/kernel/hw_breakpoint.c | 33 ++++++++++++++++++ 4 files changed, 82 insertions(+), 15 deletions(-) diff --git a/arch/arm64/include/asm/debug-monitors.h b/arch/arm64/include/a= sm/debug-monitors.h index 13d437bcbf58..75eedba2abbe 100644 --- a/arch/arm64/include/asm/debug-monitors.h +++ b/arch/arm64/include/asm/debug-monitors.h @@ -19,7 +19,7 @@ /* MDSCR_EL1 enabling bits */ #define DBG_MDSCR_KDE (1 << 13) #define DBG_MDSCR_MDE (1 << 15) -#define DBG_MDSCR_MASK ~(DBG_MDSCR_KDE | DBG_MDSCR_MDE) +#define DBG_MDSCR_EMBWE (1UL << 32) =20 #define DBG_ESR_EVT(x) (((x) >> 27) & 0x7) =20 diff --git a/arch/arm64/include/asm/hw_breakpoint.h b/arch/arm64/include/as= m/hw_breakpoint.h index bd81cf17744a..6b9822140f71 100644 --- a/arch/arm64/include/asm/hw_breakpoint.h +++ b/arch/arm64/include/asm/hw_breakpoint.h @@ -79,8 +79,8 @@ static inline void decode_ctrl_reg(u32 reg, * Limits. * Changing these will require modifications to the register accessors. */ -#define ARM_MAX_BRP 16 -#define ARM_MAX_WRP 16 +#define ARM_MAX_BRP 64 +#define ARM_MAX_WRP 64 =20 /* Virtual debug register bases. */ #define AARCH64_DBG_REG_BVR 0 @@ -135,22 +135,48 @@ static inline void ptrace_hw_copy_thread(struct task_= struct *task) } #endif =20 +static inline bool is_debug_v8p9_enabled(void) +{ + u64 dfr0 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); + int dver =3D cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_D= ebugVer_SHIFT); + + return dver =3D=3D ID_AA64DFR0_EL1_DebugVer_V8P9; +} + /* Determine number of BRP registers available. */ static inline int get_num_brps(void) { - u64 dfr0 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); - return 1 + - cpuid_feature_extract_unsigned_field(dfr0, - ID_AA64DFR0_EL1_BRPs_SHIFT); + u64 dfr0, dfr1; + int dver, brps; + + dfr0 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); + dver =3D cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_Debug= Ver_SHIFT); + if (dver =3D=3D ID_AA64DFR0_EL1_DebugVer_V8P9) { + dfr1 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR1_EL1); + brps =3D cpuid_feature_extract_unsigned_field_width(dfr1, + ID_AA64DFR1_EL1_BRPs_SHIFT, 8); + } else { + brps =3D cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_BRPs= _SHIFT); + } + return 1 + brps; } =20 /* Determine number of WRP registers available. */ static inline int get_num_wrps(void) { - u64 dfr0 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); - return 1 + - cpuid_feature_extract_unsigned_field(dfr0, - ID_AA64DFR0_EL1_WRPs_SHIFT); + u64 dfr0, dfr1; + int dver, wrps; + + dfr0 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); + dver =3D cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_Debug= Ver_SHIFT); + if (dver =3D=3D ID_AA64DFR0_EL1_DebugVer_V8P9) { + dfr1 =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR1_EL1); + wrps =3D cpuid_feature_extract_unsigned_field_width(dfr1, + ID_AA64DFR1_EL1_WRPs_SHIFT, 8); + } else { + wrps =3D cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_WRPs= _SHIFT); + } + return 1 + wrps; } =20 #ifdef CONFIG_CPU_PM diff --git a/arch/arm64/kernel/debug-monitors.c b/arch/arm64/kernel/debug-m= onitors.c index 64f2ecbdfe5c..3299d1e8dc61 100644 --- a/arch/arm64/kernel/debug-monitors.c +++ b/arch/arm64/kernel/debug-monitors.c @@ -23,6 +23,7 @@ #include #include #include +#include =20 /* Determine debug architecture. */ u8 debug_monitors_arch(void) @@ -34,7 +35,7 @@ u8 debug_monitors_arch(void) /* * MDSCR access routines. */ -static void mdscr_write(u32 mdscr) +static void mdscr_write(u64 mdscr) { unsigned long flags; flags =3D local_daif_save(); @@ -43,7 +44,7 @@ static void mdscr_write(u32 mdscr) } NOKPROBE_SYMBOL(mdscr_write); =20 -static u32 mdscr_read(void) +static u64 mdscr_read(void) { return read_sysreg(mdscr_el1); } @@ -76,10 +77,11 @@ early_param("nodebugmon", early_debug_disable); */ static DEFINE_PER_CPU(int, mde_ref_count); static DEFINE_PER_CPU(int, kde_ref_count); +static DEFINE_PER_CPU(int, embwe_ref_count); =20 void enable_debug_monitors(enum dbg_active_el el) { - u32 mdscr, enable =3D 0; + u64 mdscr, enable =3D 0; =20 WARN_ON(preemptible()); =20 @@ -90,6 +92,9 @@ void enable_debug_monitors(enum dbg_active_el el) this_cpu_inc_return(kde_ref_count) =3D=3D 1) enable |=3D DBG_MDSCR_KDE; =20 + if (is_debug_v8p9_enabled() && this_cpu_inc_return(embwe_ref_count) =3D= =3D 1) + enable |=3D DBG_MDSCR_EMBWE; + if (enable && debug_enabled) { mdscr =3D mdscr_read(); mdscr |=3D enable; @@ -100,7 +105,7 @@ NOKPROBE_SYMBOL(enable_debug_monitors); =20 void disable_debug_monitors(enum dbg_active_el el) { - u32 mdscr, disable =3D 0; + u64 mdscr, disable =3D 0; =20 WARN_ON(preemptible()); =20 @@ -111,6 +116,9 @@ void disable_debug_monitors(enum dbg_active_el el) this_cpu_dec_return(kde_ref_count) =3D=3D 0) disable &=3D ~DBG_MDSCR_KDE; =20 + if (is_debug_v8p9_enabled() && this_cpu_dec_return(embwe_ref_count) =3D= =3D 0) + disable &=3D ~DBG_MDSCR_EMBWE; + if (disable) { mdscr =3D mdscr_read(); mdscr &=3D disable; diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_break= point.c index 2f5755192c2b..7b9169535b76 100644 --- a/arch/arm64/kernel/hw_breakpoint.c +++ b/arch/arm64/kernel/hw_breakpoint.c @@ -103,10 +103,40 @@ int hw_breakpoint_slots(int type) WRITE_WB_REG_CASE(OFF, 14, REG, VAL); \ WRITE_WB_REG_CASE(OFF, 15, REG, VAL) =20 +static int set_bank_index(int n) +{ + int mdsel_bank; + int bank =3D n / 16, index =3D n % 16; + + switch (bank) { + case 0: + mdsel_bank =3D MDSELR_EL1_BANK_BANK_0; + break; + case 1: + mdsel_bank =3D MDSELR_EL1_BANK_BANK_1; + break; + case 2: + mdsel_bank =3D MDSELR_EL1_BANK_BANK_2; + break; + case 3: + mdsel_bank =3D MDSELR_EL1_BANK_BANK_3; + break; + default: + pr_warn("Unknown register bank %d\n", bank); + return -EINVAL; + } + write_sysreg_s(mdsel_bank << MDSELR_EL1_BANK_SHIFT, SYS_MDSELR_EL1); + isb(); + return index; +} + static u64 read_wb_reg(int reg, int n) { u64 val =3D 0; =20 + if (is_debug_v8p9_enabled()) + n =3D set_bank_index(n); + switch (reg + n) { GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val); GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val); @@ -122,6 +152,9 @@ NOKPROBE_SYMBOL(read_wb_reg); =20 static void write_wb_reg(int reg, int n, u64 val) { + if (is_debug_v8p9_enabled()) + n =3D set_bank_index(n); + switch (reg + n) { GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val= ); GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val= ); --=20 2.25.1