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[87.246.222.101]) by smtp.gmail.com with ESMTPSA id y3-20020a05651c020300b002d429304a20sm116880ljn.8.2024.04.05.01.41.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Apr 2024 01:41:42 -0700 (PDT) From: Konrad Dybcio Date: Fri, 05 Apr 2024 10:41:34 +0200 Subject: [PATCH 6/6] arm64: dts: qcom: sm8550: Wire up GPU speed bin & more OPPs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240405-topic-smem_speedbin-v1-6-ce2b864251b1@linaro.org> References: <20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org> In-Reply-To: <20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org> To: Bjorn Andersson , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.13-dev-0438c Add the speedbin masks to ensure only the desired OPPs are available on chips of a given bin. Using this, add the binned 719 MHz OPP and the non-binned 124.8 MHz. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 5cae8d773cec..2f6842f6a5b7 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2087,48 +2087,67 @@ zap-shader { memory-region =3D <&gpu_micro_code_mem>; }; =20 - /* Speedbin needs more work on A740+, keep only lower freqs */ gpu_opp_table: opp-table { compatible =3D "operating-points-v2"; =20 + opp-719000000 { + opp-hz =3D /bits/ 64 <719000000>; + opp-level =3D ; + opp-supported-hw =3D <0x1>; + }; + opp-680000000 { opp-hz =3D /bits/ 64 <680000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-615000000 { opp-hz =3D /bits/ 64 <615000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-550000000 { opp-hz =3D /bits/ 64 <550000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-475000000 { opp-hz =3D /bits/ 64 <475000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-401000000 { opp-hz =3D /bits/ 64 <401000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-348000000 { opp-hz =3D /bits/ 64 <348000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-295000000 { opp-hz =3D /bits/ 64 <295000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-220000000 { opp-hz =3D /bits/ 64 <220000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; + }; + + opp-124800000 { + opp-hz =3D /bits/ 64 <124800000>; + opp-level =3D ; + opp-supported-hw =3D <0x3>; }; }; }; --=20 2.40.1