From nobody Sun Feb 8 20:29:26 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 550E2126F11 for ; Thu, 4 Apr 2024 14:18:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712240290; cv=none; b=WXjUQ2aRXfhXTToXjAJVeqPrx2N3ZrgcSIp7vmmwQx9+aD3liyEq/xMOE/lQWo9vPgcBw2OMdKrOfDzqvNUx4ygJYM+V7u0lrgDttgNc4zUKLCZ2dBJwnucpzH5FHBff8bK2F4uAP2QU7UjvMS7lIeDxWpSZjTQiAidZc6Uh++I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712240290; c=relaxed/simple; bh=0S+oR25+79lKZWWwbRegFOj5KyLL3zn68gthwqbdnlM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=l/SMlQUzAQ1RGS2XNIy4LBPspjvaWVTdupASe43IjpL18o/oLCXagvWMyUGCbxSfr3SJcjWwQtDNqLIkKchXGiymK7Woq4/tW/duklQNXM1ADcUGTDzGJs9wGucWosTwsky3luOtqfTfh5Q1zPnz2196NrVNu8I1bSyftd6iAc8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=D2OjDFbV; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="D2OjDFbV" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712240290; x=1743776290; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0S+oR25+79lKZWWwbRegFOj5KyLL3zn68gthwqbdnlM=; b=D2OjDFbVJkobgxkKxdS1FvaYn79S8LEWAxqOMkB65K0eyhOO2WIi4gVV ebBCdX2L2iv6H6PZVYYN/EScawKnSigbjoZ1r+pvOVyK9WMMTYAE/VNnS +RsizyuGuJtHnFclTOGWY2xTXVFZ4K/ZRu5z7m0gak+lmb53GB0v68rzv 4Sos4qD/s4xSwCZwoFe/Dvos9neeU/QQEeM+e/CpKimoibt5D5DkLPeTd jB/zKs1/Jcc9bEKyE5wGpk0yMYZyP8c3XdFsoSNz8emxXMGHhW6XAhE41 jQfk4EeGiv4ek/gGC6uCOpVqf96jg3VFDRkmM4HFAx5PqyH8JPT5qBMyd A==; X-CSE-ConnectionGUID: VEk0kaPNTH6V7v5/zmK+Ow== X-CSE-MsgGUID: 29/0a+bdT0OV4wPog0rQMQ== X-IronPort-AV: E=McAfee;i="6600,9927,11034"; a="7632419" X-IronPort-AV: E=Sophos;i="6.07,179,1708416000"; d="scan'208";a="7632419" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Apr 2024 07:18:08 -0700 X-CSE-ConnectionGUID: 4F/1dvAKRgabWLPY9bt5uw== X-CSE-MsgGUID: 6m3By+qiQnelYpdNV9x9DA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,179,1708416000"; d="scan'208";a="23448349" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmviesa004.fm.intel.com with ESMTP; 04 Apr 2024 07:18:07 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org, irogers@google.com, adrian.hunter@intel.com, alexander.shishkin@linux.intel.com, linux-kernel@vger.kernel.org Cc: ak@linux.intel.com, Kan Liang Subject: [PATCH 1/4] perf/x86/intel/uncore: Factor out common MMIO init and ops functions Date: Thu, 4 Apr 2024 07:17:03 -0700 Message-Id: <20240404141706.1235531-2-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20240404141706.1235531-1-kan.liang@linux.intel.com> References: <20240404141706.1235531-1-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kan Liang Some uncore PMON registers are located in the MMIO space. For the client machine, the MMIO space is usually located at D0:F0 but in a different BAR. For example, some uncore PMON registers are located in the SAF BAR, not the MCHBAR in the Lunar Lake. The current __uncore_imc_init_box() hard code the BAR information. Factor out the uncore_get_box_mmio_addr() which uses the BAR information as a parameter. The only change is the error output message. The hardcode name 'MCHBAR' is replaced by the offset of a BAR. Add a new macro, MMIO_UNCORE_COMMON_OPS(), since the MMIO ops functions are usually the same among different generations. Signed-off-by: Kan Liang --- arch/x86/events/intel/uncore_snb.c | 47 +++++++++++++++++++----------- 1 file changed, 30 insertions(+), 17 deletions(-) diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/unc= ore_snb.c index 9462fd9f3b7a..05fe6e90bd8e 100644 --- a/arch/x86/events/intel/uncore_snb.c +++ b/arch/x86/events/intel/uncore_snb.c @@ -1481,33 +1481,35 @@ static struct pci_dev *tgl_uncore_get_mc_dev(void) #define TGL_UNCORE_MMIO_IMC_MEM_OFFSET 0x10000 #define TGL_UNCORE_PCI_IMC_MAP_SIZE 0xe000 =20 -static void __uncore_imc_init_box(struct intel_uncore_box *box, - unsigned int base_offset) +static void +uncore_get_box_mmio_addr(struct intel_uncore_box *box, + unsigned int base_offset, + int bar_offset, int step) { struct pci_dev *pdev =3D tgl_uncore_get_mc_dev(); struct intel_uncore_pmu *pmu =3D box->pmu; struct intel_uncore_type *type =3D pmu->type; resource_size_t addr; - u32 mch_bar; + u32 bar; =20 if (!pdev) { pr_warn("perf uncore: Cannot find matched IMC device.\n"); return; } =20 - pci_read_config_dword(pdev, SNB_UNCORE_PCI_IMC_BAR_OFFSET, &mch_bar); - /* MCHBAR is disabled */ - if (!(mch_bar & BIT(0))) { - pr_warn("perf uncore: MCHBAR is disabled. Failed to map IMC free-running= counters.\n"); + pci_read_config_dword(pdev, bar_offset, &bar); + if (!(bar & BIT(0))) { + pr_warn("perf uncore: BAR 0x%x is disabled. Failed to map %s counters.\n= ", + bar_offset, type->name); pci_dev_put(pdev); return; } - mch_bar &=3D ~BIT(0); - addr =3D (resource_size_t)(mch_bar + TGL_UNCORE_MMIO_IMC_MEM_OFFSET * pmu= ->pmu_idx); + bar &=3D ~BIT(0); + addr =3D (resource_size_t)(bar + step * pmu->pmu_idx); =20 #ifdef CONFIG_PHYS_ADDR_T_64BIT - pci_read_config_dword(pdev, SNB_UNCORE_PCI_IMC_BAR_OFFSET + 4, &mch_bar); - addr |=3D ((resource_size_t)mch_bar << 32); + pci_read_config_dword(pdev, bar_offset + 4, &bar); + addr |=3D ((resource_size_t)bar << 32); #endif =20 addr +=3D base_offset; @@ -1518,6 +1520,14 @@ static void __uncore_imc_init_box(struct intel_uncor= e_box *box, pci_dev_put(pdev); } =20 +static void __uncore_imc_init_box(struct intel_uncore_box *box, + unsigned int base_offset) +{ + uncore_get_box_mmio_addr(box, base_offset, + SNB_UNCORE_PCI_IMC_BAR_OFFSET, + TGL_UNCORE_MMIO_IMC_MEM_OFFSET); +} + static void tgl_uncore_imc_freerunning_init_box(struct intel_uncore_box *b= ox) { __uncore_imc_init_box(box, 0); @@ -1612,14 +1622,17 @@ static void adl_uncore_mmio_enable_box(struct intel= _uncore_box *box) writel(0, box->io_addr + uncore_mmio_box_ctl(box)); } =20 +#define MMIO_UNCORE_COMMON_OPS() \ + .exit_box =3D uncore_mmio_exit_box, \ + .disable_box =3D adl_uncore_mmio_disable_box, \ + .enable_box =3D adl_uncore_mmio_enable_box, \ + .disable_event =3D intel_generic_uncore_mmio_disable_event, \ + .enable_event =3D intel_generic_uncore_mmio_enable_event, \ + .read_counter =3D uncore_mmio_read_counter, + static struct intel_uncore_ops adl_uncore_mmio_ops =3D { .init_box =3D adl_uncore_imc_init_box, - .exit_box =3D uncore_mmio_exit_box, - .disable_box =3D adl_uncore_mmio_disable_box, - .enable_box =3D adl_uncore_mmio_enable_box, - .disable_event =3D intel_generic_uncore_mmio_disable_event, - .enable_event =3D intel_generic_uncore_mmio_enable_event, - .read_counter =3D uncore_mmio_read_counter, + MMIO_UNCORE_COMMON_OPS() }; =20 #define ADL_UNC_CTL_CHMASK_MASK 0x00000f00 --=20 2.35.1 From nobody Sun Feb 8 20:29:26 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 825471292E5 for ; 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X-CSE-ConnectionGUID: CAoH38RqTyq9wnYC3YgLIw== X-CSE-MsgGUID: Pjrgv2M7TpmvZUmlxMJlUw== X-IronPort-AV: E=McAfee;i="6600,9927,11034"; a="7632425" X-IronPort-AV: E=Sophos;i="6.07,179,1708416000"; d="scan'208";a="7632425" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Apr 2024 07:18:09 -0700 X-CSE-ConnectionGUID: slN87P/jTh2/jA7tLC1ZaA== X-CSE-MsgGUID: 6y9Sw2AgQn2iq5mZE0xGOg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,179,1708416000"; d="scan'208";a="23448356" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmviesa004.fm.intel.com with ESMTP; 04 Apr 2024 07:18:07 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org, irogers@google.com, adrian.hunter@intel.com, alexander.shishkin@linux.intel.com, linux-kernel@vger.kernel.org Cc: ak@linux.intel.com, Kan Liang Subject: [PATCH 2/4] perf/x86/intel/uncore: Add Lunar Lake and Arrow Lake support Date: Thu, 4 Apr 2024 07:17:04 -0700 Message-Id: <20240404141706.1235531-3-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20240404141706.1235531-1-kan.liang@linux.intel.com> References: <20240404141706.1235531-1-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kan Liang The uncore subsystem for Lunar Lake and Arrow Lake are similar to the previous Meteor Lake. The uncore PerfMon registers are located at both MSR and MMIO space. The CBOX, ARB, and iMC are kept. There is no difference from the Meteor Lake. The sNCU is moved to the MMIO space. The HBO is newly added and only be accessed from the MMIO space. Signed-off-by: Kan Liang --- arch/x86/events/intel/uncore.c | 7 ++ arch/x86/events/intel/uncore.h | 2 + arch/x86/events/intel/uncore_snb.c | 117 +++++++++++++++++++++++++++++ 3 files changed, 126 insertions(+) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 258e2cdf28fa..8408303fa41f 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1794,6 +1794,11 @@ static const struct intel_uncore_init_fun mtl_uncore= _init __initconst =3D { .mmio_init =3D adl_uncore_mmio_init, }; =20 +static const struct intel_uncore_init_fun lnl_uncore_init __initconst =3D { + .cpu_init =3D lnl_uncore_cpu_init, + .mmio_init =3D lnl_uncore_mmio_init, +}; + static const struct intel_uncore_init_fun icx_uncore_init __initconst =3D { .cpu_init =3D icx_uncore_cpu_init, .pci_init =3D icx_uncore_pci_init, @@ -1871,6 +1876,8 @@ static const struct x86_cpu_id intel_uncore_match[] _= _initconst =3D { X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, &adl_uncore_init), X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE, &mtl_uncore_init), X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, &mtl_uncore_init), + X86_MATCH_INTEL_FAM6_MODEL(LUNARLAKE_M, &lnl_uncore_init), + X86_MATCH_INTEL_FAM6_MODEL(ARROWLAKE, &lnl_uncore_init), X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &spr_uncore_init), X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X, &spr_uncore_init), X86_MATCH_INTEL_FAM6_MODEL(GRANITERAPIDS_X, &gnr_uncore_init), diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h index 4838502d89ae..edebb5a6c9a0 100644 --- a/arch/x86/events/intel/uncore.h +++ b/arch/x86/events/intel/uncore.h @@ -607,10 +607,12 @@ void skl_uncore_cpu_init(void); void icl_uncore_cpu_init(void); void tgl_uncore_cpu_init(void); void adl_uncore_cpu_init(void); +void lnl_uncore_cpu_init(void); void mtl_uncore_cpu_init(void); void tgl_uncore_mmio_init(void); void tgl_l_uncore_mmio_init(void); void adl_uncore_mmio_init(void); +void lnl_uncore_mmio_init(void); int snb_pci2phy_map_init(int devid); =20 /* uncore_snbep.c */ diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/unc= ore_snb.c index 05fe6e90bd8e..d1605163f11e 100644 --- a/arch/x86/events/intel/uncore_snb.c +++ b/arch/x86/events/intel/uncore_snb.c @@ -252,6 +252,7 @@ DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23"); DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28"); DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31"); DEFINE_UNCORE_FORMAT_ATTR(threshold, threshold, "config:24-29"); +DEFINE_UNCORE_FORMAT_ATTR(threshold2, threshold, "config:24-31"); =20 /* Sandy Bridge uncore support */ static void snb_uncore_msr_enable_event(struct intel_uncore_box *box, stru= ct perf_event *event) @@ -746,6 +747,18 @@ void mtl_uncore_cpu_init(void) uncore_msr_uncores =3D mtl_msr_uncores; } =20 +static struct intel_uncore_type *lnl_msr_uncores[] =3D { + &mtl_uncore_cbox, + &mtl_uncore_arb, + NULL +}; + +void lnl_uncore_cpu_init(void) +{ + mtl_uncore_cbox.num_boxes =3D 4; + uncore_msr_uncores =3D lnl_msr_uncores; +} + enum { SNB_PCI_UNCORE_IMC, }; @@ -1716,3 +1729,107 @@ void adl_uncore_mmio_init(void) } =20 /* end of Alder Lake MMIO uncore support */ + +/* Lunar Lake MMIO uncore support */ +#define LNL_UNCORE_PCI_SAFBAR_OFFSET 0x68 +#define LNL_UNCORE_MAP_SIZE 0x1000 +#define LNL_UNCORE_SNCU_BASE 0xE4B000 +#define LNL_UNCORE_SNCU_CTR 0x390 +#define LNL_UNCORE_SNCU_CTRL 0x398 +#define LNL_UNCORE_SNCU_BOX_CTL 0x380 +#define LNL_UNCORE_GLOBAL_CTL 0x700 +#define LNL_UNCORE_HBO_BASE 0xE54000 +#define LNL_UNCORE_HBO_OFFSET -4096 +#define LNL_UNCORE_HBO_CTR 0x570 +#define LNL_UNCORE_HBO_CTRL 0x550 +#define LNL_UNCORE_HBO_BOX_CTL 0x548 + +#define LNL_UNC_CTL_THRESHOLD 0xff000000 +#define LNL_UNC_RAW_EVENT_MASK (SNB_UNC_CTL_EV_SEL_MASK | \ + SNB_UNC_CTL_UMASK_MASK | \ + SNB_UNC_CTL_EDGE_DET | \ + SNB_UNC_CTL_INVERT | \ + LNL_UNC_CTL_THRESHOLD) + +static struct attribute *lnl_uncore_formats_attr[] =3D { + &format_attr_event.attr, + &format_attr_umask.attr, + &format_attr_edge.attr, + &format_attr_inv.attr, + &format_attr_threshold2.attr, + NULL +}; + +static const struct attribute_group lnl_uncore_format_group =3D { + .name =3D "format", + .attrs =3D lnl_uncore_formats_attr, +}; + +static void lnl_uncore_hbo_init_box(struct intel_uncore_box *box) +{ + uncore_get_box_mmio_addr(box, LNL_UNCORE_HBO_BASE, + LNL_UNCORE_PCI_SAFBAR_OFFSET, + LNL_UNCORE_HBO_OFFSET); +} + +static struct intel_uncore_ops lnl_uncore_hbo_ops =3D { + .init_box =3D lnl_uncore_hbo_init_box, + MMIO_UNCORE_COMMON_OPS() +}; + +static struct intel_uncore_type lnl_uncore_hbo =3D { + .name =3D "hbo", + .num_counters =3D 4, + .num_boxes =3D 2, + .perf_ctr_bits =3D 64, + .perf_ctr =3D LNL_UNCORE_HBO_CTR, + .event_ctl =3D LNL_UNCORE_HBO_CTRL, + .event_mask =3D LNL_UNC_RAW_EVENT_MASK, + .box_ctl =3D LNL_UNCORE_HBO_BOX_CTL, + .mmio_map_size =3D LNL_UNCORE_MAP_SIZE, + .ops =3D &lnl_uncore_hbo_ops, + .format_group =3D &lnl_uncore_format_group, +}; + +static void lnl_uncore_sncu_init_box(struct intel_uncore_box *box) +{ + uncore_get_box_mmio_addr(box, LNL_UNCORE_SNCU_BASE, + LNL_UNCORE_PCI_SAFBAR_OFFSET, + 0); + + if (box->io_addr) + writel(ADL_UNCORE_IMC_CTL_INT, box->io_addr + LNL_UNCORE_GLOBAL_CTL); +} + +static struct intel_uncore_ops lnl_uncore_sncu_ops =3D { + .init_box =3D lnl_uncore_sncu_init_box, + MMIO_UNCORE_COMMON_OPS() +}; + +static struct intel_uncore_type lnl_uncore_sncu =3D { + .name =3D "sncu", + .num_counters =3D 2, + .num_boxes =3D 1, + .perf_ctr_bits =3D 64, + .perf_ctr =3D LNL_UNCORE_SNCU_CTR, + .event_ctl =3D LNL_UNCORE_SNCU_CTRL, + .event_mask =3D LNL_UNC_RAW_EVENT_MASK, + .box_ctl =3D LNL_UNCORE_SNCU_BOX_CTL, + .mmio_map_size =3D LNL_UNCORE_MAP_SIZE, + .ops =3D &lnl_uncore_sncu_ops, + .format_group =3D &lnl_uncore_format_group, +}; + +static struct intel_uncore_type *lnl_mmio_uncores[] =3D { + &adl_uncore_imc, + &lnl_uncore_hbo, + &lnl_uncore_sncu, + NULL +}; + +void lnl_uncore_mmio_init(void) +{ + uncore_mmio_uncores =3D lnl_mmio_uncores; +} + +/* end of Lunar Lake MMIO uncore support */ --=20 2.35.1 From nobody Sun Feb 8 20:29:26 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E19C1129E66 for ; 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charset="utf-8" From: Zhenyu Wang LNL uncore imc freerunning counters keep same as previous HW. Signed-off-by: Zhenyu Wang Signed-off-by: Kan Liang --- arch/x86/events/intel/uncore_snb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/unc= ore_snb.c index d1605163f11e..4cab1bf57602 100644 --- a/arch/x86/events/intel/uncore_snb.c +++ b/arch/x86/events/intel/uncore_snb.c @@ -1824,6 +1824,7 @@ static struct intel_uncore_type *lnl_mmio_uncores[] = =3D { &adl_uncore_imc, &lnl_uncore_hbo, &lnl_uncore_sncu, + &adl_uncore_imc_free_running, NULL }; =20 --=20 2.35.1 From nobody Sun Feb 8 20:29:26 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E3A0129E8A for ; Thu, 4 Apr 2024 14:18:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712240292; cv=none; b=OXM/j6NERFGLy8o9f3YRzwOht/A8HtvPWVw1fMKdIeDZM/RE92BCqbzWDTsIQUQQiBv/DOpvxzX7QEEpO4EzCG6+m1sQ20Eirn2OpWV1FcNHj8XX5DW5Sn8dY7HNLOw8mio2QW82XLO1g/2XT2gPegM+VThVU8NzMyPLwk2QTIk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712240292; c=relaxed/simple; bh=WyGBRp+4Ek1Eean8T0mP193ZzJ1ucRVfqIn46Xxik5E=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=pwAw0jjhgJB5t0ep5Hc4vEuUDXQsAf0dwBKVIDNGUf2V+LtABa2p2mf9NZkqlqSq+sCk4rob3fLSR3PYLFtnKbOZhtcoWITHU6i3Ek+bhdOHZF7ed5H5FYAlRCGHX51oETP8591eVFLvCZfxFrHacBIW5bifxINYAzO7Qhur3Oc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nkObM7iO; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nkObM7iO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712240292; x=1743776292; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WyGBRp+4Ek1Eean8T0mP193ZzJ1ucRVfqIn46Xxik5E=; b=nkObM7iO/+YAf0M9hIjBIz8SMSd7DJr3SjLQWHFF1knCPo3wLkL/VgsY O+7/uViwObYfT6vLFaU48xS1et+dDtoYsUNhKq4gZGL/itdrWYyvxcAtO 8n+ChJLAjM2uMp0OBM1q7dER3glmT/U0rnkyEmM86XC4epRmXlgizgK9y mh24tLTyO8VVnItbqtqsKXwY7ouvdSzZv2KW2hE75KWdplIOGx/uK6KkV 2JwJjE2KK078VpUBnN+wqIwLRSu2STrGH1G6+oYcOzCxUcAA0ygzsjzJO zV1Jyd3iG5pbg9d/65VLUAo9M9frkHVsn7MJl2LBDvocYHhY6lLiUq8Yw A==; X-CSE-ConnectionGUID: /29ZGWJETeyE0nTVIXz8+g== X-CSE-MsgGUID: IEzVLLs5SS6azSa6G993SA== X-IronPort-AV: E=McAfee;i="6600,9927,11034"; a="7632436" X-IronPort-AV: E=Sophos;i="6.07,179,1708416000"; d="scan'208";a="7632436" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Apr 2024 07:18:10 -0700 X-CSE-ConnectionGUID: /nwTIp+TTm2h0SNFh2ORBA== X-CSE-MsgGUID: KYFylQmHQvSGQtkiQZOAag== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,179,1708416000"; d="scan'208";a="23448366" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmviesa004.fm.intel.com with ESMTP; 04 Apr 2024 07:18:08 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org, irogers@google.com, adrian.hunter@intel.com, alexander.shishkin@linux.intel.com, linux-kernel@vger.kernel.org Cc: ak@linux.intel.com, Zhenyu Wang , Kan Liang Subject: [PATCH 4/4] perf/x86/intel/uncore: Use D0:F0 as a default device Date: Thu, 4 Apr 2024 07:17:06 -0700 Message-Id: <20240404141706.1235531-5-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20240404141706.1235531-1-kan.liang@linux.intel.com> References: <20240404141706.1235531-1-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Zhenyu Wang Some uncore PMON registers are located in the MMIO space of the Host Bridge and DRAM Controller device, which is located at D0:F0 for Tiger Lake and later client generation. Use D0:F0 as a default device. So it doesn't need to keep adding the complete Device ID list for each generation anymore. Signed-off-by: Zhenyu Wang Signed-off-by: Kan Liang --- arch/x86/events/intel/uncore_snb.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/unc= ore_snb.c index 4cab1bf57602..8625d6d279c3 100644 --- a/arch/x86/events/intel/uncore_snb.c +++ b/arch/x86/events/intel/uncore_snb.c @@ -1488,6 +1488,10 @@ static struct pci_dev *tgl_uncore_get_mc_dev(void) ids++; } =20 + /* Just try to grab 00:00.0 device */ + if (!mc_dev) + mc_dev =3D pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0)); + return mc_dev; } =20 --=20 2.35.1