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The SoM has been designed as a pin-compatible replacement for the older Armada 388 based SoM. Therefore it supports the same boards and a similar feature set. Most notable upgrades: - 4x Cortex-A72 - 10Gbps SFP - Both eMMC and SD supported at the same time The developer first supporting this product at SolidRun decided to use different filenames for the DTBs: Armada 388 uses the full "clearfog" string while cn9130 uses the abbreviation "cf". This name is already hard-coded in pre-installed vendor u-boot and can not be changed easily. NOTICE IN CASE ANYBODY WANTS TO SELF-UPGRADE: CN9130 SoM has a different footprint from Armada 388 SoM. Components on the carrier board below the SoM may collide causing damage, such as on Clearfog Base. Signed-off-by: Josua Mayer Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/marvell/Makefile | 2 + arch/arm64/boot/dts/marvell/cn9130-cf-base.dts | 178 ++++++++++++ arch/arm64/boot/dts/marvell/cn9130-cf-pro.dts | 367 +++++++++++++++++++++= ++++ arch/arm64/boot/dts/marvell/cn9130-cf.dtsi | 193 +++++++++++++ arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi | 159 +++++++++++ 5 files changed, 899 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/mar= vell/Makefile index 99b8cb3c49e1..019f2251d696 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -28,3 +28,5 @@ dtb-$(CONFIG_ARCH_MVEBU) +=3D cn9130-crb-A.dtb dtb-$(CONFIG_ARCH_MVEBU) +=3D cn9130-crb-B.dtb dtb-$(CONFIG_ARCH_MVEBU) +=3D ac5x-rd-carrier-cn9131.dtb dtb-$(CONFIG_ARCH_MVEBU) +=3D ac5-98dx35xx-rd.dtb +dtb-$(CONFIG_ARCH_MVEBU) +=3D cn9130-cf-base.dtb +dtb-$(CONFIG_ARCH_MVEBU) +=3D cn9130-cf-pro.dtb diff --git a/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts b/arch/arm64/bo= ot/dts/marvell/cn9130-cf-base.dts new file mode 100644 index 000000000000..788a5c302b17 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Josua Mayer + * + * DTS for SolidRun CN9130 Clearfog Base. + * + */ + +/dts-v1/; + +#include +#include + +#include "cn9130.dtsi" +#include "cn9130-sr-som.dtsi" +#include "cn9130-cf.dtsi" + +/ { + model =3D "SolidRun CN9130 Clearfog Base"; + compatible =3D "solidrun,cn9130-clearfog-base", + "solidrun,cn9130-sr-som", "marvell,cn9130"; + + gpio-keys { + compatible =3D "gpio-keys"; + pinctrl-0 =3D <&rear_button_pins>; + pinctrl-names =3D "default"; + + button-0 { + /* The rear SW3 button */ + label =3D "Rear Button"; + gpios =3D <&cp0_gpio1 31 GPIO_ACTIVE_LOW>; + linux,can-disable; + linux,code =3D ; + }; + }; + + rfkill-m2-gnss { + compatible =3D "rfkill-gpio"; + label =3D "m.2 GNSS"; + radio-type =3D "gps"; + /* rfkill-gpio inverts internally */ + shutdown-gpios =3D <&expander0 9 GPIO_ACTIVE_HIGH>; + }; + + /* M.2 is B-keyed, so w-disable is for WWAN */ + rfkill-m2-wwan { + compatible =3D "rfkill-gpio"; + label =3D "m.2 WWAN"; + radio-type =3D "wwan"; + /* rfkill-gpio inverts internally */ + shutdown-gpios =3D <&expander0 8 GPIO_ACTIVE_HIGH>; + }; +}; + +/* SRDS #3 - SGMII 1GE */ +&cp0_eth1 { + phy =3D <&phy1>; + phys =3D <&cp0_comphy3 1>; + phy-mode =3D "sgmii"; + status =3D "okay"; +}; + +&cp0_eth2_phy { + /* + * Configure LEDs default behaviour: + * - LED[0]: link/activity: On/blink (green) + * - LED[1]: link is 100/1000Mbps: On (yellow) + * - LED[2]: high impedance (floating) + */ + marvell,reg-init =3D <3 16 0xf000 0x0a61>; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@0 { + reg =3D <0>; + color =3D ; + function =3D LED_FUNCTION_WAN; + default-state =3D "keep"; + }; + + led@1 { + reg =3D <1>; + color =3D ; + function =3D LED_FUNCTION_WAN; + default-state =3D "keep"; + }; + }; +}; + +&cp0_gpio1 { + sim-select-hog { + gpio-hog; + gpios =3D <27 GPIO_ACTIVE_HIGH>; + output-high; + line-name =3D "sim-select"; + }; +}; + +&cp0_mdio { + phy1: ethernet-phy@1 { + reg =3D <1>; + /* + * Configure LEDs default behaviour: + * - LED[0]: link/activity: On/blink (green) + * - LED[1]: link is 100/1000Mbps: On (yellow) + * - LED[2]: high impedance (floating) + * + * Configure LEDs electrical polarity + * - on-state: low + * - off-state: high (not hi-z, to avoid residual glow) + */ + marvell,reg-init =3D <3 16 0xf000 0x0a61>, + <3 17 0x003f 0x000a>; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@0 { + reg =3D <0>; + color =3D ; + function =3D LED_FUNCTION_LAN; + default-state =3D "keep"; + }; + + led@1 { + reg =3D <1>; + color =3D ; + function =3D LED_FUNCTION_LAN; + default-state =3D "keep"; + }; + }; + }; +}; + +&cp0_pinctrl { + pinctrl-0 =3D <&sim_select_pins>; + pintrl-names =3D "default"; + + rear_button_pins: cp0-rear-button-pins { + marvell,pins =3D "mpp31"; + marvell,function =3D "gpio"; + }; + + sim_select_pins: cp0-sim-select-pins { + marvell,pins =3D "mpp27"; + marvell,function =3D "gpio"; + }; +}; + +/* + * SRDS #4 - USB 3.0 host on M.2 connector + * USB-2.0 Host on Type-A connector + */ +&cp0_usb3_1 { + phys =3D <&cp0_comphy4 1>, <&cp0_utmi1>; + phy-names =3D "comphy", "utmi"; + dr_mode =3D "host"; + status =3D "okay"; +}; + +&expander0 { + m2-full-card-power-off-hog { + gpio-hog; + gpios =3D <2 GPIO_ACTIVE_LOW>; + output-low; + line-name =3D "m2-full-card-power-off"; + }; + + m2-reset-hog { + gpio-hog; + gpios =3D <10 GPIO_ACTIVE_LOW>; + output-low; + line-name =3D "m2-reset"; + }; +}; diff --git a/arch/arm64/boot/dts/marvell/cn9130-cf-pro.dts b/arch/arm64/boo= t/dts/marvell/cn9130-cf-pro.dts new file mode 100644 index 000000000000..0b95d5f7acfd --- /dev/null +++ b/arch/arm64/boot/dts/marvell/cn9130-cf-pro.dts @@ -0,0 +1,367 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Josua Mayer + * + * DTS for SolidRun CN9130 Clearfog Pro. + * + */ + +/dts-v1/; + +#include +#include + +#include "cn9130.dtsi" +#include "cn9130-sr-som.dtsi" +#include "cn9130-cf.dtsi" + +/ { + model =3D "SolidRun CN9130 Clearfog Pro"; + compatible =3D "solidrun,cn9130-clearfog-pro", + "solidrun,cn9130-sr-som", "marvell,cn9130"; + + gpio-keys { + compatible =3D "gpio-keys"; + pinctrl-0 =3D <&rear_button_pins>; + pinctrl-names =3D "default"; + + button-0 { + /* The rear SW3 button */ + label =3D "Rear Button"; + gpios =3D <&cp0_gpio2 0 GPIO_ACTIVE_LOW>; + linux,can-disable; + linux,code =3D ; + }; + }; +}; + +/* SRDS #3 - SGMII 1GE to L2 switch */ +&cp0_eth1 { + phys =3D <&cp0_comphy3 1>; + phy-mode =3D "sgmii"; + status =3D "okay"; + + fixed-link { + speed =3D <1000>; + full-duplex; + }; +}; + +&cp0_eth2_phy { + /* + * Configure LEDs default behaviour similar to switch ports: + * - LED[0]: link/activity: On/blink (green) + * - LED[1]: link is 100/1000Mbps: On (red) + * - LED[2]: high impedance (floating) + * + * Switch port defaults: + * - LED0: link/activity: On/blink (green) + * - LED1: link is 1000Mbps: On (red) + * + * Identical configuration is impossible with hardware offload. + */ + marvell,reg-init =3D <3 16 0xf000 0x0a61>; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@0 { + reg =3D <0>; + color =3D ; + function =3D LED_FUNCTION_WAN; + label =3D "LED2"; + default-state =3D "keep"; + }; + + led@1 { + reg =3D <1>; + color =3D ; + function =3D LED_FUNCTION_WAN; + label =3D "LED1"; + default-state =3D "keep"; + }; + }; +}; + +&cp0_mdio { + ethernet-switch@4 { + compatible =3D "marvell,mv88e6085"; + reg =3D <4>; + pinctrl-0 =3D <&dsa_clk_pins &dsa_pins>; + pinctrl-names =3D "default"; + reset-gpios =3D <&cp0_gpio1 27 GPIO_ACTIVE_LOW>; + interrupt-parent =3D <&cp0_gpio1>; + interrupts =3D <29 IRQ_TYPE_EDGE_FALLING>; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethernet-port@0 { + reg =3D <0>; + label =3D "lan5"; + phy =3D <&switch0phy0>; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@0 { + reg =3D <0>; + color =3D ; + function =3D LED_FUNCTION_LAN; + label =3D "LED12"; + default-state =3D "keep"; + }; + + led@1 { + reg =3D <1>; + color =3D ; + function =3D LED_FUNCTION_LAN; + label =3D "LED11"; + default-state =3D "keep"; + }; + }; + }; + + ethernet-port@1 { + reg =3D <1>; + label =3D "lan4"; + phy =3D <&switch0phy1>; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@0 { + reg =3D <0>; + color =3D ; + function =3D LED_FUNCTION_LAN; + label =3D "LED10"; + default-state =3D "keep"; + }; + + led@1 { + reg =3D <1>; + color =3D ; + function =3D LED_FUNCTION_LAN; + label =3D "LED9"; + default-state =3D "keep"; + }; + }; + }; + + ethernet-port@2 { + reg =3D <2>; + label =3D "lan3"; + phy =3D <&switch0phy2>; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@0 { + reg =3D <0>; + color =3D ; + function =3D LED_FUNCTION_LAN; + label =3D "LED8"; + default-state =3D "keep"; + }; + + led@1 { + reg =3D <1>; + color =3D ; + function =3D LED_FUNCTION_LAN; + label =3D "LED7"; + default-state =3D "keep"; + }; + }; + }; + + ethernet-port@3 { + reg =3D <3>; + label =3D "lan2"; + phy =3D <&switch0phy3>; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@0 { + reg =3D <0>; + color =3D ; + function =3D LED_FUNCTION_LAN; + label =3D "LED6"; + default-state =3D "keep"; + }; + + led@1 { + reg =3D <1>; + color =3D ; + function =3D LED_FUNCTION_LAN; + label =3D "LED5"; + default-state =3D "keep"; + }; + }; + }; + + ethernet-port@4 { + reg =3D <4>; + label =3D "lan1"; + phy =3D <&switch0phy4>; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@0 { + reg =3D <0>; + color =3D ; + function =3D LED_FUNCTION_LAN; + label =3D "LED4"; + default-state =3D "keep"; + }; + + led@1 { + reg =3D <1>; + color =3D ; + function =3D LED_FUNCTION_LAN; + label =3D "LED3"; + default-state =3D "keep"; + }; + }; + }; + + ethernet-port@5 { + reg =3D <5>; + label =3D "cpu"; + ethernet =3D <&cp0_eth1>; + phy-mode =3D "sgmii"; + + fixed-link { + speed =3D <1000>; + full-duplex; + }; + }; + + ethernet-port@6 { + reg =3D <6>; + label =3D "lan6"; + phy-mode =3D "rgmii"; + + /* + * Because of mdio address conflict the + * external phy is not readable. + * Force a fixed link instead. + */ + fixed-link { + speed =3D <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + switch0phy0: ethernet-phy@0 { + reg =3D <0x0>; + }; + + switch0phy1: ethernet-phy@1 { + reg =3D <0x1>; + /* + * Indirectly configure default behaviour + * for port lan6 leds behind external phy. + * Internal PHYs are not using page 3, + * therefore writing to it is safe. + */ + marvell,reg-init =3D <3 16 0xf000 0x0a61>; + }; + + switch0phy2: ethernet-phy@2 { + reg =3D <0x2>; + }; + + switch0phy3: ethernet-phy@3 { + reg =3D <0x3>; + }; + + switch0phy4: ethernet-phy@4 { + reg =3D <0x4>; + }; + }; + + /* + * There is an external phy on the switch mdio bus. + * Because its mdio address collides with internal phys, + * it is not readable. + * + * mdio-external { + * compatible =3D "marvell,mv88e6xxx-mdio-external"; + * #address-cells =3D <1>; + * #size-cells =3D <0>; + * + * ethernet-phy@1 { + * reg =3D <0x1>; + * }; + * }; + */ + }; +}; + +/* SRDS #4 - miniPCIe (CON2) */ +&cp0_pcie1 { + num-lanes =3D <1>; + phys =3D <&cp0_comphy4 1>; + /* dw-pcie inverts internally */ + reset-gpios =3D <&expander0 2 GPIO_ACTIVE_HIGH>; + status =3D "okay"; +}; + +&cp0_pinctrl { + dsa_clk_pins: cp0-dsa-clk-pins { + marvell,pins =3D "mpp40"; + marvell,function =3D "synce1"; + }; + + dsa_pins: cp0-dsa-pins { + marvell,pins =3D "mpp27", "mpp29"; + marvell,function =3D "gpio"; + }; + + rear_button_pins: cp0-rear-button-pins { + marvell,pins =3D "mpp32"; + marvell,function =3D "gpio"; + }; +}; + +/* + * USB-2.0 Host on Type-A connector + */ +&cp0_usb3_1 { + phys =3D <&cp0_utmi1>; + phy-names =3D "utmi"; + dr_mode =3D "host"; + status =3D "okay"; +}; + +&expander0 { + /* CON2 */ + pcie1-0-clkreq-hog { + gpio-hog; + gpios =3D <4 GPIO_ACTIVE_LOW>; + input; + line-name =3D "pcie1.0-clkreq"; + }; + + /* CON2 */ + pcie1-0-w-disable-hog { + gpio-hog; + gpios =3D <7 GPIO_ACTIVE_LOW>; + output-low; + line-name =3D "pcie1.0-w-disable"; + }; +}; diff --git a/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi b/arch/arm64/boot/d= ts/marvell/cn9130-cf.dtsi new file mode 100644 index 000000000000..53aedddf0e26 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Josua Mayer + * + * DTS for common base of SolidRun CN9130 Clearfog Base and Pro. + * + */ + +/ { + aliases { + i2c1 =3D &cp0_i2c1; + mmc1 =3D &cp0_sdhci0; + }; + + reg_usb3_vbus0: regulator-usb3-vbus0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vbus0"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&expander0 6 GPIO_ACTIVE_LOW>; + }; + + sfp: sfp { + compatible =3D "sff,sfp"; + i2c-bus =3D <&cp0_i2c1>; + los-gpios =3D <&expander0 12 GPIO_ACTIVE_HIGH>; + mod-def0-gpios =3D <&expander0 15 GPIO_ACTIVE_LOW>; + tx-disable-gpios =3D <&expander0 14 GPIO_ACTIVE_HIGH>; + tx-fault-gpios =3D <&expander0 13 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt =3D <2000>; + }; +}; + +/* SRDS #2 - SFP+ 10GE */ +&cp0_eth0 { + managed =3D "in-band-status"; + phys =3D <&cp0_comphy2 0>; + phy-mode =3D "10gbase-r"; + sfp =3D <&sfp>; + status =3D "okay"; +}; + +&cp0_i2c0 { + expander0: gpio-expander@20 { + compatible =3D "nxp,pca9555"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + pinctrl-0 =3D <&expander0_pins>; + pinctrl-names =3D "default"; + interrupt-parent =3D <&cp0_gpio1>; + interrupts =3D <4 IRQ_TYPE_LEVEL_LOW>; + + /* CON3 */ + pcie2-0-clkreq-hog { + gpio-hog; + gpios =3D <0 GPIO_ACTIVE_LOW>; + input; + line-name =3D "pcie2.0-clkreq"; + }; + + /* CON3 */ + pcie2-0-w-disable-hog { + gpio-hog; + gpios =3D <3 GPIO_ACTIVE_LOW>; + output-low; + line-name =3D "pcie2.0-w-disable"; + }; + + usb3-ilimit-hog { + gpio-hog; + gpios =3D <5 GPIO_ACTIVE_LOW>; + input; + line-name =3D "usb3-current-limit"; + }; + + m2-devslp-hog { + gpio-hog; + gpios =3D <11 GPIO_ACTIVE_HIGH>; + output-low; + line-name =3D "m.2 devslp"; + }; + }; + + /* The MCP3021 supports standard and fast modes */ + adc@4c { + compatible =3D "microchip,mcp3021"; + reg =3D <0x4c>; + }; + + carrier_eeprom: eeprom@52 { + compatible =3D "atmel,24c02"; + reg =3D <0x52>; + pagesize =3D <8>; + }; +}; + +&cp0_i2c1 { + /* + * Routed to SFP, M.2, mikrobus, and miniPCIe + * SFP limits this to 100kHz, and requires an AT24C01A/02/04 with + * address pins tied low, which takes addresses 0x50 and 0x51. + * Mikrobus doesn't specify beyond an I2C bus being present. + * PCIe uses ARP to assign addresses, or 0x63-0x64. + */ + clock-frequency =3D <100000>; + pinctrl-0 =3D <&cp0_i2c1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +/* SRDS #5 - miniPCIe (CON3) */ +&cp0_pcie2 { + num-lanes =3D <1>; + phys =3D <&cp0_comphy5 2>; + /* dw-pcie inverts internally */ + reset-gpios =3D <&expander0 1 GPIO_ACTIVE_HIGH>; + status =3D "okay"; +}; + +&cp0_pinctrl { + cp0_i2c1_pins: cp0-i2c1-pins { + marvell,pins =3D "mpp35", "mpp36"; + marvell,function =3D "i2c1"; + }; + + cp0_mmc0_pins: cp0-mmc0-pins { + marvell,pins =3D "mpp43", "mpp56", "mpp57", "mpp58", + "mpp59", "mpp60", "mpp61"; + marvell,function =3D "sdio"; + }; + + mikro_spi_pins: cp0-spi1-cs1-pins { + marvell,pins =3D "mpp12"; + marvell,function =3D "spi1"; + }; + + mikro_uart_pins: cp0-uart-pins { + marvell,pins =3D "mpp2", "mpp3"; + marvell,function =3D "uart1"; + }; + + expander0_pins: cp0-expander0-pins { + marvell,pins =3D "mpp4"; + marvell,function =3D "gpio"; + }; +}; + +/* SRDS #0 - SATA on M.2 connector */ +&cp0_sata0 { + phys =3D <&cp0_comphy0 1>; + status =3D "okay"; + + /* only port 1 is available */ + /delete-node/ sata-port@0; +}; + +/* microSD */ +&cp0_sdhci0 { + pinctrl-0 =3D <&cp0_mmc0_pins>; + pinctrl-names =3D "default"; + bus-width =3D <4>; + no-1-8-v; + status =3D "okay"; +}; + +&cp0_spi1 { + /* CS1 for mikrobus */ + pinctrl-0 =3D <&cp0_spi1_pins &mikro_spi_pins>; +}; + +/* + * SRDS #1 - 3.0 Host on Type-A connector + * USB-2.0 Host on mPCI-e connector (CON3) + */ +&cp0_usb3_0 { + phys =3D <&cp0_comphy1 0>, <&cp0_utmi0>; + phy-names =3D "comphy", "utmi"; + vbus-supply =3D <®_usb3_vbus0>; + dr_mode =3D "host"; + status =3D "okay"; +}; + +&cp0_utmi { + status =3D "okay"; +}; + +/* mikrobus uart */ +&cp0_uart0 { + pinctrl-0 =3D <&mikro_uart_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi b/arch/arm64/bo= ot/dts/marvell/cn9130-sr-som.dtsi new file mode 100644 index 000000000000..ec08066fb6e8 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Josua Mayer + * + */ + +#include + +/ { + model =3D "SolidRun CN9130 SoM"; + compatible =3D "solidrun,cn9130-sr-som", "marvell,cn9130"; + + aliases { + /* label nics like armada-388 som */ + ethernet0 =3D &cp0_eth2; + ethernet1 =3D &cp0_eth1; + ethernet2 =3D &cp0_eth0; + i2c0 =3D &cp0_i2c0; + mmc0 =3D &ap_sdhci0; + rtc0 =3D &cp0_rtc; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + v_1_8: regulator-1-8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + /* requires assembly of R9307 */ + vhv: regulator-vhv-1-8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vhv-1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + pinctrl-0 =3D <&cp0_reg_vhv_pins>; + pinctrl-names =3D "default"; + gpio =3D <&cp0_gpio2 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&ap_pinctrl { + ap_mmc0_pins: ap-mmc0-pins { + marvell,pins =3D "mpp0", "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", + "mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp12"; + marvell,function =3D "sdio"; + /* + * mpp12 is emmc reset, function should be sdio (hw_rst), + * but pinctrl-mvebu does not support this. + * + * From pinctrl-mvebu.h: + * "The name will be used to switch to this setting in DT description, e= .g. + * marvell,function =3D "uart2". subname is only for debugging purposes." + */ + }; +}; + +&ap_sdhci0 { + bus-width =3D <8>; + pinctrl-0 =3D <&ap_mmc0_pins>; + pinctrl-names =3D "default"; + vqmmc-supply =3D <&v_1_8>; + status =3D "okay"; +}; + +&cp0_ethernet { + status =3D "okay"; +}; + +/* for assembly with phy */ +&cp0_eth2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_eth2_pins>; + phy-mode =3D "rgmii-id"; + phy =3D <&cp0_eth2_phy>; + status =3D "okay"; +}; + +&cp0_i2c0 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_i2c0_pins>; + clock-frequency =3D <100000>; + status =3D "okay"; + + som_eeprom: eeprom@53 { + compatible =3D "atmel,24c02"; + reg =3D <0x53>; + pagesize =3D <8>; + }; +}; + +&cp0_mdio { + status =3D "okay"; + pinctrl-0 =3D <&cp0_mdio_pins>; + + /* assembly option */ + cp0_eth2_phy: ethernet-phy@0 { + reg =3D <0>; + }; +}; + +&cp0_spi1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cp0_spi1_pins>; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <10000000>; + }; +}; + +&cp0_syscon0 { + cp0_pinctrl: pinctrl { + compatible =3D "marvell,cp115-standalone-pinctrl"; + + cp0_eth2_pins: cp0-ge2-rgmii-pins { + marvell,pins =3D "mpp44", "mpp45", "mpp46", "mpp47", + "mpp48", "mpp49", "mpp50", "mpp51", + "mpp52", "mpp53", "mpp54", "mpp55"; + /* docs call it "ge2", but cp110-pinctrl "ge1" */ + marvell,function =3D "ge1"; + }; + + cp0_i2c0_pins: cp0-i2c0-pins { + marvell,pins =3D "mpp37", "mpp38"; + marvell,function =3D "i2c0"; + }; + + cp0_mdio_pins: cp0-mdio-pins { + marvell,pins =3D "mpp40", "mpp41"; + marvell,function =3D "ge"; + }; + + cp0_spi1_pins: cp0-spi1-pins { + marvell,pins =3D "mpp13", "mpp14", "mpp15", "mpp16"; + marvell,function =3D "spi1"; + }; + + cp0_reg_vhv_pins: cp0-reg-vhv-pins { + marvell,pins =3D "mpp41"; + marvell,function =3D "gpio"; + }; + }; +}; + +/* AP default console */ +&uart0 { + pinctrl-0 =3D <&uart0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; --=20 2.35.3