From nobody Tue Feb 10 19:01:01 2026 Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E31F14A4C6; Wed, 3 Apr 2024 15:15:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712157312; cv=none; b=QQzSNP0DyllKLOpj0XONBPckZIpbrYrN9JLuGvKNAhML0v17SYKwbxMLacv790Rxs3TtjyGhJyjBzpzpIoRha8g8MoHBg9c5eWGOETQr0UdJBpko8uvFhRX/BU8mFOT2KX8gQGJmAMccxg7OKwXJ3Urvj4hEv978W5S1CBHM6q0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712157312; c=relaxed/simple; bh=xRT47/6InyVfuKw2nn7R8WolyO2LrrsH72AfgvyYriU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iCcEfOlbFQxoqR0zthfxuX7TYnAmRUU862fQM/WkSB50wo7kclm+eszPjXVI4HMdKtnKR4UPLqRTvWL8un8LSdJvRWAjeGicfv6RPjtvceM9NtAoXPJJvbLMVw1/hi3RE+0WFds0qUYxO1WoF3yBDiv3fGxv6Oj2LLPBke4nBrQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Wz0JB3oN; arc=none smtp.client-ip=209.85.167.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Wz0JB3oN" Received: by mail-lf1-f41.google.com with SMTP id 2adb3069b0e04-516c116f480so381679e87.2; Wed, 03 Apr 2024 08:15:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1712157309; x=1712762109; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nj5TDWQVb2XSTc84tXGHgdC1SlhtLQsmEzRGKgn31fo=; b=Wz0JB3oNL5OAzJAaokMR9+eMURUwiFBJftCDxwOZU7+51Y1RooFLR1QhZkHJVF48KT mvnwbV6ECs5BU6vIKOjlTccuHvC7KvJDKoOjf3xtYf0UzViFUCeGlVIi7mT2PzX4betA Y7rXtp6HkEjeGcchGdgrk++CbrUwA1EiwEYCeebiO4ncBT5VEFMTmECftxOOoy+N7uIV EoVNssVX+4QgTWDcrCDrxqvs/u23bSZwQcWNlm7AiGKXlM34zwldP9B2sCSUfg41zzY7 iXmxJlMSNISKhDcMVQgOJlFkxO+hPg708j8hjr0fooVrxvdXmmUmdGt8g4rZu5tb9Kcz t5+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712157309; x=1712762109; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nj5TDWQVb2XSTc84tXGHgdC1SlhtLQsmEzRGKgn31fo=; b=wlZXH8pqMCTJcwnT/EHwmjq0QX+oudOYGqlh9Yik8hUwJiKlES+SBwTCr9HGX/LGrH +3qgF8tiHO2kUEnFiUjsId9ILa2K0mxQM28PGqEv/T0RNOyYIpMGr1TM2y/q3lqaLUYU yQawNKH4blS3D3f5D99P6ftshuQ5+ApVkxvMYiDPfFUUHJE5Sa1kHDGmvD5iAJLRQyOy IJl09nS8gnnCrcbpTLKHmHE4nTZOfArmjsIcw6wnqe63m5g8zgFwkILXONASbAuGvP3d oguPd3WcfJ1DaZKrwCl5JeC5NYOqo5tuhirnWAqn3zDl5tLYRmmtplKtGPSC5fc6ZtY9 VI0w== X-Forwarded-Encrypted: i=1; AJvYcCXJwfhfOjJ94pQsamS1+4Ak2w5wk+H4CgPviDVYwhKY8/uk5wmHe/kS3ItErx+j1NJDIbkLTyMqqn/VA+Dj7UQLYwYHfUuFdBvgoOANbo73xS75Z5JfVmWubRaxUP55duxADoKg6fAhCg== X-Gm-Message-State: AOJu0YyiXHIts5TbRnGYa/uc94p1zvEL5XrxjvcD+RKixzk3Wc75AmJe 0v5Z3z1ZVGmfKf8UiIdFbyJivhkQXBzdLgMgjINtcgl3YJKlwN5M X-Google-Smtp-Source: AGHT+IFlIr9UEuT5wVeqplQbAjOeG0sFykcRo47FfL206kz0fVfObrck+iFqq6Xhb35CszEyyzMZMQ== X-Received: by 2002:a05:6512:344d:b0:513:bad6:cf03 with SMTP id j13-20020a056512344d00b00513bad6cf03mr1666922lfr.16.1712157308646; Wed, 03 Apr 2024 08:15:08 -0700 (PDT) Received: from yoga-710.tas.nnz-ipc.net ([178.218.200.115]) by smtp.gmail.com with ESMTPSA id d6-20020a0565123d0600b00515c1b1fb85sm2055092lfv.233.2024.04.03.08.15.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 08:15:08 -0700 (PDT) From: Dmitry Yashin To: Heiko Stuebner , linux-rockchip@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dmitry Yashin Subject: [PATCH v2 2/3] arm64: dts: rockchip: add Forlinx FET3588-C Date: Wed, 3 Apr 2024 20:12:28 +0500 Message-ID: <20240403151229.30577-3-dmt.yashin@gmail.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240403151229.30577-1-dmt.yashin@gmail.com> References: <20240403151229.30577-1-dmt.yashin@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" FET3588-C is an System on Module made by Forlinx based on Rockchip RK3588. This SoM used by OK3588-C Board. FET3588-C features: - Rockchip RK3588 - LPDDR4 4/8 GB - eMMC 32/64 GB Add support for Forlinx FET3588-C SoM. Signed-off-by: Dmitry Yashin --- Changes in v2: - rename dtsi to rk3588-fet3588-c - reorder regulator nodes - reorder properties in sdhci - drop regulator-always-on from vdd_gpu_s0 - enable tsadc .../boot/dts/rockchip/rk3588-fet3588-c.dtsi | 558 ++++++++++++++++++ 1 file changed, 558 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi b/arch/arm6= 4/boot/dts/rockchip/rk3588-fet3588-c.dtsi new file mode 100644 index 000000000000..47e64d547ea9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi @@ -0,0 +1,558 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include +#include +#include +#include "rk3588.dtsi" + +/ { + compatible =3D "forlinx,fet3588-c", "rockchip,rk3588"; + + aliases { + mmc0 =3D &sdhci; + }; + + chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&led_rgb_b>; + + io-led { + function =3D LED_FUNCTION_STATUS; + color =3D ; + gpios =3D <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + }; + + pcie20_avdd0v85: pcie20-avdd0v85-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "pcie20_avdd0v85"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + vin-supply =3D <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "pcie20_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "pcie30_avdd0v75"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + vin-supply =3D <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&avcc_1v8_s0>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc4v0_sys: vcc4v0-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc4v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <4000000>; + regulator-max-microvolt =3D <4000000>; + vin-supply =3D <&vcc12v_dcin>; + }; +}; + +&combphy0_ps { + status =3D "okay"; +}; + +&combphy1_ps { + status =3D "okay"; +}; + +&combphy2_psu { + status =3D "okay"; +}; + +&cpu_b0 { + cpu-supply =3D <&vdd_cpu_big0_s0>; + mem-supply =3D <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply =3D <&vdd_cpu_big0_s0>; + mem-supply =3D <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply =3D <&vdd_cpu_big1_s0>; + mem-supply =3D <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply =3D <&vdd_cpu_big1_s0>; + mem-supply =3D <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply =3D <&vdd_cpu_lit_s0>; + mem-supply =3D <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l1 { + cpu-supply =3D <&vdd_cpu_lit_s0>; + mem-supply =3D <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l2 { + cpu-supply =3D <&vdd_cpu_lit_s0>; + mem-supply =3D <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l3 { + cpu-supply =3D <&vdd_cpu_lit_s0>; + mem-supply =3D <&vdd_cpu_lit_mem_s0>; +}; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0m2_xfer>; + status =3D "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible =3D "rockchip,rk8602"; + reg =3D <0x42>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible =3D "rockchip,rk8603", "rockchip,rk8602"; + reg =3D <0x43>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1m2_xfer>; + + vdd_npu_s0: regulator@42 { + compatible =3D "rockchip,rk8602"; + reg =3D <0x42>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&pinctrl { + leds { + led_rgb_b: led-rgb-b { + rockchip,pins =3D <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdhci { + bus-width =3D <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status =3D "okay"; +}; + +&spi2 { + status =3D "okay"; + assigned-clocks =3D <&cru CLK_SPI2>; + assigned-clock-rates =3D <200000000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi2m2_cs0 &spi2m2_pins>; + num-cs =3D <1>; + + pmic@0 { + compatible =3D "rockchip,rk806"; + spi-max-frequency =3D <1000000>; + reg =3D <0x0>; + + interrupt-parent =3D <&gpio0>; + interrupts =3D <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + system-power-controller; + + vcc1-supply =3D <&vcc5v0_sys>; + vcc2-supply =3D <&vcc5v0_sys>; + vcc3-supply =3D <&vcc5v0_sys>; + vcc4-supply =3D <&vcc5v0_sys>; + vcc5-supply =3D <&vcc5v0_sys>; + vcc6-supply =3D <&vcc5v0_sys>; + vcc7-supply =3D <&vcc5v0_sys>; + vcc8-supply =3D <&vcc5v0_sys>; + vcc9-supply =3D <&vcc5v0_sys>; + vcc10-supply =3D <&vcc5v0_sys>; + vcc11-supply =3D <&vcc_2v0_pldo_s3>; + vcc12-supply =3D <&vcc5v0_sys>; + vcc13-supply =3D <&vcc_1v1_nldo_s3>; + vcc14-supply =3D <&vcc_1v1_nldo_s3>; + vcca-supply =3D <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells =3D <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_gpu_s0"; + regulator-enable-ramp-delay =3D <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <750000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <900000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <2000000>; + regulator-max-microvolt =3D <2000000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-name =3D "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status =3D "okay"; +}; + +&uart2 { + pinctrl-0 =3D <&uart2m0_xfer>; + status =3D "okay"; +}; --=20 2.39.2