From nobody Mon Feb 9 10:26:51 2026 Received: from mail-lf1-f42.google.com (mail-lf1-f42.google.com [209.85.167.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15A4014BF96; Wed, 3 Apr 2024 15:15:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712157310; cv=none; b=oTBI2YTLJx1J/exzazRqTTei9nVTQWCBX8a2xO36tcj+oCynYUBVhkf/xFo6iFQqS6WGgqMxAcZYPqAYo5a6lihldNF2D1/EAlGr5l/SowfNiBtmJyUawRTbOxt6MS9Yf3qkLy7KE8CfzR750w/wn2WAjrRKZlicTfKOJ4lXFXk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712157310; c=relaxed/simple; bh=uTHBJcc7y/HIoMrmE5WnHMHHOZMMQgUixx1II2fzdt4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=V10HVjFVfGLc6cYJKslgX9j5+0F1EHoV8R7XQHaWxb6qUnrXX9ndmus+JwrLeAXkXarSKBvzXkI0ng4ERskImYK9dl3Szk8HqtLA+22DA3oulKDGLpdLHWc/K8bdTWk5rUI0nhM1uvpez6RFPPVX844RgS4ksCD53tQ25+PQVCg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=PZT1g5gm; arc=none smtp.client-ip=209.85.167.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PZT1g5gm" Received: by mail-lf1-f42.google.com with SMTP id 2adb3069b0e04-515a68d45faso7467692e87.3; Wed, 03 Apr 2024 08:15:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1712157307; x=1712762107; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=K9DvDDhS7AAIoJbW8z9CAGKW4h0e01rZII/6xw2xvNo=; b=PZT1g5gmH8vauDh4xBMSxBVKp+M92Ayxh/i/QJRiGdPj8YrqCzaqE+FePCTMLnRKuy fbxNd4zCZAVGvQfWMmRRTRycmR3KjlWfYlptMnfgAixJsd00VO5VyYzb/CPy6kR5Zvxn U/I1Ij7GvzzG+9d26F5IobplMOwm3zciRuZtYeXGjFB3CqMK0UlCdc3I7xLyt2NGOrRO v0BJUJkmeqvQjQdx05+NwrBUped5viCu8mHHRwg+e0T5wMC+Wj5SaYcAUokAobMhV+yQ G0Uqa8OmN62ciqnrQUpkAEOoHeWXn9COqLzfVyUWnSkex6k8OsoIejnE093mlHT6xhGJ 5uJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712157307; x=1712762107; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K9DvDDhS7AAIoJbW8z9CAGKW4h0e01rZII/6xw2xvNo=; b=HVObhGs3TJx1ORIpnNow4Azipp7WLuW7usz6k7CvX3immWSg7dFBeBBrcNfMBt7ggt iou7d7k6BcvS7eFEJqwWJC7DeuaHuSPkRvpz/L0sUZBXsEbqEOsoMKn1/w4OY/tqpSeO 9NRWJUDLqvpMS7cM1H5O0/DTjZpLxRy03s7hL5ZNncpoN1G7z7t2sashwjaiMzSXJAMj 1jZ2D9Q2+Y+6EthpMH71Yt41pNEKCBuDCW/TpSNrJHvJxnMJzF5TVJj659B+benOXIKt yKW0+aEqL0ADWZrqlUlOIld0ym7+BWBAa8A4w8SKBPUj3udYKv8+9bKeqEG9yVTO8MLL oJVQ== X-Forwarded-Encrypted: i=1; AJvYcCV7jUNAs2RnIyNGJFTyv2fc5c4sqmlxkKvscPJlQqpxxvv/RaONqtpx8+oc3Uj/YzBfNJJtNIXUNoiE8esAsg3G0hqcqt9KOizdiW9r8jPpvpc+ybf58YEOvkWlYPVi726YAyp94o7E2A== X-Gm-Message-State: AOJu0Yy4A3sJL1XylEjSbHmxlhw9tDbiyCXl2HYjGYf3pEShbmJPKLOq kQyzCew9qOnUnSBRoWKW8I2R1q9nKlM4+pk7p419q9rBtzHyvuWu X-Google-Smtp-Source: AGHT+IElyLvQavifnocrB9GexBBa7fY1VWFgDzAzVxIUg7DTS2DEPfT1SI7ZYNsjLQcPQdpLzjfp6Q== X-Received: by 2002:a19:6459:0:b0:515:d10b:522a with SMTP id b25-20020a196459000000b00515d10b522amr9939503lfj.30.1712157306999; Wed, 03 Apr 2024 08:15:06 -0700 (PDT) Received: from yoga-710.tas.nnz-ipc.net ([178.218.200.115]) by smtp.gmail.com with ESMTPSA id d6-20020a0565123d0600b00515c1b1fb85sm2055092lfv.233.2024.04.03.08.15.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 08:15:06 -0700 (PDT) From: Dmitry Yashin To: Heiko Stuebner , linux-rockchip@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dmitry Yashin , Conor Dooley Subject: [PATCH v2 1/3] dt-bindings: arm: rockchip: add Forlinx FET3588-C Date: Wed, 3 Apr 2024 20:12:27 +0500 Message-ID: <20240403151229.30577-2-dmt.yashin@gmail.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240403151229.30577-1-dmt.yashin@gmail.com> References: <20240403151229.30577-1-dmt.yashin@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" FET3588-C is an System on Module made by Forlinx based on Rockchip RK3588. This SoM used by OK3588-C Board. FET3588-C features: - Rockchip RK3588 - LPDDR4 4/8 GB - eMMC 32/64 GB Add devicetree binding for Forlinx FET3588-C SoM. Signed-off-by: Dmitry Yashin Acked-by: Conor Dooley --- (no changes since v1) Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 99bd5e2c76a0..2e61c3980444 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -198,6 +198,13 @@ properties: - const: firefly,rk3568-roc-pc - const: rockchip,rk3568 =20 + - description: Forlinx FET3588-C SoM + items: + - enum: + - forlinx,ok3588-c + - const: forlinx,fet3588-c + - const: rockchip,rk3588 + - description: FriendlyElec NanoPi R2 series boards items: - enum: --=20 2.39.2 From nobody Mon Feb 9 10:26:51 2026 Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E31F14A4C6; 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Wed, 03 Apr 2024 08:15:08 -0700 (PDT) Received: from yoga-710.tas.nnz-ipc.net ([178.218.200.115]) by smtp.gmail.com with ESMTPSA id d6-20020a0565123d0600b00515c1b1fb85sm2055092lfv.233.2024.04.03.08.15.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 08:15:08 -0700 (PDT) From: Dmitry Yashin To: Heiko Stuebner , linux-rockchip@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dmitry Yashin Subject: [PATCH v2 2/3] arm64: dts: rockchip: add Forlinx FET3588-C Date: Wed, 3 Apr 2024 20:12:28 +0500 Message-ID: <20240403151229.30577-3-dmt.yashin@gmail.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240403151229.30577-1-dmt.yashin@gmail.com> References: <20240403151229.30577-1-dmt.yashin@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" FET3588-C is an System on Module made by Forlinx based on Rockchip RK3588. This SoM used by OK3588-C Board. FET3588-C features: - Rockchip RK3588 - LPDDR4 4/8 GB - eMMC 32/64 GB Add support for Forlinx FET3588-C SoM. Signed-off-by: Dmitry Yashin --- Changes in v2: - rename dtsi to rk3588-fet3588-c - reorder regulator nodes - reorder properties in sdhci - drop regulator-always-on from vdd_gpu_s0 - enable tsadc .../boot/dts/rockchip/rk3588-fet3588-c.dtsi | 558 ++++++++++++++++++ 1 file changed, 558 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi b/arch/arm6= 4/boot/dts/rockchip/rk3588-fet3588-c.dtsi new file mode 100644 index 000000000000..47e64d547ea9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi @@ -0,0 +1,558 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include +#include +#include +#include "rk3588.dtsi" + +/ { + compatible =3D "forlinx,fet3588-c", "rockchip,rk3588"; + + aliases { + mmc0 =3D &sdhci; + }; + + chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&led_rgb_b>; + + io-led { + function =3D LED_FUNCTION_STATUS; + color =3D ; + gpios =3D <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + }; + + pcie20_avdd0v85: pcie20-avdd0v85-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "pcie20_avdd0v85"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + vin-supply =3D <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "pcie20_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "pcie30_avdd0v75"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + vin-supply =3D <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&avcc_1v8_s0>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc4v0_sys: vcc4v0-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc4v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <4000000>; + regulator-max-microvolt =3D <4000000>; + vin-supply =3D <&vcc12v_dcin>; + }; +}; + +&combphy0_ps { + status =3D "okay"; +}; + +&combphy1_ps { + status =3D "okay"; +}; + +&combphy2_psu { + status =3D "okay"; +}; + +&cpu_b0 { + cpu-supply =3D <&vdd_cpu_big0_s0>; + mem-supply =3D <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply =3D <&vdd_cpu_big0_s0>; + mem-supply =3D <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply =3D <&vdd_cpu_big1_s0>; + mem-supply =3D <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply =3D <&vdd_cpu_big1_s0>; + mem-supply =3D <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply =3D <&vdd_cpu_lit_s0>; + mem-supply =3D <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l1 { + cpu-supply =3D <&vdd_cpu_lit_s0>; + mem-supply =3D <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l2 { + cpu-supply =3D <&vdd_cpu_lit_s0>; + mem-supply =3D <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l3 { + cpu-supply =3D <&vdd_cpu_lit_s0>; + mem-supply =3D <&vdd_cpu_lit_mem_s0>; +}; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0m2_xfer>; + status =3D "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible =3D "rockchip,rk8602"; + reg =3D <0x42>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible =3D "rockchip,rk8603", "rockchip,rk8602"; + reg =3D <0x43>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1m2_xfer>; + + vdd_npu_s0: regulator@42 { + compatible =3D "rockchip,rk8602"; + reg =3D <0x42>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&pinctrl { + leds { + led_rgb_b: led-rgb-b { + rockchip,pins =3D <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdhci { + bus-width =3D <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status =3D "okay"; +}; + +&spi2 { + status =3D "okay"; + assigned-clocks =3D <&cru CLK_SPI2>; + assigned-clock-rates =3D <200000000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi2m2_cs0 &spi2m2_pins>; + num-cs =3D <1>; + + pmic@0 { + compatible =3D "rockchip,rk806"; + spi-max-frequency =3D <1000000>; + reg =3D <0x0>; + + interrupt-parent =3D <&gpio0>; + interrupts =3D <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + system-power-controller; + + vcc1-supply =3D <&vcc5v0_sys>; + vcc2-supply =3D <&vcc5v0_sys>; + vcc3-supply =3D <&vcc5v0_sys>; + vcc4-supply =3D <&vcc5v0_sys>; + vcc5-supply =3D <&vcc5v0_sys>; + vcc6-supply =3D <&vcc5v0_sys>; + vcc7-supply =3D <&vcc5v0_sys>; + vcc8-supply =3D <&vcc5v0_sys>; + vcc9-supply =3D <&vcc5v0_sys>; + vcc10-supply =3D <&vcc5v0_sys>; + vcc11-supply =3D <&vcc_2v0_pldo_s3>; + vcc12-supply =3D <&vcc5v0_sys>; + vcc13-supply =3D <&vcc_1v1_nldo_s3>; + vcc14-supply =3D <&vcc_1v1_nldo_s3>; + vcca-supply =3D <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells =3D <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_gpu_s0"; + regulator-enable-ramp-delay =3D <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <750000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <900000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <2000000>; + regulator-max-microvolt =3D <2000000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-name =3D "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; 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Wed, 03 Apr 2024 08:15:10 -0700 (PDT) Received: from yoga-710.tas.nnz-ipc.net ([178.218.200.115]) by smtp.gmail.com with ESMTPSA id d6-20020a0565123d0600b00515c1b1fb85sm2055092lfv.233.2024.04.03.08.15.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 08:15:10 -0700 (PDT) From: Dmitry Yashin To: Heiko Stuebner , linux-rockchip@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dmitry Yashin Subject: [PATCH v2 3/3] arm64: dts: rockchip: add Forlinx OK3588-C Date: Wed, 3 Apr 2024 20:12:29 +0500 Message-ID: <20240403151229.30577-4-dmt.yashin@gmail.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240403151229.30577-1-dmt.yashin@gmail.com> References: <20240403151229.30577-1-dmt.yashin@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" OK3588-C is the carrier board for FET3588-C System on Module. OK3588-C features: - 2x 1GbE Realtek RTL8211F Ethernet - 1x HDMI Type A out - 1x HDMI Type A in - 3x USB 3.1 Type C (2x OTG and 1x serial console) - 1x USB 2.0 Type A - 1x USB 3.0 & USB 2.0 Combo M.2 M Key (4G/5G modem) - 1x PCIE 2.0 M.2 E Key (1 lane) - 1x PCIE 2.0 PCIe (1 lane) - 1x PCIE 3.0 PCIe (4 lanes) - 1x TF scard slot - 5x MIPI CSI - 2x MIP DSI - 2x CAN2.0B - 1x RS485 - 1x NAU8822 onboard audio - 1x FAN connector - 1x RTC - 20-pin expansion header - ADC keys Add support for Forlinx OK3588-C board. Signed-off-by: Dmitry Yashin --- Changes in v2: - update dtsi include - set more generic names for tca6424a, nau8822 and sound nodes - reorder regulator and nodes in pinctrl - reorder properties in gmac and sdmmc - drop vmmc-supply from sdmmc and update max-frequency - enable gpu (depends on for-next branch) - enable usb_host nodes arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588-ok3588-c.dts | 409 ++++++++++++++++++ 2 files changed, 410 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 0192980ef37f..c6a7fe9522ae 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -116,6 +116,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-edgeble-neu6b-i= o.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-jaguar.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-nanopc-t6.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-ok3588-c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-orangepi-5-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-quartzpro64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-rock-5b.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts b/arch/arm64/= boot/dts/rockchip/rk3588-ok3588-c.dts new file mode 100644 index 000000000000..009566d881f3 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts @@ -0,0 +1,409 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include "rk3588-fet3588-c.dtsi" + +/ { + model =3D "Forlinx OK3588-C Board"; + compatible =3D "forlinx,ok3588-c", "forlinx,fet3588-c", "rockchip,rk3588"; + + aliases { + ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; + mmc1 =3D &sdmmc; + }; + + adc-keys-0 { + compatible =3D "adc-keys"; + io-channels =3D <&saradc 0>; + io-channel-names =3D "buttons"; + keyup-threshold-microvolt =3D <1800000>; + poll-interval =3D <100>; + + button-maskrom { + label =3D "Maskrom"; + linux,code =3D ; + press-threshold-microvolt =3D <400>; + }; + }; + + adc-keys-1 { + compatible =3D "adc-keys"; + io-channels =3D <&saradc 1>; + io-channel-names =3D "buttons"; + keyup-threshold-microvolt =3D <1800000>; + poll-interval =3D <100>; + + button-volume-up { + label =3D "V+/Recovery"; + linux,code =3D ; + press-threshold-microvolt =3D <17000>; + }; + + button-volume-down { + label =3D "V-"; + linux,code =3D ; + press-threshold-microvolt =3D <417000>; + }; + + button-menu { + label =3D "Menu"; + linux,code =3D ; + press-threshold-microvolt =3D <890000>; + }; + + button-escape { + label =3D "ESC"; + linux,code =3D ; + press-threshold-microvolt =3D <1235000>; + }; + }; + + fan: pwm-fan { + compatible =3D "pwm-fan"; + cooling-levels =3D <0 95 145 195 255>; + fan-supply =3D <&vcc12v_dcin>; + pwms =3D <&pwm2 0 50000 0>; + #cooling-cells =3D <2>; + }; + + sound { + compatible =3D "simple-audio-card"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hp_detect>; + simple-audio-card,name =3D "RK3588 OK3588-C Audio"; + simple-audio-card,bitclock-master =3D <&masterdai>; + simple-audio-card,format =3D "i2s"; + simple-audio-card,frame-master =3D <&masterdai>; + simple-audio-card,hp-det-gpio =3D <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs =3D <256>; + simple-audio-card,pin-switches =3D "Headphones", "Speaker"; + simple-audio-card,widgets =3D + "Headphones", "Headphones", + "Speaker", "Speaker", + "Microphone", "Internal Microphone", + "Microphone", "Headset Microphone"; + simple-audio-card,routing =3D + "Headphones", "LHP", + "Headphones", "RHP", + "Speaker", "LSPK", + "Speaker", "RSPK", + "LMICP", "Headset Microphone", + "RMICP", "Internal Microphone"; + + simple-audio-card,cpu { + sound-dai =3D <&i2s0_8ch>; + }; + + masterdai: simple-audio-card,codec { + sound-dai =3D <&nau8822>; + }; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + vcc1v8_sys: vcc1v8-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc1v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vcc3v3_sys>; + }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_pcie2x1l0"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + startup-delay-us =3D <50000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_pcie2x1l2"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + startup-delay-us =3D <5000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc3v3_pcie30: vcc3v3_pcie30-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_pcie30"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc12v_dcin>; + }; +}; + +&gmac0 { + clock_in_out =3D "output"; + phy-handle =3D <&rgmii_phy0>; + phy-mode =3D "rgmii-rxid"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + tx_delay =3D <0x44>; + rx_delay =3D <0x00>; + status =3D "okay"; +}; + +&gmac1 { + clock_in_out =3D "output"; + phy-handle =3D <&rgmii_phy1>; + phy-mode =3D "rgmii-rxid"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + tx_delay =3D <0x44>; + rx_delay =3D <0x00>; + status =3D "okay"; +}; + +&gpu { + mali-supply =3D <&vdd_gpu_s0>; + status =3D "okay"; +}; + +&i2c2 { + status =3D "okay"; + + tca6424a: gpio@23 { + compatible =3D "ti,tca6424"; + reg =3D <0x23>; + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-parent =3D <&gpio1>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <2>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&tca6424a_int>; + vcc-supply =3D <&vcc3v3_sys>; + }; +}; + +&i2c5 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c5m2_xfer>; + + pcf8563: rtc@51 { + compatible =3D "nxp,pcf8563"; + reg =3D <0x51>; + }; +}; + +&i2c7 { + status =3D "okay"; + + nau8822: audio-codec@1a { + compatible =3D "nuvoton,nau8822"; + reg =3D <0x1a>; + clocks =3D <&cru I2S0_8CH_MCLKOUT>; + clock-names =3D "mclk"; + assigned-clocks =3D <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates =3D <12288000>; + #sound-dai-cells =3D <0>; + }; +}; + +&i2s0_8ch { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status =3D "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@1 { + /* RTL8211F */ + compatible =3D "ethernet-phy-id001c.c916", + "ethernet-phy-ieee802.3-c22"; + reg =3D <0x1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rtl8211f_0_rst>; + reset-assert-us =3D <20000>; + reset-deassert-us =3D <100000>; + reset-gpios =3D <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@2 { + /* RTL8211F */ + compatible =3D "ethernet-phy-id001c.c916", + "ethernet-phy-ieee802.3-c22"; + reg =3D <0x2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rtl8211f_1_rst>; + reset-assert-us =3D <20000>; + reset-deassert-us =3D <100000>; + reset-gpios =3D <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie2x1l0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie2_0_rst>; + reset-gpios =3D <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pcie2x1l0>; + status =3D "okay"; +}; + +&pcie2x1l2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie2_2_rst>; + reset-gpios =3D <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pcie2x1l2>; + status =3D "okay"; +}; + +&pcie30phy { + status =3D "okay"; +}; + +&pcie3x4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie3_rst>; + reset-gpios =3D <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pcie30>; + status =3D "okay"; +}; + +&pinctrl { + pcie2 { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins =3D <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_2_rst: pcie2-2-rst { + rockchip,pins =3D <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie3 { + pcie3_rst: pcie3-rst { + rockchip,pins =3D <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtl8211f { + rtl8211f_0_rst: rtl8211f-0-rst { + rockchip,pins =3D <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + rtl8211f_1_rst: rtl8211f-1-rst { + rockchip,pins =3D <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sound { + hp_detect: hp-detect { + rockchip,pins =3D <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + tca6424a { + tca6424a_int: tca6424a-int { + rockchip,pins =3D <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + status =3D "okay"; +}; + +&saradc { + vref-supply =3D <&avcc_1v8_s0>; + status =3D "okay"; +}; + +&sdmmc { + bus-width =3D <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios =3D <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency =3D <150000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vqmmc-supply =3D <&vccio_sd_s0>; + status =3D "okay"; +}; + +&u2phy2 { + status =3D "okay"; +}; + +&u2phy2_host { + status =3D "okay"; +}; + +&u2phy3 { + status =3D "okay"; +}; + +&u2phy3_host { + status =3D "okay"; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; + +&usb_host1_ehci { + status =3D "okay"; +}; + +&usb_host1_ohci { + status =3D "okay"; +}; --=20 2.39.2