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Lin" , Houlong Wei , , , , Subject: [PATCH v5 09/10] mailbox: mediatek: Add secure CMDQ driver support for CMDQ driver Date: Wed, 3 Apr 2024 18:26:01 +0800 Message-ID: <20240403102602.32155-10-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240403102602.32155-1-shawn.sung@mediatek.com> References: <20240403102602.32155-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--2.736600-8.000000 X-TMASE-MatchedRID: 8ytEwWiOUqMlen1U/pCyekKcYi5Qw/RVCt59Uh3p/NVZps+y1VXzqUY/ auwRJnMLb1ikhugskqP8Qxx3otU4NgS+Xc7cwjX6A9lly13c/gGy4iyjvVWToslgi/vLS272sTA lYjdRdV71NEe6iuR2Lqx2oKSmYVP/ydSy/G+xHpKNCVVXBJuPJyhRWQHuJ8memIdt8XFDxCujxY yRBa/qJcFwgTvxipFajoczmuoPCq0J4NGAnmRP66kea7KunB1NH+ehIz6y+NgelHsQuY+j1Bk9R wcCrPEIrLtrh+vxIRaq0jvdyzToJRb6DSujyvwCS7Uplf7Nx8bBkGBTIlURuXoXDz8+lMxFpW+a IDJ4DaRzkxJ+SIkUjlAEm1wpw5h+lExlQIQeRG0= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--2.736600-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 996E1AF9F37D4AFBC63BD05F1E171E93FD0C4A6D0E2BE9BF168B2E905F6B74AB2000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "Jason-JH.Lin" CMDQ driver will probe a secure CMDQ driver when has_sec flag in platform data is true and its device node in dts has defined a event id of CMDQ_SYNC_TOKEN_SEC_EOF. Secure CMDQ driver support on mt8188 and mt8195 currently. So add a has_secure flag to their driver data to probe it. Signed-off-by: Jason-JH.Lin Signed-off-by: Hsiao Chien Sung --- drivers/mailbox/mtk-cmdq-mailbox.c | 69 +++++++++++++++++++++++++++++- 1 file changed, 68 insertions(+), 1 deletion(-) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-= mailbox.c index e04302ca6ec03..a51140404d116 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -15,8 +15,8 @@ #include #include #include +#include #include - #define CMDQ_MBOX_AUTOSUSPEND_DELAY_MS 100 =20 #define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT) @@ -55,11 +55,19 @@ #define CMDQ_JUMP_BY_OFFSET 0x10000000 #define CMDQ_JUMP_BY_PA 0x10000001 =20 +#define CMDQ_IS_SECURE_THREAD(idx, cmdq) (cmdq->pdata->has_secure && \ + idx >=3D cmdq->pdata->secure_thread_min && \ + idx < cmdq->pdata->secure_thread_min + \ + cmdq->pdata->secure_thread_nr) + struct gce_plat { u32 thread_nr; u8 shift; bool control_by_sw; bool sw_ddr_en; + bool has_secure; + u32 secure_thread_nr; + u32 secure_thread_min; u32 gce_num; }; =20 @@ -377,6 +385,13 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan,= void *data) if (ret < 0) return ret; =20 + if (CMDQ_IS_SECURE_THREAD(thread->idx, cmdq)) { + ret =3D cmdq_sec_mbox.ops->send_data(chan, data); + pm_runtime_mark_last_busy(cmdq->mbox.dev); + pm_runtime_put_autosuspend(cmdq->mbox.dev); + return ret; + } + task =3D kzalloc(sizeof(*task), GFP_ATOMIC); if (!task) { pm_runtime_put_autosuspend(cmdq->mbox.dev); @@ -436,6 +451,12 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan,= void *data) =20 static int cmdq_mbox_startup(struct mbox_chan *chan) { + struct cmdq *cmdq =3D dev_get_drvdata(chan->mbox->dev); + struct cmdq_thread *thread =3D (struct cmdq_thread *)chan->con_priv; + + if (CMDQ_IS_SECURE_THREAD(thread->idx, cmdq)) + cmdq_sec_mbox.ops->startup(chan); + return 0; } =20 @@ -448,6 +469,13 @@ static void cmdq_mbox_shutdown(struct mbox_chan *chan) =20 WARN_ON(pm_runtime_get_sync(cmdq->mbox.dev)); =20 + if (CMDQ_IS_SECURE_THREAD(thread->idx, cmdq)) { + cmdq_sec_mbox.ops->shutdown(chan); + pm_runtime_mark_last_busy(cmdq->mbox.dev); + pm_runtime_put_autosuspend(cmdq->mbox.dev); + return; + } + spin_lock_irqsave(&thread->chan->lock, flags); if (list_empty(&thread->task_busy_list)) goto done; @@ -494,6 +522,13 @@ static int cmdq_mbox_flush(struct mbox_chan *chan, uns= igned long timeout) if (ret < 0) return ret; =20 + if (CMDQ_IS_SECURE_THREAD(thread->idx, cmdq)) { + cmdq_sec_mbox.ops->flush(chan, timeout); + pm_runtime_mark_last_busy(cmdq->mbox.dev); + pm_runtime_put_autosuspend(cmdq->mbox.dev); + return 0; + } + spin_lock_irqsave(&thread->chan->lock, flags); if (list_empty(&thread->task_busy_list)) goto out; @@ -569,6 +604,7 @@ static int cmdq_probe(struct platform_device *pdev) int alias_id =3D 0; static const char * const clk_name =3D "gce"; static const char * const clk_names[] =3D { "gce0", "gce1" }; + u32 hwid =3D 0; =20 cmdq =3D devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL); if (!cmdq) @@ -594,6 +630,8 @@ static int cmdq_probe(struct platform_device *pdev) dev, cmdq->base, cmdq->irq); =20 if (cmdq->pdata->gce_num > 1) { + hwid =3D of_alias_get_id(dev->of_node, clk_name); + for_each_child_of_node(phandle->parent, node) { alias_id =3D of_alias_get_id(node, clk_name); if (alias_id >=3D 0 && alias_id < cmdq->pdata->gce_num) { @@ -643,6 +681,29 @@ static int cmdq_probe(struct platform_device *pdev) cmdq->mbox.chans[i].con_priv =3D (void *)&cmdq->thread[i]; } =20 + if (cmdq->pdata->has_secure) { + struct platform_device *cmdq_sec; + static struct gce_sec_plat sec_plat =3D {0}; + + if (of_property_read_u32_index(dev->of_node, "mediatek,gce-events", 0, + &sec_plat.cmdq_event) =3D=3D 0) { + sec_plat.mbox =3D &cmdq->mbox; + sec_plat.base =3D cmdq->base; + sec_plat.hwid =3D hwid; + sec_plat.secure_thread_nr =3D cmdq->pdata->secure_thread_nr; + sec_plat.secure_thread_min =3D cmdq->pdata->secure_thread_min; + + cmdq_sec =3D platform_device_register_data(dev, "mtk-cmdq-sec", + PLATFORM_DEVID_AUTO, + &sec_plat, + sizeof(sec_plat)); + if (IS_ERR(cmdq_sec)) { + dev_err(dev, "failed to register platform_device mtk-cmdq-sec\n"); + return PTR_ERR(cmdq_sec); + } + } + } + err =3D devm_mbox_controller_register(dev, &cmdq->mbox); if (err < 0) { dev_err(dev, "failed to register mailbox: %d\n", err); @@ -719,6 +780,9 @@ static const struct gce_plat gce_plat_mt8188 =3D { .thread_nr =3D 32, .shift =3D 3, .control_by_sw =3D true, + .has_secure =3D true, + .secure_thread_nr =3D 2, + .secure_thread_min =3D 8, .gce_num =3D 2 }; =20 @@ -733,6 +797,9 @@ static const struct gce_plat gce_plat_mt8195 =3D { .thread_nr =3D 24, .shift =3D 3, .control_by_sw =3D true, + .has_secure =3D true, + .secure_thread_nr =3D 2, + .secure_thread_min =3D 8, .gce_num =3D 2 }; =20 --=20 2.18.0