From nobody Mon Feb 9 08:54:35 2026 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 660956CDDF for ; Wed, 3 Apr 2024 08:05:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131516; cv=none; b=h0iQuGsoBMLBtcx7u/r9a7RaeYwhKpEgrhpPL1mxGS0TgGimtdTJZfRO8m7FFnh+I77QWhWts0atXOt7sSg4Kg45NKxttxCsKZ7/NQ9PG95fwuL1WNl4NKsDn4UVU7WmKSWKaRcH8iNzBmpg26JpwCnilRrz4laXPognr/SJ3lM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131516; c=relaxed/simple; bh=QPSBE9QZ9I3ka5tiVYaLmRJclnGfjz8CpXpruGJQvzE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=UbEPKDl9ucKoDMV5o9dpuKVAaid0RHhYw0BCbksKxEDc1pOHjiEDQrh0X3EhYgL6aT/ZtnTSWV17psy4CJw1csF3acwMwCD4yYghZYryTctw5pfqEXWUUNRxxbiVki2s9lPncDwEDtwB4PDITidJjRPSN/O2+en+XDDoBtlA4CU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=Jh5qO/+J; arc=none smtp.client-ip=209.85.214.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="Jh5qO/+J" Received: by mail-pl1-f172.google.com with SMTP id d9443c01a7336-1e034607879so48828415ad.0 for ; Wed, 03 Apr 2024 01:05:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131514; x=1712736314; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wk9dPs2pdPMy/ouYyBMSDOPD1OQUOIvovvehkpc98kM=; b=Jh5qO/+Jj8wcgB/ufwV8mJL6YrXrofnTLzFgpsa198jYW5k5XiCnnki3noQara2nHb WQF1f77pG5O1RY/JA+lZX4FwJ1w8kw/JGKEF0bakvmaZ8dml+I4Xsnp9NohJ6a+VTH2B o3kGPlqwG64nEH5r8P1OckbN3reFARfNvvdd+PJPYyCCiEfMWY6977kvtQQZVJpotM2c v8Ed4pDzJxrfwfrW1skSjD39oUIDU75+iWOAoH1Sb2eB2G6MBl+yMMALvj3XOLelGyIq 5oYhbCaGMuIp8kfy7MuENeERQRMWoWOlmJ56aRckrkECIz8ShRgnF2/oCfe/QfKPqe7n Hk9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131514; x=1712736314; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wk9dPs2pdPMy/ouYyBMSDOPD1OQUOIvovvehkpc98kM=; b=kEqKN+Wz5J/X0ztF0caZc0PKOm61K97/nl4b+eBYR3F2trW8P/rxOXjTsXWiKSw0C7 I80Ibp6sagW3BB8HMSSK+uIGXa1slOV/hRtQ2+UsTgv4SJ63Bp+GFgZ/n5PBfN2JWBUo MyVUm0YjQmPOV3c355RBO84Wd1Fipu46yiGCt3fyBC4xl6GspGiJG5fAryi0Dck/vCtF iMPM/ZA+WpMbyqtbuhJQxTknIR6Pi+CG85bJB72ikXyNpbwSbl/Tag2wVME1o5TV12T3 Ll7NgI6Erj4dNYCZ+i+I+GyyPjpNRVR4r0zLIt/lnUVN2D8uchv++lCN7iy6ZMDEthJt qy3A== X-Gm-Message-State: AOJu0YxAee41f5/H7ZGWdxvD7pa86acbTqTm5k246Nr0BPpf7Tln6x1x KCw+nCtzju1InQsXspeh+nsi3P6EbigxcupCYpN9L6fZDY6InXHJd98IkUL66UHkZJ+tFeCg+S9 u X-Google-Smtp-Source: AGHT+IGJGNXcOyb9YrykwAGNPaYyhw8xhsLdGwuGzUBrwVAzvp1h6eGWJ0tNbKMZggDJyDT4f6wwug== X-Received: by 2002:a17:903:292:b0:1e2:6240:72e7 with SMTP id j18-20020a170903029200b001e2624072e7mr5865569plr.53.1712131513754; Wed, 03 Apr 2024 01:05:13 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:13 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Conor Dooley , Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 01/22] RISC-V: Fix the typo in Scountovf CSR name Date: Wed, 3 Apr 2024 01:04:30 -0700 Message-Id: <20240403080452.1007601-2-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The counter overflow CSR name is "scountovf" not "sscountovf". Fix the csr name. Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") Reviewed-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Conor Dooley Reviewed-by: Anup Patel Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- arch/riscv/include/asm/csr.h | 2 +- drivers/perf/riscv_pmu_sbi.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 2468c55933cd..9d1b07932794 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -281,7 +281,7 @@ #define CSR_HPMCOUNTER30H 0xc9e #define CSR_HPMCOUNTER31H 0xc9f =20 -#define CSR_SSCOUNTOVF 0xda0 +#define CSR_SCOUNTOVF 0xda0 =20 #define CSR_SSTATUS 0x100 #define CSR_SIE 0x104 diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 8cbe6e5f9c39..3e44d2fb8bf8 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -27,7 +27,7 @@ =20 #define ALT_SBI_PMU_OVERFLOW(__ovl) \ asm volatile(ALTERNATIVE_2( \ - "csrr %0, " __stringify(CSR_SSCOUNTOVF), \ + "csrr %0, " __stringify(CSR_SCOUNTOVF), \ "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \ THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \ CONFIG_ERRATA_THEAD_PMU, \ --=20 2.34.1 From nobody Mon Feb 9 08:54:35 2026 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 925876E613 for ; Wed, 3 Apr 2024 08:05:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131518; cv=none; b=Y99b1DY4tnpqE46u28g3TJVj8MkydVoubJooRG4rL0TXVtRC5QWie1UeJ0FrvLIpWS0dihB6gtLtAW+FHrb40bqmGneSUY4hSD8Xqk0X9zZJvJYIZdKKVC7lOAcSb9a9IeOidOjJRvTqXiIaLmq5LVMsTUU6zOrdpAq0eWwkKgs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131518; c=relaxed/simple; bh=lSkNV6iOiiqqPiO/F6auQ8ekda3aYuop52golLpc0/E=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=nzFW30pDdgyFFpo3TAFy23Rkg9W0DehzFm3qSzzsMpliqTCZNomcVzP7pz70OOxdS+E79qtmUclC32hUHIRvs0cL+jgI2PzDtTBvPkPewVLk47sKs8lvCcOqM7YjRFGrqz24x5S826sFBdZf7CEVKMdHwPKSxXTpQw5LTt2x5EU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=oxhkt9fd; arc=none smtp.client-ip=209.85.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="oxhkt9fd" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-1e0f3052145so57204695ad.2 for ; Wed, 03 Apr 2024 01:05:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131516; x=1712736316; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Bc4Qbmx0AoxDu4ditj7xvL7MfGG2VDboL8zvDiTC/bw=; b=oxhkt9fdvmejQVTV8QHTUzo7DRIpKcnjzFU+NnGgKNIBu8ieSzb6S2HReVX67i+wWr YJUxb7Kkcvtv8Iy4HW0WTlt12PpIz5iRapjoRPv5t1KlSdu1sq1HZlHq6qYJOBy/RCvQ M8bwsCMM8UQRRYkfnjvdgjdiEaRnyt4A3YzSPmRNyyPT3syoIVRfbmJjzpxMDE3Yumdc i7T+Lrc//ohXWlC+hPX3q8Ik8FP7yNcE4qSxe5Dun/c7VLW4UaqHCjeRl3fFN/XIMttu mephSuuXM/lQC488lnVyAsklT2yMsl8AnAfQ2rB95SUm58PClgrG2Am8LqKmGGvPeTqZ dG5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131516; x=1712736316; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Bc4Qbmx0AoxDu4ditj7xvL7MfGG2VDboL8zvDiTC/bw=; b=GxaKHfvaXPR8rWN3AaDsQiNUNlLkwRMYtWqqLE9/2uMob8F46dGDZKpB9trOFqd/YW OfypCS1Jg/kPdIvd49rArT50pQYskaAPuiw4Y7Fn5fDU66T8AooLo+wbcZwoxVZ9zk+s BKsYfT/LGfn0oGFOql1fO8VIm+oqn+Zk97WD04RnFQ52xvBjwTAmOBN8Y93nRIeZZBz/ TmggMr0e3m6/5mansl81+jkM0isjq7ttBSsuvunV68p6SA9ehecA33st3J8ScBKEBffb vRDJ0a/lGrBE30vl8nVMU29yBMT7A4xnz7kIFJLcUxDM2t6qyxqrkGWO7gQeNEf4GmPq V5Vg== X-Gm-Message-State: AOJu0YzL2d9+MgYF7TD9KAdBE64QhWSd0i7E4TLournC0qDdl0rBMuu3 ccClta8rgyQZo/DKH/Bc4NsMHuF99V0rIistd0pyQWoHnRDxGdpbiTXgmp0Yy+s2N4HTdNtx6Rg 7 X-Google-Smtp-Source: AGHT+IEN9FTCaj0hRotpYu2L3MLNBsnLZyWzCk4MgIL/9u1tPeTTuGgG3qQXqUKuRiVdVxo5cBEIJA== X-Received: by 2002:a17:902:b089:b0:1dd:878d:9dca with SMTP id p9-20020a170902b08900b001dd878d9dcamr1981385plr.48.1712131516075; Wed, 03 Apr 2024 01:05:16 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:15 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Conor Dooley , Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 02/22] RISC-V: Add FIRMWARE_READ_HI definition Date: Wed, 3 Apr 2024 01:04:31 -0700 Message-Id: <20240403080452.1007601-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable SBI v2.0 added another function to SBI PMU extension to read the upper bits of a counter with width larger than XLEN. Add the definition for that function. Reviewed-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Conor Dooley Reviewed-by: Anup Patel Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- arch/riscv/include/asm/sbi.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 6e68f8dff76b..ef8311dafb91 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -131,6 +131,7 @@ enum sbi_ext_pmu_fid { SBI_EXT_PMU_COUNTER_START, SBI_EXT_PMU_COUNTER_STOP, SBI_EXT_PMU_COUNTER_FW_READ, + SBI_EXT_PMU_COUNTER_FW_READ_HI, }; =20 union sbi_pmu_ctr_info { --=20 2.34.1 From nobody Mon Feb 9 08:54:35 2026 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA2FB6FE0D for ; Wed, 3 Apr 2024 08:05:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131521; cv=none; b=jz8eGu06H1mvTozfwFYE7P+Q3ZT1f8tw6iWc8ey3MtVbkFGwWUSvIoiG+bVgw4s2f4JwNh0mqYLMRDSNrrYfT3MnB9ZeI3y+Qr1chSly0uo9BdFTU2zeyDAwsgRvL+1TfAS17VOKLKpYYac98Yi1srcJ5bzMMgsd0WKUn37+TTw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131521; c=relaxed/simple; bh=5SixT0kcz+8IGtYwvZGhA9Q1KZ5SaAWo/BakwlxdqZM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=KVgbMmYVQc9KCHyIRxsb72RNgHloQHXnfPTlMpQtVGFQs3P8BPkNtESg5I6hPhy9I1GkviIyQ9ATXIV4pXF7jYQwcB1/YoGFeYmxUYSGXNz9BkKE+UGK8ptvnwhlNXC5TRTJghrQieQu4SaftP2rl5r2qcqVi9hxJlyIZNWLyZc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=uK75Skh/; arc=none smtp.client-ip=209.85.214.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="uK75Skh/" Received: by mail-pl1-f172.google.com with SMTP id d9443c01a7336-1e0b889901bso49280525ad.1 for ; Wed, 03 Apr 2024 01:05:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131518; x=1712736318; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2ukUdwvkRaeQmBPwRJpu6uMxNPU93zNWp+RJiBVsFw4=; b=uK75Skh/kr8v4RnArctSD7ENSLfakR6lkmYZzFmP10Hlu2kXP5spk6IQXSbS309AaS 9nbmQ4aRhTKH0iRWuaqGf6zCfxadSs2xbbF1T8ORRzclYNTfaQOwuOGETxdNIWfmEm8U p+CqL2TIKw4I3+/L6Q5T3lQl4JiL3qaYPBcj/PlhwrhVE8iEJOY/iM27X3hlAS+ZN2tv Gpml8cz1wynHkSUN1G2U14IRmkD/g3YTv5c2wNNneC94/mcK5Lmt1jBQ9OHoeFn+zgRu oGQennlWMs0RxBAo6lHuE8p69IWXe5O9cqfHqvgriT9PzQqbyvumCyJWNX9P8TMdmxzP 8SBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131518; x=1712736318; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2ukUdwvkRaeQmBPwRJpu6uMxNPU93zNWp+RJiBVsFw4=; b=bbAbvWazcB3atJclHhytYU2GNsBN9v5mqzESri7XCewWKKWfBVp64G/Q3Fy8y7w7PQ 0FZm8wyHCkxMvnz298FkD76Vd//2nyUYQK+6mMvIh00OMYAwXemfVkQn+zfM+rc11Tcu OYOiNX0rjc39J4wdyohplbjyhebrz/DfHa55JVXQKWifrYJiy0pB/pdYAWpv/WaNb4ZA 9URZfOQf3blHE4ek7gmNJQx+WxiiqnO0kTgIMHQv75SNYlSid4ULpcX7r/1fN3YeSnuY Hz9zJWpCcN+/vkLFuIBx/HWP1YnCVmt6sXcXVb/1HMv/80W+bgDMkPyXclPC9CWv4E0X N3rg== X-Gm-Message-State: AOJu0YzxBdTQWuy6gJZKeyhf4cCh3fHVtKO9vOwOu0628id1j7htb8i1 Irx2rEHoXWmjEJB4VooMdH/D3tfl6tUxfwe3rJuPI34ltuOmLqyZCHuDpbEzFzS8S2e5ROQnaKx H X-Google-Smtp-Source: AGHT+IGzCaqR/FZVf4jG8/W5aRGI+FZChKgtdmsu22b2KjgU9hzL33Vhb0robWHwzAUPtLmResHVWQ== X-Received: by 2002:a17:902:e741:b0:1dc:a605:5435 with SMTP id p1-20020a170902e74100b001dca6055435mr16071106plf.31.1712131518213; Wed, 03 Apr 2024 01:05:18 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:17 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Andrew Jones , Palmer Dabbelt , Conor Dooley , Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 03/22] drivers/perf: riscv: Read upper bits of a firmware counter Date: Wed, 3 Apr 2024 01:04:32 -0700 Message-Id: <20240403080452.1007601-4-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SBI v2.0 introduced a explicit function to read the upper 32 bits for any firmware counter width that is longer than 32bits. This is only applicable for RV32 where firmware counter can be 64 bit. Reviewed-by: Andrew Jones Acked-by: Palmer Dabbelt Reviewed-by: Conor Dooley Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 3e44d2fb8bf8..babf1b9a4dbe 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -57,6 +57,8 @@ asm volatile(ALTERNATIVE( \ PMU_FORMAT_ATTR(event, "config:0-47"); PMU_FORMAT_ATTR(firmware, "config:63"); =20 +static bool sbi_v2_available; + static struct attribute *riscv_arch_formats_attr[] =3D { &format_attr_event.attr, &format_attr_firmware.attr, @@ -511,19 +513,29 @@ static u64 pmu_sbi_ctr_read(struct perf_event *event) struct hw_perf_event *hwc =3D &event->hw; int idx =3D hwc->idx; struct sbiret ret; - union sbi_pmu_ctr_info info; u64 val =3D 0; + union sbi_pmu_ctr_info info =3D pmu_ctr_list[idx]; =20 if (pmu_sbi_is_fw_event(event)) { ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ, hwc->idx, 0, 0, 0, 0, 0); - if (!ret.error) - val =3D ret.value; + if (ret.error) + return 0; + + val =3D ret.value; + if (IS_ENABLED(CONFIG_32BIT) && sbi_v2_available && info.width >=3D 32) { + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ_HI, + hwc->idx, 0, 0, 0, 0, 0); + if (!ret.error) + val |=3D ((u64)ret.value << 32); + else + WARN_ONCE(1, "Unable to read upper 32 bits of firmware counter error: = %d\n", + sbi_err_map_linux_errno(ret.error)); + } } else { - info =3D pmu_ctr_list[idx]; val =3D riscv_pmu_ctr_read_csr(info.csr); if (IS_ENABLED(CONFIG_32BIT)) - val =3D ((u64)riscv_pmu_ctr_read_csr(info.csr + 0x80)) << 31 | val; + val |=3D ((u64)riscv_pmu_ctr_read_csr(info.csr + 0x80)) << 32; } =20 return val; @@ -1135,6 +1147,9 @@ static int __init pmu_sbi_devinit(void) return 0; } =20 + if (sbi_spec_version >=3D sbi_mk_version(2, 0)) + sbi_v2_available =3D true; + ret =3D cpuhp_setup_state_multi(CPUHP_AP_PERF_RISCV_STARTING, "perf/riscv/pmu:starting", pmu_sbi_starting_cpu, pmu_sbi_dying_cpu); --=20 2.34.1 From nobody Mon Feb 9 08:54:35 2026 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 003FD71B3B for ; Wed, 3 Apr 2024 08:05:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131523; cv=none; b=TBJ8ciYCy2wYIxHHfPJEqEAnJZwM3xkA/Xg6xH7ctusCNJTlpNUnoeNA/GtcNdRv9pYWtgNwzbiJwkECXSJny0xi/RGCL9Khzh6A7sTHQwo0X3EXKQH1WgedR2EvgggoxzWEU9Z6+N+tuEBMu0MDDsbc3hX8/8xH2Yv7FG/yPR8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131523; c=relaxed/simple; bh=IeCUKxpOMKG0zL7LcLS/wH2lWaOxpIfM9zaAAyQj4Uk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=bPmVSorNmFHxXeo9XP67lA3rRBXcQuWajYzHK5nzSyP/L629mtTcl08IXFcsALTTWHZIySKXniSu9Emjy+qjhZ9Ru33x++nuU0IvE/g8e8AlL4su9cH3oXy255Efuu5Hon3dh3ideZFSLPCNiWNav4waP/4kN7u1QsCQxoRC2FA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=OdCJtUm/; arc=none smtp.client-ip=209.85.214.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="OdCJtUm/" Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-1e0d82c529fso51751645ad.2 for ; Wed, 03 Apr 2024 01:05:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131520; x=1712736320; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ixjc/2duOe8tMNsDFapztE6WZpMRR0IqMx2Riyo3ljE=; b=OdCJtUm/TnCsKRq0tOayzDsxkmSlAE4FjEpJQ8e4FvpENOjnl6jwWVCrlwrgStP4zL AKlz3P/CLAem4ptLrNY6j0UaCbQqAbfvKQ6u8qMnfN50cRknOPKxAa6FyBCn5zVQYG1W EcMpRnWm2kHkgkpEAHc5xIwmNgVAINAVvJ0g2zxWgw1sfPBOis1sYIQJNdIGQUSadp/F 2WkDKPYY6YDOwvrioJDD36yGUs0aoegshj5HvZie4Uy3uXFovDk7heQZa4hOJfsWGW20 e/cWfP2ScDyVwCxu7mAjRNoKhvFrQbfRApoN1NXz/sViPapNAeAhJCBIY9CxfCFtkLtC cFFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131520; x=1712736320; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ixjc/2duOe8tMNsDFapztE6WZpMRR0IqMx2Riyo3ljE=; b=FtLInM9gigQddtkwTS2Y6LyZWiiS1gYRTb8XHHl+2713Qh0ZWFM/0lJ1mqoCfl5iXi 1dl/VkXUg6yu0Uqvhclhq/K0Zzfz7lNVwq14cDm4YNqp03AlsZG/yyld4AbQTYD6wotV yhl14wVfOHp2OSDFtyP+9vWuPyf5WX1imeHq5r5zDtG7fgAOwq0TwmfkhtOw5rrJu0/S OTdP8/zuY1jXaIyxmHcfO8QaLMYtuJcQXpim6B5J6EqcoXSW1JhwXifl7ufRGh8sIdMf dkTtt/fvOmhYdk3Eb64NMsuan0LwdJ/f5i9EOmxjBaiSb7+QmwsvGjOKtUQOXmnsBuHO dLdQ== X-Gm-Message-State: AOJu0Yybb12ppFPhkWFCpIwJcUoZCNrMtmWKeKDKD3csgPd/0OxbObVz YE6AURTkPoLQ4jxK9gBHnV7DYgY8rFau7hS1iiLUeN/RW1GvrwOcbNTRRdHK7MfW5jMKrLOsu/b A X-Google-Smtp-Source: AGHT+IFNP2TORKh7//FzhNMEZN9MBNitQSqhLOnah919WVqeHY+e2MYv0jsRIRUc8mtVSGHiLEDhcg== X-Received: by 2002:a17:902:b701:b0:1e0:a1c7:56fd with SMTP id d1-20020a170902b70100b001e0a1c756fdmr13300312pls.61.1712131520248; Wed, 03 Apr 2024 01:05:20 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:19 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Anup Patel , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 04/22] drivers/perf: riscv: Use BIT macro for shifting operations Date: Wed, 3 Apr 2024 01:04:33 -0700 Message-Id: <20240403080452.1007601-5-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It is a good practice to use BIT() instead of (1UL << x). Replace the current usages with BIT(). Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- arch/riscv/include/asm/sbi.h | 20 ++++++++++---------- drivers/perf/riscv_pmu_sbi.c | 2 +- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index ef8311dafb91..4afa2cd01bae 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -233,20 +233,20 @@ enum sbi_pmu_ctr_type { #define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF =20 /* Flags defined for config matching function */ -#define SBI_PMU_CFG_FLAG_SKIP_MATCH (1 << 0) -#define SBI_PMU_CFG_FLAG_CLEAR_VALUE (1 << 1) -#define SBI_PMU_CFG_FLAG_AUTO_START (1 << 2) -#define SBI_PMU_CFG_FLAG_SET_VUINH (1 << 3) -#define SBI_PMU_CFG_FLAG_SET_VSINH (1 << 4) -#define SBI_PMU_CFG_FLAG_SET_UINH (1 << 5) -#define SBI_PMU_CFG_FLAG_SET_SINH (1 << 6) -#define SBI_PMU_CFG_FLAG_SET_MINH (1 << 7) +#define SBI_PMU_CFG_FLAG_SKIP_MATCH BIT(0) +#define SBI_PMU_CFG_FLAG_CLEAR_VALUE BIT(1) +#define SBI_PMU_CFG_FLAG_AUTO_START BIT(2) +#define SBI_PMU_CFG_FLAG_SET_VUINH BIT(3) +#define SBI_PMU_CFG_FLAG_SET_VSINH BIT(4) +#define SBI_PMU_CFG_FLAG_SET_UINH BIT(5) +#define SBI_PMU_CFG_FLAG_SET_SINH BIT(6) +#define SBI_PMU_CFG_FLAG_SET_MINH BIT(7) =20 /* Flags defined for counter start function */ -#define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0) +#define SBI_PMU_START_FLAG_SET_INIT_VALUE BIT(0) =20 /* Flags defined for counter stop function */ -#define SBI_PMU_STOP_FLAG_RESET (1 << 0) +#define SBI_PMU_STOP_FLAG_RESET BIT(0) =20 enum sbi_ext_dbcn_fid { SBI_EXT_DBCN_CONSOLE_WRITE =3D 0, diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index babf1b9a4dbe..a83ae82301e3 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -386,7 +386,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event) cmask =3D 1; } else if (event->attr.config =3D=3D PERF_COUNT_HW_INSTRUCTIONS) { cflags |=3D SBI_PMU_CFG_FLAG_SKIP_MATCH; - cmask =3D 1UL << (CSR_INSTRET - CSR_CYCLE); + cmask =3D BIT(CSR_INSTRET - CSR_CYCLE); } } =20 --=20 2.34.1 From nobody Mon Feb 9 08:54:35 2026 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A75346CDC2 for ; Wed, 3 Apr 2024 08:05:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131527; cv=none; b=JDLz3/Ao9HHggAFnH77OarjQDy3SVrGdodkKMb4BMiTT6Jg2iof1fu9aIPzYfh3iMhA6dhrcz8uvCHTpkdB1Z++BxDsHmgTz4Sj/DqnvVFrEM32necry6Uax5z/dI5uyA+ptqWn4k++InCsLZc+yToAPWAwPVzUfaASjTcHcd1U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131527; c=relaxed/simple; bh=hD4T8CbQGFqb30M4m5Qq8QzxJC1eOzrHV+Z0kwBj2NI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XnAE1lyi00QJb1Ja548cedWHrdk1UrKiemIy9jHa1HywrrYlhx4uJ0O6R53lWo5WUx8zwm7Sxfwdj7vccoLIEOlzxO2LA1CBvg2oavVDBlc2E6xG+RRZfwdypR0+J2F0wQLgrrJDsnsX9OOlb2486FUrzYuAu91UuNGZvE9+vDU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=APZqJJ8W; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="APZqJJ8W" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-1e2987e9d67so1069885ad.1 for ; Wed, 03 Apr 2024 01:05:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131524; x=1712736324; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2cY+c1Et8e4Cu0t4snI2MWrn2141KaT0UNrXkfFbuJA=; b=APZqJJ8WSPdO9PXMkbYaajjlgHZk/+LXQVLPNEm7KKgpstdaAxBsJKFvSjRkKyalxj GhI6XbI1lR2S/RAoiqbaITQOrNGnqQuC5ctwCaPrBX9x+3tE535d2qZkghN1qNAUhopi +o07EKoPDnvJeorLpjmDCLJ6H2vdcMe1uF484REY+UtuPnxiHkMkQjKjErWMbfL1KzU3 +24QXhFSpTdSJwSZUm8jd8nkQbrhDXOJ6UibLUnsTI60blqSeH8prptkviOh10sYvhFa lYiJNgfBMUV5QZqMSUf1TZsT/sSwa1+GWWo9JaVcg1qJO62fOd4bnlfpVvuxPfcP7Ckh INUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131524; x=1712736324; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2cY+c1Et8e4Cu0t4snI2MWrn2141KaT0UNrXkfFbuJA=; b=nN1fjAO0K2G6ZVKssv3IdwQZ19uT1gFFAVQOQQD7D2L+T17oVdfOqQE5fKCL9YfDsx oaC+IpyXqc9RFRI6zbfMGWpsKHveXOH8pwXvLjjnyAHmFgOiFT14mzsX1jCYwan6QgvI oa0BT6QAceUEhfb2LNCclNrdUjWPAd050CHyNDsBvsJZN9IhCHxGUCjIBlLAdgC1TFnb MdetnjVOnABOSAXWLxDe8m7ZIkUqAwhzeFZgZBRbgBR8ztKgqDkHP26ERyke1eGZRh/e LR5WntyoBmEUjloUJKn8OvOGiiO4iQQq+tdIuOhb8s329z8e5Aayj2bWyfXge6OIpVzV rfAg== X-Gm-Message-State: AOJu0YyoPNQkxtjD/UpAdd4JBsx/7jqX/RvR4EdeRI1rupOQX59v4woO K4nuKQ6XJM+OUHZ9VfZHgK6yZZPzuev4odPNOzrX7fQbhrkZOMnP64Z4Nr5p8zbjkllksHrkSNS K X-Google-Smtp-Source: AGHT+IFKoJgtWxPYCEvG4otnYA6GehE6Ju467AMTWra/Y4iLfyYQ+vCfm0Zt2yPKMvFR+PhSvC1EhQ== X-Received: by 2002:a17:902:c412:b0:1de:fdf2:b483 with SMTP id k18-20020a170902c41200b001defdf2b483mr2836035plk.8.1712131524245; Wed, 03 Apr 2024 01:05:24 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:22 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Palmer Dabbelt , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 05/22] RISC-V: Add SBI PMU snapshot definitions Date: Wed, 3 Apr 2024 01:04:34 -0700 Message-Id: <20240403080452.1007601-6-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SBI PMU Snapshot function optimizes the number of traps to higher privilege mode by leveraging a shared memory between the S/VS-mode and the M/HS mode. Add the definitions for that extension and new error codes. Reviewed-by: Anup Patel Acked-by: Palmer Dabbelt Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- arch/riscv/include/asm/sbi.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 4afa2cd01bae..9aada4b9f7b5 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -132,6 +132,7 @@ enum sbi_ext_pmu_fid { SBI_EXT_PMU_COUNTER_STOP, SBI_EXT_PMU_COUNTER_FW_READ, SBI_EXT_PMU_COUNTER_FW_READ_HI, + SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, }; =20 union sbi_pmu_ctr_info { @@ -148,6 +149,13 @@ union sbi_pmu_ctr_info { }; }; =20 +/* Data structure to contain the pmu snapshot data */ +struct riscv_pmu_snapshot_data { + u64 ctr_overflow_mask; + u64 ctr_values[64]; + u64 reserved[447]; +}; + #define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0) #define RISCV_PMU_RAW_EVENT_IDX 0x20000 =20 @@ -244,9 +252,11 @@ enum sbi_pmu_ctr_type { =20 /* Flags defined for counter start function */ #define SBI_PMU_START_FLAG_SET_INIT_VALUE BIT(0) +#define SBI_PMU_START_FLAG_INIT_SNAPSHOT BIT(1) =20 /* Flags defined for counter stop function */ #define SBI_PMU_STOP_FLAG_RESET BIT(0) +#define SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT BIT(1) =20 enum sbi_ext_dbcn_fid { SBI_EXT_DBCN_CONSOLE_WRITE =3D 0, @@ -285,6 +295,7 @@ struct sbi_sta_struct { #define SBI_ERR_ALREADY_AVAILABLE -6 #define SBI_ERR_ALREADY_STARTED -7 #define SBI_ERR_ALREADY_STOPPED -8 +#define SBI_ERR_NO_SHMEM -9 =20 extern unsigned long sbi_spec_version; struct sbiret { --=20 2.34.1 From nobody Mon Feb 9 08:54:35 2026 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CD9F7442A for ; Wed, 3 Apr 2024 08:05:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131529; cv=none; b=WzUVybsqt1jrlrf13XfliQnkEEaysqaHi+3abVIM11gtnqQAlf0OdPArSiOKIcRCRoUR05gjgJa6oMHlgccuCtakMrXBjebbSRIKj9r0DBICMO3LeS3azZEkpKAYLqmV+8UGhHYFJI9RbosuiLI30S39Qv2GWh2ykttbIepkkn4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131529; c=relaxed/simple; bh=tlKQ5eJopDdqvp5ZG4gqUxdkZ/ZHIpbzQCA659cFf7M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Hgr5sdg74g9/+GO2JJ6ghRAtrPxrDMRQL/n89x98kYai1nqgd5PevDcb3aRmP0jDITYc7CCBFMoossOJYcV6xu3oSjxNTr449aXP7VHTAhk9pa8T8ixMF5dUx5zuwJyHnMS8nTtZ05Hp/pIIfarKQJFPNk7UWPWr0r1WJrgkibE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=pgHSB0l4; arc=none smtp.client-ip=209.85.214.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="pgHSB0l4" Received: by mail-pl1-f175.google.com with SMTP id d9443c01a7336-1e0d82c529fso51752335ad.2 for ; Wed, 03 Apr 2024 01:05:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131526; x=1712736326; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fy/HVfkL9/BXnOczniC04Qwl03af3PzLwP7P+h0XO80=; b=pgHSB0l40WtIL9pHBNLPaIbKE0nvcc/33EsTQXUbvgI63SV233YRifF+L62Ov//UgR lfyZRN5cBVxU2B3JXApJ6eJKb+gP7q8rSuSHWKZgEu/HStWrQT84rco+ZmiYnUWVucYs 62YtMu9TI3G16OUG30MqbhT01oTozJy20fBbFTkmJ7KJilzp/vj0qh3L7g6vL5m6Pnqq i0EXrwzReobCqycw19Q8EuRiDfFjNp68alKbORQAkeRyPlou0sUKvig+54p8losbKPug XruC0EKZVDRBTuTBTk64WGo0bTF/DIpRNoteMVi63y+kmZYvQKY4RqFO8TOfLClzDDUJ IjfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131526; x=1712736326; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fy/HVfkL9/BXnOczniC04Qwl03af3PzLwP7P+h0XO80=; b=XYjE5Z++b5xJvVqafjCoIr7ShxsJ/rBW7yamaTbhpYH9Z4pVWLFIwgbKvMKaukU4Vk K9tD5Rbx2aVCJG0astnlGwiLH0BDWjn9r1OC/L58WfvmvemH1V9ZZ78sEOCmCRgoKwTS KI4dmrocJGKFBc4cYUxgPge1Z9BaL90IJ2fw6/96DZjy1yMIbSh9BrCBUeVMQxZvzPn0 XyroDkB9TwOC8eMS1mQiVWikg9CrOYKlN/PPdfgBUdU3S+Whsoey4N2C3nnaOYBVNDQR xRpGf2i3wE8GjfUJ0840tis6y1Fi0NheSVr91iRT1BiRidYeFu1f3xcVoQdMWV6qFGTb TF2w== X-Gm-Message-State: AOJu0YxeGJ0BLOSa7KCY3AqqbO61GDRoQ03BRMcmYjzkPSV4gny9Frl6 kZDhpIIjZ8EUFMhMhvHIrSxR+f7gRiEGecOJrltBtjeKRTGn1uGEIXVwBzA4F8QFPh7FwytUM+M + X-Google-Smtp-Source: AGHT+IHx7Qx+ILTKaOpBzWSewlWwQIWzzEUfidMKA5sGbjy/wjDwFOC4pIF0Hh3Hy6z59AOf6brM7A== X-Received: by 2002:a17:902:c94e:b0:1e2:9945:dff with SMTP id i14-20020a170902c94e00b001e299450dffmr364388pla.2.1712131525791; Wed, 03 Apr 2024 01:05:25 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:25 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Palmer Dabbelt , Anup Patel , Conor Dooley , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 06/22] drivers/perf: riscv: Implement SBI PMU snapshot function Date: Wed, 3 Apr 2024 01:04:35 -0700 Message-Id: <20240403080452.1007601-7-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SBI v2.0 SBI introduced PMU snapshot feature which adds the following features. 1. Read counter values directly from the shared memory instead of csr read. 2. Start multiple counters with initial values with one SBI call. These functionalities optimizes the number of traps to the higher privilege mode. If the kernel is in VS mode while the hypervisor deploy trap & emulate method, this would minimize all the hpmcounter CSR read traps. If the kernel is running in S-mode, the benefits reduced to CSR latency vs DRAM/cache latency as there is no trap involved while accessing the hpmcounter CSRs. In both modes, it does saves the number of ecalls while starting multiple counter together with an initial values. This is a likely scenario if multiple counters overflow at the same time. Acked-by: Palmer Dabbelt Reviewed-by: Anup Patel Reviewed-by: Conor Dooley Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu.c | 1 + drivers/perf/riscv_pmu_sbi.c | 216 +++++++++++++++++++++++++++++++-- include/linux/perf/riscv_pmu.h | 6 + 3 files changed, 211 insertions(+), 12 deletions(-) diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c index c78a6fd6c57f..3a941b2c3888 100644 --- a/drivers/perf/riscv_pmu.c +++ b/drivers/perf/riscv_pmu.c @@ -404,6 +404,7 @@ struct riscv_pmu *riscv_pmu_alloc(void) cpuc->n_events =3D 0; for (i =3D 0; i < RISCV_MAX_COUNTERS; i++) cpuc->events[i] =3D NULL; + cpuc->snapshot_addr =3D NULL; } pmu->pmu =3D (struct pmu) { .event_init =3D riscv_pmu_event_init, diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index a83ae82301e3..8c3475d55433 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -58,6 +58,9 @@ PMU_FORMAT_ATTR(event, "config:0-47"); PMU_FORMAT_ATTR(firmware, "config:63"); =20 static bool sbi_v2_available; +static DEFINE_STATIC_KEY_FALSE(sbi_pmu_snapshot_available); +#define sbi_pmu_snapshot_available() \ + static_branch_unlikely(&sbi_pmu_snapshot_available) =20 static struct attribute *riscv_arch_formats_attr[] =3D { &format_attr_event.attr, @@ -508,14 +511,108 @@ static int pmu_sbi_event_map(struct perf_event *even= t, u64 *econfig) return ret; } =20 +static void pmu_sbi_snapshot_free(struct riscv_pmu *pmu) +{ + int cpu; + + for_each_possible_cpu(cpu) { + struct cpu_hw_events *cpu_hw_evt =3D per_cpu_ptr(pmu->hw_events, cpu); + + if (!cpu_hw_evt->snapshot_addr) + continue; + + free_page((unsigned long)cpu_hw_evt->snapshot_addr); + cpu_hw_evt->snapshot_addr =3D NULL; + cpu_hw_evt->snapshot_addr_phys =3D 0; + } +} + +static int pmu_sbi_snapshot_alloc(struct riscv_pmu *pmu) +{ + int cpu; + struct page *snapshot_page; + + for_each_possible_cpu(cpu) { + struct cpu_hw_events *cpu_hw_evt =3D per_cpu_ptr(pmu->hw_events, cpu); + + if (cpu_hw_evt->snapshot_addr) + continue; + + snapshot_page =3D alloc_page(GFP_ATOMIC | __GFP_ZERO); + if (!snapshot_page) { + pmu_sbi_snapshot_free(pmu); + return -ENOMEM; + } + cpu_hw_evt->snapshot_addr =3D page_to_virt(snapshot_page); + cpu_hw_evt->snapshot_addr_phys =3D page_to_phys(snapshot_page); + } + + return 0; +} + +static int pmu_sbi_snapshot_disable(void) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, -1, + -1, 0, 0, 0, 0); + if (ret.error) { + pr_warn("failed to disable snapshot shared memory\n"); + return sbi_err_map_linux_errno(ret.error); + } + + return 0; +} + +static int pmu_sbi_snapshot_setup(struct riscv_pmu *pmu, int cpu) +{ + struct cpu_hw_events *cpu_hw_evt; + struct sbiret ret =3D {0}; + + cpu_hw_evt =3D per_cpu_ptr(pmu->hw_events, cpu); + if (!cpu_hw_evt->snapshot_addr_phys) + return -EINVAL; + + if (cpu_hw_evt->snapshot_set_done) + return 0; + + if (IS_ENABLED(CONFIG_32BIT)) + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, + cpu_hw_evt->snapshot_addr_phys, + (u64)(cpu_hw_evt->snapshot_addr_phys) >> 32, 0, 0, 0, 0); + else + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, + cpu_hw_evt->snapshot_addr_phys, 0, 0, 0, 0, 0); + + /* Free up the snapshot area memory and fall back to SBI PMU calls withou= t snapshot */ + if (ret.error) { + if (ret.error !=3D SBI_ERR_NOT_SUPPORTED) + pr_warn("pmu snapshot setup failed with error %ld\n", ret.error); + return sbi_err_map_linux_errno(ret.error); + } + + cpu_hw_evt->snapshot_set_done =3D true; + + return 0; +} + static u64 pmu_sbi_ctr_read(struct perf_event *event) { struct hw_perf_event *hwc =3D &event->hw; int idx =3D hwc->idx; struct sbiret ret; u64 val =3D 0; + struct riscv_pmu *pmu =3D to_riscv_pmu(event->pmu); + struct cpu_hw_events *cpu_hw_evt =3D this_cpu_ptr(pmu->hw_events); + struct riscv_pmu_snapshot_data *sdata =3D cpu_hw_evt->snapshot_addr; union sbi_pmu_ctr_info info =3D pmu_ctr_list[idx]; =20 + /* Read the value from the shared memory directly */ + if (sbi_pmu_snapshot_available()) { + val =3D sdata->ctr_values[idx]; + return val; + } + if (pmu_sbi_is_fw_event(event)) { ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ, hwc->idx, 0, 0, 0, 0, 0); @@ -565,6 +662,7 @@ static void pmu_sbi_ctr_start(struct perf_event *event,= u64 ival) struct hw_perf_event *hwc =3D &event->hw; unsigned long flag =3D SBI_PMU_START_FLAG_SET_INIT_VALUE; =20 + /* There is no benefit setting SNAPSHOT FLAG for a single counter */ #if defined(CONFIG_32BIT) ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx, 1, flag, ival, ival >> 32, 0); @@ -585,16 +683,36 @@ static void pmu_sbi_ctr_stop(struct perf_event *event= , unsigned long flag) { struct sbiret ret; struct hw_perf_event *hwc =3D &event->hw; + struct riscv_pmu *pmu =3D to_riscv_pmu(event->pmu); + struct cpu_hw_events *cpu_hw_evt =3D this_cpu_ptr(pmu->hw_events); + struct riscv_pmu_snapshot_data *sdata =3D cpu_hw_evt->snapshot_addr; =20 if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) && (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT)) pmu_sbi_reset_scounteren((void *)event); =20 + if (sbi_pmu_snapshot_available()) + flag |=3D SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT; + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, hwc->idx, 1, fla= g, 0, 0, 0); - if (ret.error && (ret.error !=3D SBI_ERR_ALREADY_STOPPED) && - flag !=3D SBI_PMU_STOP_FLAG_RESET) + if (!ret.error && sbi_pmu_snapshot_available()) { + /* + * The counter snapshot is based on the index base specified by hwc->idx. + * The actual counter value is updated in shared memory at index 0 when = counter + * mask is 0x01. To ensure accurate counter values, it's necessary to tr= ansfer + * the counter value to shared memory. However, if hwc->idx is zero, the= counter + * value is already correctly updated in shared memory, requiring no fur= ther + * adjustment. + */ + if (hwc->idx > 0) { + sdata->ctr_values[hwc->idx] =3D sdata->ctr_values[0]; + sdata->ctr_values[0] =3D 0; + } + } else if (ret.error && (ret.error !=3D SBI_ERR_ALREADY_STOPPED) && + flag !=3D SBI_PMU_STOP_FLAG_RESET) { pr_err("Stopping counter idx %d failed with error %d\n", hwc->idx, sbi_err_map_linux_errno(ret.error)); + } } =20 static int pmu_sbi_find_num_ctrs(void) @@ -652,10 +770,14 @@ static inline void pmu_sbi_stop_all(struct riscv_pmu = *pmu) static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu) { struct cpu_hw_events *cpu_hw_evt =3D this_cpu_ptr(pmu->hw_events); + unsigned long flag =3D 0; + + if (sbi_pmu_snapshot_available()) + flag =3D SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT; =20 /* No need to check the error here as we can't do anything about the erro= r */ sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, 0, - cpu_hw_evt->used_hw_ctrs[0], 0, 0, 0, 0); + cpu_hw_evt->used_hw_ctrs[0], flag, 0, 0, 0); } =20 /* @@ -664,11 +786,10 @@ static inline void pmu_sbi_stop_hw_ctrs(struct riscv_= pmu *pmu) * while the overflowed counters need to be started with updated initializ= ation * value. */ -static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, - unsigned long ctr_ovf_mask) +static noinline void pmu_sbi_start_ovf_ctrs_sbi(struct cpu_hw_events *cpu_= hw_evt, + unsigned long ctr_ovf_mask) { int idx =3D 0; - struct cpu_hw_events *cpu_hw_evt =3D this_cpu_ptr(pmu->hw_events); struct perf_event *event; unsigned long flag =3D SBI_PMU_START_FLAG_SET_INIT_VALUE; unsigned long ctr_start_mask =3D 0; @@ -703,6 +824,48 @@ static inline void pmu_sbi_start_overflow_mask(struct = riscv_pmu *pmu, } } =20 +static noinline void pmu_sbi_start_ovf_ctrs_snapshot(struct cpu_hw_events = *cpu_hw_evt, + unsigned long ctr_ovf_mask) +{ + int idx =3D 0; + struct perf_event *event; + unsigned long flag =3D SBI_PMU_START_FLAG_INIT_SNAPSHOT; + u64 max_period, init_val =3D 0; + struct hw_perf_event *hwc; + struct riscv_pmu_snapshot_data *sdata =3D cpu_hw_evt->snapshot_addr; + + for_each_set_bit(idx, cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS) { + if (ctr_ovf_mask & (BIT(idx))) { + event =3D cpu_hw_evt->events[idx]; + hwc =3D &event->hw; + max_period =3D riscv_pmu_ctr_get_width_mask(event); + init_val =3D local64_read(&hwc->prev_count) & max_period; + sdata->ctr_values[idx] =3D init_val; + } + /* + * We do not need to update the non-overflow counters the previous + * value should have been there already. + */ + } + + for (idx =3D 0; idx < BITS_TO_LONGS(RISCV_MAX_COUNTERS); idx++) { + /* Start all the counters in a single shot */ + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx * BITS_PER_LONG, + cpu_hw_evt->used_hw_ctrs[idx], flag, 0, 0, 0); + } +} + +static void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, + unsigned long ctr_ovf_mask) +{ + struct cpu_hw_events *cpu_hw_evt =3D this_cpu_ptr(pmu->hw_events); + + if (sbi_pmu_snapshot_available()) + pmu_sbi_start_ovf_ctrs_snapshot(cpu_hw_evt, ctr_ovf_mask); + else + pmu_sbi_start_ovf_ctrs_sbi(cpu_hw_evt, ctr_ovf_mask); +} + static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev) { struct perf_sample_data data; @@ -716,6 +879,7 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *d= ev) unsigned long overflowed_ctrs =3D 0; struct cpu_hw_events *cpu_hw_evt =3D dev; u64 start_clock =3D sched_clock(); + struct riscv_pmu_snapshot_data *sdata =3D cpu_hw_evt->snapshot_addr; =20 if (WARN_ON_ONCE(!cpu_hw_evt)) return IRQ_NONE; @@ -737,8 +901,10 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *= dev) pmu_sbi_stop_hw_ctrs(pmu); =20 /* Overflow status register should only be read after counter are stopped= */ - ALT_SBI_PMU_OVERFLOW(overflow); - + if (sbi_pmu_snapshot_available()) + overflow =3D sdata->ctr_overflow_mask; + else + ALT_SBI_PMU_OVERFLOW(overflow); /* * Overflow interrupt pending bit should only be cleared after stopping * all the counters to avoid any race condition. @@ -819,6 +985,9 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struc= t hlist_node *node) enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE); } =20 + if (sbi_pmu_snapshot_available()) + return pmu_sbi_snapshot_setup(pmu, cpu); + return 0; } =20 @@ -831,6 +1000,9 @@ static int pmu_sbi_dying_cpu(unsigned int cpu, struct = hlist_node *node) /* Disable all counters access for user mode now */ csr_write(CSR_SCOUNTEREN, 0x0); =20 + if (sbi_pmu_snapshot_available()) + return pmu_sbi_snapshot_disable(); + return 0; } =20 @@ -1106,10 +1278,6 @@ static int pmu_sbi_device_probe(struct platform_devi= ce *pdev) pmu->event_unmapped =3D pmu_sbi_event_unmapped; pmu->csr_index =3D pmu_sbi_csr_index; =20 - ret =3D cpuhp_state_add_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node= ); - if (ret) - return ret; - ret =3D riscv_pm_pmu_register(pmu); if (ret) goto out_unregister; @@ -1118,8 +1286,32 @@ static int pmu_sbi_device_probe(struct platform_devi= ce *pdev) if (ret) goto out_unregister; =20 + /* SBI PMU Snapsphot is only available in SBI v2.0 */ + if (sbi_v2_available) { + ret =3D pmu_sbi_snapshot_alloc(pmu); + if (ret) + goto out_unregister; + + ret =3D pmu_sbi_snapshot_setup(pmu, smp_processor_id()); + if (!ret) { + pr_info("SBI PMU snapshot detected\n"); + /* + * We enable it once here for the boot cpu. If snapshot shmem setup + * fails during cpu hotplug process, it will fail to start the cpu + * as we can not handle hetergenous PMUs with different snapshot + * capability. + */ + static_branch_enable(&sbi_pmu_snapshot_available); + } + /* Snapshot is an optional feature. Continue if not available */ + } + register_sysctl("kernel", sbi_pmu_sysctl_table); =20 + ret =3D cpuhp_state_add_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node= ); + if (ret) + return ret; + return 0; =20 out_unregister: diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index 43282e22ebe1..c3fa90970042 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -39,6 +39,12 @@ struct cpu_hw_events { DECLARE_BITMAP(used_hw_ctrs, RISCV_MAX_COUNTERS); /* currently enabled firmware counters */ DECLARE_BITMAP(used_fw_ctrs, RISCV_MAX_COUNTERS); + /* The virtual address of the shared memory where counter snapshot will b= e taken */ + void *snapshot_addr; + /* The physical address of the shared memory where counter snapshot will = be taken */ + phys_addr_t snapshot_addr_phys; + /* Boolean flag to indicate setup is already done */ + bool snapshot_set_done; }; =20 struct riscv_pmu { --=20 2.34.1 From nobody Mon Feb 9 08:54:35 2026 Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD8B97602B for ; Wed, 3 Apr 2024 08:05:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131530; cv=none; b=kFIS+IG9OdbuUD1cAf3mf7L1tEGkX9JgkGUBkOEEaWX20k4/9bWOPnAfLPY1zS8INFSBO8MWqfXaqp51u+oWpQJVeOHFlYbcIlYVufNIJXaUFyt9q6EgnQ5kqZ2NSij0+hveoiCcDZgHqtFW5Nqc8+TNs3aGEJ+PHqKzXa4jmN0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131530; c=relaxed/simple; bh=aDfanLTs21GL0maDPQpRseQyiyuKg+u1j0b2hveDXpI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=r6jZB0V6XrbAxf3D+2b4aACLD+qpzTTRaJV6cNZGYSi5tGiZ1WKOLGodW1imbF28pS6rHMaHXf56y81AVPJidrfcW2JNJd8+2lod08YTNafRKsZdTSoWuzT4Edl+EjM+D60iQax1vtKvwy1HA/9m5T00KkSLYXipwrUyi47JNJw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=2iixUOkb; arc=none smtp.client-ip=209.85.210.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="2iixUOkb" Received: by mail-pf1-f176.google.com with SMTP id d2e1a72fcca58-6e6bee809b8so5731846b3a.1 for ; Wed, 03 Apr 2024 01:05:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131527; x=1712736327; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4rw21DNPDWpaXnd5Gs3cWE2qTmUGGOZ0JnLHhYLDMiI=; b=2iixUOkb5ZvcS909cd2IhppvnztzEejMRSDC99adKGajjgp1jtLAQJ5lGxpJnmnkXf FKM3oJrgfdEAKK3vfP76gfrAjghy5khVIwIYF7SFJunpu52SD0BTSTKxP/BD27F4utB9 jTfRLGEBLDRrvUmjpBVJUVHf16VfmhhhsQNjQXFQIJI7KB2mpwfepVwdczJGhAMKYbCM aagO54xA8Bj2XqknrkufVfHoo/UOcQwcra9A1ZcLz/+Xyrfu8plWr+PwAwsahUkm10Mb XNUcukZutv8afK4JgJf4PdCY2I3mBfyn5ZjrbXcTJR2txMIppT3GM5JtHvvP+7RA/5/H Ii/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131527; x=1712736327; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4rw21DNPDWpaXnd5Gs3cWE2qTmUGGOZ0JnLHhYLDMiI=; b=ljCgpjp3iwDfWtg8hqmDR/ur1OEOSBtu88jGaxpkNOlPbqqweY1LZpC0VUoJi+9vBT Nwn6hcEQKQU6+one2/4Lm7ayo0vcktvbnmJPRBUv2m3nQsfBMn8zfl5ELl5+Y1Z/j6c/ xpiPmAmRXgUKxMNhicDbAe0hx1Q+TqXFXQVN1bfYQ4+G652gXSUw2ErDDpYMfQaswWM0 uGZQjgoLkFt0T18xpuXXDxKRMl31HLejx0MWBbjyQEodP9mquknG2QLhOj68n1hieIUs +boH1416pNIxwFdhppM3RBgim4JD/HmoQogJMOcVDDmMFhJAf4HdAzllsY6ZzVIAW1QM QirQ== X-Gm-Message-State: AOJu0YwkjgWB9Qf/dRkXTpPqTM/BZz377DrbVf5KSBhNMI/Ly8zVOiE3 /V5it1lJ/ugZq1xpysiiwQEG7EAKsrhBHD6brjnQA7uxnUM8KRPPw+ViS/GiA4xqNfOUEwEbPSg n X-Google-Smtp-Source: AGHT+IHZeguUWEErPiWxvNkeVU9lmGoRHX/48aTBnxr2DMrqRPKV9Qdy9c2zpt6UamZ4tC6ZYgwGwA== X-Received: by 2002:a05:6a20:17a7:b0:1a3:34c4:b184 with SMTP id bl39-20020a056a2017a700b001a334c4b184mr13823636pzb.19.1712131527654; Wed, 03 Apr 2024 01:05:27 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:26 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Anup Patel , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 07/22] drivers/perf: riscv: Fix counter mask iteration for RV32 Date: Wed, 3 Apr 2024 01:04:36 -0700 Message-Id: <20240403080452.1007601-8-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For RV32, used_hw_ctrs can have more than 1 word if the firmware chooses to interleave firmware/hardware counters indicies. Even though it's a unlikely scenario, handle that case by iterating over all the words instead of just using the first word. Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- drivers/perf/riscv_pmu_sbi.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 8c3475d55433..82336fec82b8 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -771,13 +771,15 @@ static inline void pmu_sbi_stop_hw_ctrs(struct riscv_= pmu *pmu) { struct cpu_hw_events *cpu_hw_evt =3D this_cpu_ptr(pmu->hw_events); unsigned long flag =3D 0; + int i; =20 if (sbi_pmu_snapshot_available()) flag =3D SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT; =20 - /* No need to check the error here as we can't do anything about the erro= r */ - sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, 0, - cpu_hw_evt->used_hw_ctrs[0], flag, 0, 0, 0); + for (i =3D 0; i < BITS_TO_LONGS(RISCV_MAX_COUNTERS); i++) + /* No need to check the error here as we can't do anything about the err= or */ + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, i * BITS_PER_LONG, + cpu_hw_evt->used_hw_ctrs[i], flag, 0, 0, 0); } =20 /* @@ -789,7 +791,7 @@ static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pm= u *pmu) static noinline void pmu_sbi_start_ovf_ctrs_sbi(struct cpu_hw_events *cpu_= hw_evt, unsigned long ctr_ovf_mask) { - int idx =3D 0; + int idx =3D 0, i; struct perf_event *event; unsigned long flag =3D SBI_PMU_START_FLAG_SET_INIT_VALUE; unsigned long ctr_start_mask =3D 0; @@ -797,11 +799,12 @@ static noinline void pmu_sbi_start_ovf_ctrs_sbi(struc= t cpu_hw_events *cpu_hw_evt struct hw_perf_event *hwc; u64 init_val =3D 0; =20 - ctr_start_mask =3D cpu_hw_evt->used_hw_ctrs[0] & ~ctr_ovf_mask; - - /* Start all the counters that did not overflow in a single shot */ - sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, 0, ctr_start_mask, - 0, 0, 0, 0); + for (i =3D 0; i < BITS_TO_LONGS(RISCV_MAX_COUNTERS); i++) { + ctr_start_mask =3D cpu_hw_evt->used_hw_ctrs[i] & ~ctr_ovf_mask; + /* Start all the counters that did not overflow in a single shot */ + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, i * BITS_PER_LONG, ctr= _start_mask, + 0, 0, 0, 0); + } =20 /* Reinitialize and start all the counter that overflowed */ while (ctr_ovf_mask) { --=20 2.34.1 From nobody Mon Feb 9 08:54:35 2026 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD3576D1AF for ; Wed, 3 Apr 2024 08:05:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131532; cv=none; b=ZEfuYtB/o8WQp+06YjenRgF7uGLdJ7IsM8HuCKAOFNGdt86doyhc7pOKylqczqOJ3WbMM65N2lwpxv8+isJkINooV6wMB/fI3VYqJ2owjuZUEOysjX4ksV+pqVbSydah35aStKbn2AdB4fzHkiSmMB5i9/4ZGL4sAuhWtAypDVI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131532; c=relaxed/simple; bh=qmTer1L5IWEJQe0rkUy5cvb4CMl5u/8y+hPoEZoMutA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Zj81jhNmz9VaU9NulnnwqcDLFK6ipS73qzqV64K/hikpxbi/niwjWEE2ZvEtvxdoUHwDNamxpmzqR99GIddiHZx1VAqbg30vb78vqHAq64W8qsPB0//8Ct0qY+Gm6vhhgQfyCiHsaJTyhnoA5O8VCz4Dnx5xD4Vk3o4e9k8g32g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=TSeifkcC; arc=none smtp.client-ip=209.85.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="TSeifkcC" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-1e0411c0a52so51648385ad.0 for ; Wed, 03 Apr 2024 01:05:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131529; x=1712736329; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2HMUEh/ouJpwrjadx4E8ELJ1oGZIEAqlVNHNOiveHPA=; b=TSeifkcCVel9tg4BDxNqVioc8wG9MlkoJ3zjDFmQ42yLVyPQQ8/t+ga6mhJbasv/cw kdJkdlohOprTHDTHFncMalAz2OKXkpESH3KiBcjPJ3O0ROPYzDMLNerLFiJXwcaURbUe 3mI2ilSR2OFLFlLOLX1B4cW/7jrw41WmIldFZwK2rPx7Q4ZzK6Bw97v8K/ZJs5yHr3TS 6SlM4sakMFvnbC9Gbl3qb8BFO+Y+NQVomRmg8WnYURs55sBXVKzOufTz7YG/ZqSp8MLp ZVpChGoH1VXBdxE7bFMf9Dp0wm1JhxgFxm0n5HeRKbSBSShB8oHiu3umukjLxijTUd35 srDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131529; x=1712736329; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2HMUEh/ouJpwrjadx4E8ELJ1oGZIEAqlVNHNOiveHPA=; b=FJs1+8/ahjNP+76QCj6oI84FSkkQYcjXW2hF6ZADnno6I7wc0NktplpZEaz/LHXjnS KA4DuOBpiMnbp28Ogsl5ki5MmEUcffoFaV59z2OiTL+i2k3vG+p5ToItWR2AafUKHsX6 06x2+vgknvcEEmxganeGSjaaMYIvOVLeeJ4kPnHUhv+V4x03qY+hpFAcwuXVoZtBNQGO jxfjjt5Vh08tzWUmHn8XXK7jVfyzx09sDQlhpyG3tMwFAG8njCse1iN7iLNnvvQFPaYM GUD7d/x6DZOZ+dIYxvdtAVaI7JLKTLSlOGKtKgpSMoDp5TtL+854HzC7Pln1WyNjUl+M IPAw== X-Gm-Message-State: AOJu0Yzf+ddMuae206tRLTS3uvczUJri5+5nhYD6oP5q+HSsx0pkRw7i GP0ub43xMNybvKIFj0jCkBDZih5jLFOcKMzzpPmvKd0UfT8vi2pKjs/Wi4rdk8IbyzTho/A9Fyo 3 X-Google-Smtp-Source: AGHT+IF30gBaFjuZamH6gB+fLa8VQAOCDXL32p+FdETcNWyCBYGk0g9s0A7zOmyK2RvO8zqC4rEDCA== X-Received: by 2002:a17:902:aa04:b0:1e2:23b8:98dd with SMTP id be4-20020a170902aa0400b001e223b898ddmr14090965plb.69.1712131529484; Wed, 03 Apr 2024 01:05:29 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:28 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Anup Patel , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 08/22] RISC-V: KVM: Fix the initial sample period value Date: Wed, 3 Apr 2024 01:04:37 -0700 Message-Id: <20240403080452.1007601-9-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The initial sample period value when counter value is not assigned should be set to maximum value supported by the counter width. Otherwise, it may result in spurious interrupts. Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- arch/riscv/kvm/vcpu_pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index 86391a5061dd..cee1b9ca4ec4 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -39,7 +39,7 @@ static u64 kvm_pmu_get_sample_period(struct kvm_pmc *pmc) u64 sample_period; =20 if (!pmc->counter_val) - sample_period =3D counter_val_mask + 1; + sample_period =3D counter_val_mask; else sample_period =3D (-pmc->counter_val) & counter_val_mask; =20 --=20 2.34.1 From nobody Mon Feb 9 08:54:35 2026 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0388811E7 for ; Wed, 3 Apr 2024 08:05:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131534; cv=none; b=cSIadLh/NIUkEB89CUIh7T5Tpg9rOKML/cGU0ZIQW+NlEk28QuSP0kvyS93v9qW68Q7jbWjz4UQxT0F1DXVocJsPLRSUp3tx0aydcqq44+3DNpJFYImq/K0GjXvc6jOxCYxNWcu8c2DnVswtVKWa83dRRrkUFA3RdIqlonH4Oh4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131534; c=relaxed/simple; bh=es6oj90niK7eIua41w4bb0VuAogviBB5JDOj1DIbVoo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XrryTfDSyo0iogR7211S9mVkdfIr6PJWMJhefcmdXNeCdbssbF1Nxz3Vf9xpfbBYr9QDLs+OJPhrt/KnPFiO6q18rLaeH9PzJ+s8JyvimxOcuOhXzDzZ1m9cdexZIPptue8DyCTJ2TDeeaGP6fiF1VPCEV0cYOE7GMhsNNP6Zag= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=kj1jNd4T; arc=none smtp.client-ip=209.85.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="kj1jNd4T" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-1e28856ed7aso8288245ad.0 for ; Wed, 03 Apr 2024 01:05:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131531; x=1712736331; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+MJsU2/1DVF77yTSQMrmRq+eYVFGn04LSwUVmAHv4W8=; b=kj1jNd4T8fIHxcVBo6zc+oA4iL6egZxuQwfHFbT8z3Lqfur2HrQO/pwmBQsivMY8rW v2T+XavCkXLQlN1z/o+pjAuh/mRhz6/BQmNZs1SO/T1YyWu3pBcoh0khpDdz/iJmJnVF Jml3E+a2iYTsOq3E+xSYwN1y/zHwAnUo6MSpkVkQmX4o0j9FdYjhB5pOnUbR1grpcjaT IEEeW1IXghX2DWT/wn5TX8eIp8wAhfi9jq53iL5+4rs8oI0gu0zHkkGRYy2naSN73QrG bDtEoGVgdXEEjlIIofYSt7+rRLudeP3zVh77IjZUHNNpwg3GHe6De9D5zbgQ7jlZWRBP NLAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131531; x=1712736331; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+MJsU2/1DVF77yTSQMrmRq+eYVFGn04LSwUVmAHv4W8=; b=sGsZjzKvpCE7WIC1ZiJxQLYtS5tu4itxbtlSZRKueDp3ayWxCzhLWx56QwaBVbfCHK DEm4cxLzGZrjBhapMa5mflKG6W5XX9ACk8+ZI/AxCQrIm3i2kCITcmCTBif9xrGDp2YM YBqFGmB+PyVgzxJAQSRKh+nRiUKxeoRt/ZdGD3yR7rDdMOYgvnFT8BVsGKAUhiWwtV1K Ael7M8i/jbc5/BLFSQTWUeR4TfPGz2c5AyF2WFa7OF3cC8LIaFyfK8aYQnyU2UV1Dnj8 C4HLUM3rnILkm5h/0hp8nQqOeqBolHEWLWIS9waikDLuvqXvl8OzlWcK5jX92O3kaa+q To5w== X-Gm-Message-State: AOJu0Yy5uMsBZLXxN03DEJ6hp+gXrxKLk7GPtEoIChaINAa3k0HPGyGP nho8k2Hbplmv8UsQDVYVX7JUFPUhxIHmVCwW1TYKkOSHBe1CJ7WwGWINd8swBxWdfHE0jW9Z8d+ 9 X-Google-Smtp-Source: AGHT+IE6hcM+iluLyfs2xAMwl4nidxEf2cHLsogRdu+mNxI8DxtzYjnOXL+jL/8fbjTuoDpYxOz/uQ== X-Received: by 2002:a17:903:244c:b0:1e2:6191:f6ae with SMTP id l12-20020a170903244c00b001e26191f6aemr2389190pls.0.1712131531142; Wed, 03 Apr 2024 01:05:31 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:30 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Anup Patel , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 09/22] RISC-V: KVM: Rename the SBI_STA_SHMEM_DISABLE to a generic name Date: Wed, 3 Apr 2024 01:04:38 -0700 Message-Id: <20240403080452.1007601-10-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SBI_STA_SHMEM_DISABLE is a macro to invoke disable shared memory commands. As this can be invoked from other SBI extension context as well, rename it to more generic name as SBI_SHMEM_DISABLE. Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- arch/riscv/include/asm/sbi.h | 2 +- arch/riscv/kernel/paravirt.c | 6 +++--- arch/riscv/kvm/vcpu_sbi_sta.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 9aada4b9f7b5..f31650b10899 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -277,7 +277,7 @@ struct sbi_sta_struct { u8 pad[47]; } __packed; =20 -#define SBI_STA_SHMEM_DISABLE -1 +#define SBI_SHMEM_DISABLE -1 =20 /* SBI spec version fields */ #define SBI_SPEC_VERSION_DEFAULT 0x1 diff --git a/arch/riscv/kernel/paravirt.c b/arch/riscv/kernel/paravirt.c index 0d6225fd3194..fa6b0339a65d 100644 --- a/arch/riscv/kernel/paravirt.c +++ b/arch/riscv/kernel/paravirt.c @@ -62,7 +62,7 @@ static int sbi_sta_steal_time_set_shmem(unsigned long lo,= unsigned long hi, ret =3D sbi_ecall(SBI_EXT_STA, SBI_EXT_STA_STEAL_TIME_SET_SHMEM, lo, hi, flags, 0, 0, 0); if (ret.error) { - if (lo =3D=3D SBI_STA_SHMEM_DISABLE && hi =3D=3D SBI_STA_SHMEM_DISABLE) + if (lo =3D=3D SBI_SHMEM_DISABLE && hi =3D=3D SBI_SHMEM_DISABLE) pr_warn("Failed to disable steal-time shmem"); else pr_warn("Failed to set steal-time shmem"); @@ -84,8 +84,8 @@ static int pv_time_cpu_online(unsigned int cpu) =20 static int pv_time_cpu_down_prepare(unsigned int cpu) { - return sbi_sta_steal_time_set_shmem(SBI_STA_SHMEM_DISABLE, - SBI_STA_SHMEM_DISABLE, 0); + return sbi_sta_steal_time_set_shmem(SBI_SHMEM_DISABLE, + SBI_SHMEM_DISABLE, 0); } =20 static u64 pv_time_steal_clock(int cpu) diff --git a/arch/riscv/kvm/vcpu_sbi_sta.c b/arch/riscv/kvm/vcpu_sbi_sta.c index d8cf9ca28c61..5f35427114c1 100644 --- a/arch/riscv/kvm/vcpu_sbi_sta.c +++ b/arch/riscv/kvm/vcpu_sbi_sta.c @@ -93,8 +93,8 @@ static int kvm_sbi_sta_steal_time_set_shmem(struct kvm_vc= pu *vcpu) if (flags !=3D 0) return SBI_ERR_INVALID_PARAM; =20 - if (shmem_phys_lo =3D=3D SBI_STA_SHMEM_DISABLE && - shmem_phys_hi =3D=3D SBI_STA_SHMEM_DISABLE) { + if (shmem_phys_lo =3D=3D SBI_SHMEM_DISABLE && + shmem_phys_hi =3D=3D SBI_SHMEM_DISABLE) { vcpu->arch.sta.shmem =3D INVALID_GPA; return 0; } --=20 2.34.1 From nobody Mon Feb 9 08:54:35 2026 Received: from mail-pf1-f178.google.com (mail-pf1-f178.google.com [209.85.210.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B74A182C7D for ; Wed, 3 Apr 2024 08:05:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131536; cv=none; b=T0qbfAa63fLLdf8eU+8/Drt6WxqVbEOTfV8IbK494gPt2jGr9F5mjgexq+xY7zEU7Oxq8xoj98gq6L550TGPFSfQsfksih7//qq394Dw003AJCv31n7pktKwtLweg7/5zoWXfNOr9d5PRBLQw4ABVihSXCFp4dHxlZ3/kITcyqA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131536; c=relaxed/simple; bh=+BS7mctHpN9iWLFPEwC2/74zIoWzY97OXSTjHAOIU1s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=o34/xEIVKVwRpYeF4+fVnxTsQICBJhIy+5wLhUJ5EWm6hpAegM3LXWP2/kkVxB1MiPUl6PW63qkPKBZZ8oiDBh3AFozERcxOoUg3QpGs1HxC+EFZwOuTJFPKb+uCOvaZh9Yh3/upmYfX7dGSl9j7rS4pUeaDL+1RwWqNHY98PqM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=LoaKepvw; arc=none smtp.client-ip=209.85.210.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="LoaKepvw" Received: by mail-pf1-f178.google.com with SMTP id d2e1a72fcca58-6ea7f2d093aso5682243b3a.3 for ; Wed, 03 Apr 2024 01:05:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131533; x=1712736333; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oLadZMY/1E+aj61iqE390ie32fUnJXqsMN5cFXtebck=; b=LoaKepvwpIgMgTETh3kzvXiZiZwSk+B9o73db2yUsrHf0PeqmmT4O4FXUjdiF6lgH9 +SJTk8Gp6utJJzIeThkrwLJp0MkiycHvkrPfjfaUDYF9G0kuF2olWU0A9/MGQcI/1YHq ePSbSQa4NDp1GdSg5ozbKaFx6dny/viVqIQhIhfawKkC8GCzYZ86G/Np1ZnrHtrEdzFG Ia31qc9p6AvwgtLwXeT23pDuQCNoDayhHtGguhQ//jSZsvEW+nsWqQ8tNS7uMugcnWK2 0qApW4wFGj1MmdZNsRCk5LFO9sekAdwsTLJCTs9wmR3OsbpnYZmHXW5TFHHWYI76Z315 17Sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131533; x=1712736333; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oLadZMY/1E+aj61iqE390ie32fUnJXqsMN5cFXtebck=; b=NIeHzEP7OLh2l+0+ODQul6XTABgPdYjqZuAhli3nNJn8IuBk+zKLSBDS4t+DGosy/U B2t1Vq7QbwM9w4oJQ5rEKBkbnRKlvXssWNFFQ0GQ8R5ErGDCiP+EkEaXnYd1uQlwqDh9 qVgBo27sYbRa8vCsQxAlOT62BHXlMfftYqaUMR1XbmQYK+XAbr+Dtw2E3e4Ieq2w23W1 rnPnbQaOTcZuQwO+VXy1uiJJG3WVQ9f4z9DCgc8WjWl11gqoOVbegnZOBluhNL659tIo Q4/RUlwAcja/kiHhoj0hv6BeW3mVxuW8NDhK+mZNfXyYPVvUWA69RpQEAvEbm7zWNISi EKRA== X-Gm-Message-State: AOJu0YyyBG/TtUTy1KYJ24q63wzgGkthzkH6TrKi6+qkdBPtTJxVLVkl 4urP2HTOpdeKZXzmLLWoiw8SMaENFZAIN35fXpt9yfg1+UH8ZU9drGmlOUCqlx9TiB9BWxSxJ9q / X-Google-Smtp-Source: AGHT+IHYBgMwEeWVbd4P9PNDRXwi0PIWRTlB15cj+AGKTpxTy9q1IU7RrYP0KIGaFYPVod/3S9sbOg== X-Received: by 2002:a05:6a21:3294:b0:1a5:6a85:8ce9 with SMTP id yt20-20020a056a21329400b001a56a858ce9mr2619252pzb.12.1712131533285; Wed, 03 Apr 2024 01:05:33 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:32 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Andrew Jones , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 10/22] RISC-V: KVM: No need to update the counter value during reset Date: Wed, 3 Apr 2024 01:04:39 -0700 Message-Id: <20240403080452.1007601-11-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The virtual counter value is updated during pmu_ctr_read. There is no need to update it in reset case. Otherwise, it will be counted twice which is incorrect. Fixes: 0cb74b65d2e5 ("RISC-V: KVM: Implement perf support without sampling") Reviewed-by: Anup Patel Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- arch/riscv/kvm/vcpu_pmu.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index cee1b9ca4ec4..b5159ce4592d 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -397,7 +397,6 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, = unsigned long ctr_base, { struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); int i, pmc_index, sbiret =3D 0; - u64 enabled, running; struct kvm_pmc *pmc; int fevent_code; =20 @@ -432,12 +431,9 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu,= unsigned long ctr_base, sbiret =3D SBI_ERR_ALREADY_STOPPED; } =20 - if (flags & SBI_PMU_STOP_FLAG_RESET) { - /* Relase the counter if this is a reset request */ - pmc->counter_val +=3D perf_event_read_value(pmc->perf_event, - &enabled, &running); + if (flags & SBI_PMU_STOP_FLAG_RESET) + /* Release the counter if this is a reset request */ kvm_pmu_release_perf_event(pmc); - } } else { sbiret =3D SBI_ERR_INVALID_PARAM; } --=20 2.34.1 From nobody Mon Feb 9 08:54:35 2026 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B73FB83CC9 for ; Wed, 3 Apr 2024 08:05:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131538; cv=none; b=hyp3KseAZg8627p23K44TrkERmTUEmUqepdSNTOT69NQMFy5BwaeYhuEolE4bnjXKkFtw3HRSeTDv3c9wxfdqKlJcBDtwP4VNh3QpA6o6pQQ930Uy9h3bF7lKJ40I+Om+NcfGGtRWhKxVq/EO8tM1HedgeG4uvCo86uVsf1rsFE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131538; c=relaxed/simple; bh=HvWaHaPle0cX5HGWWdRxWlP3z/kNux1E5mFj4+zTNsM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=c82xTAoo8nz4cxFe+/yymSj6jAeYsu+feh+y5GkU+nyU7WEecKmWtGUMhXoJXwIKbMiD4/E0ynlBZtpuv5xkO+0Fcbnt+DwQxUTZFTEpmP1brv9sagZAxh5aKcbR0g6aedGgkpc3RBN5v0I1qZkiIwMnzq65mfdigFx26zA24Cs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=wZrRzEN4; arc=none smtp.client-ip=209.85.214.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="wZrRzEN4" Received: by mail-pl1-f182.google.com with SMTP id d9443c01a7336-1e0d8403257so47314505ad.1 for ; Wed, 03 Apr 2024 01:05:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131535; x=1712736335; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QIyaUvQe1Xat3Gv2wtXts1DoFv5C5UbopqhCGzslRuw=; b=wZrRzEN4mvK+xE6qW9yhoyBS7dtZadBB/pH+gn+EpBESynBYMsudJxE6XM0vBjKRB3 RJE2txVaYQacAX6JAGkvULmXR0NcL819Xptbg8nrZXvowUAR8TPXvWHN5KUGnHWWtr9K 1Bp9h+SV/BT/p/pG9NVf8U16filPqgWS0Dpbvu4tRDxo0V4ImkkQLfUeTcb4aL089Q/H NIBJ4Kyb2PTq1CrDOKRlieh++SM4v3yORgLpb9XDl6lbqgdGny+kzKveh7MyhdOlXXJz 7TbM01q2FeI2uYA75bD7BsLrb89HNKN5hqYrKUXePkvUwFdhdVs87jmO85njLvDL6Phi RuDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131535; x=1712736335; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QIyaUvQe1Xat3Gv2wtXts1DoFv5C5UbopqhCGzslRuw=; b=U8CNg4T3iVxIozREjIyN40fmsUxu2YwL67gd+TCPxgH484hY3C2FpNL8ory+8upDiE 4LlawWGzgCr+rcKNySVoDtRUKjAHhPn8sS3QG9wSIx4tK/11qBpLyHnK6kzEekLsk3zT fmsuyUqgJdaWXjSlsYHg/Gs1DsMWdy2OxIr7tejIQX05Y4dz9pbOjtK0p/O1hCXbbtw8 Sa46X7MFoyZHFlSAzlo7/LM6GrrXgNb6AbrEFxK9NlWfTV33DwRQ7xqShZxfSTF1gbfk 21xs+i+UKLGP9zcPLL4Bzk0bOCQPjXAuQBk0UWAcK5/aOMd3/yZnD7Muv9wqI76Rzob7 zzbw== X-Gm-Message-State: AOJu0Yws+0Dxbx0f+hWgK4f2VCYnqAnOJTYEZD1TJPzakiGNBoR91vTH tuAaEmb2VhpDHdFCeo/sx3dsalH5rljqM7rB6uEAlGCKOprlXfFTVa/fcylQsBaBk/+z2/vLcIt R X-Google-Smtp-Source: AGHT+IEWaMwJlilOpjjtAd3ogSZtQYb7+W8r4UBVM9U3DF3iIMbLdC4POqTiOnAm6aIo/b0Y3UPrBw== X-Received: by 2002:a17:902:7881:b0:1e0:cd01:9fd with SMTP id q1-20020a170902788100b001e0cd0109fdmr11915195pll.26.1712131535324; Wed, 03 Apr 2024 01:05:35 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:34 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 11/22] RISC-V: KVM: No need to exit to the user space if perf event failed Date: Wed, 3 Apr 2024 01:04:40 -0700 Message-Id: <20240403080452.1007601-12-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, we return a linux error code if creating a perf event failed in kvm. That shouldn't be necessary as guest can continue to operate without perf profiling or profiling with firmware counters. Return appropriate SBI error code to indicate that PMU configuration failed. An error message in kvm already describes the reason for failure. Fixes: 0cb74b65d2e5 ("RISC-V: KVM: Implement perf support without sampling") Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/kvm/vcpu_pmu.c | 14 +++++++++----- arch/riscv/kvm/vcpu_sbi_pmu.c | 6 +++--- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index b5159ce4592d..2d9929bbc2c8 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -229,8 +229,9 @@ static int kvm_pmu_validate_counter_mask(struct kvm_pmu= *kvpmu, unsigned long ct return 0; } =20 -static int kvm_pmu_create_perf_event(struct kvm_pmc *pmc, struct perf_even= t_attr *attr, - unsigned long flags, unsigned long eidx, unsigned long evtdata) +static long kvm_pmu_create_perf_event(struct kvm_pmc *pmc, struct perf_eve= nt_attr *attr, + unsigned long flags, unsigned long eidx, + unsigned long evtdata) { struct perf_event *event; =20 @@ -454,7 +455,8 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *v= cpu, unsigned long ctr_ba unsigned long eidx, u64 evtdata, struct kvm_vcpu_sbi_return *retdata) { - int ctr_idx, ret, sbiret =3D 0; + int ctr_idx, sbiret =3D 0; + long ret; bool is_fevent; unsigned long event_code; u32 etype =3D kvm_pmu_get_perf_event_type(eidx); @@ -513,8 +515,10 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *= vcpu, unsigned long ctr_ba kvpmu->fw_event[event_code].started =3D true; } else { ret =3D kvm_pmu_create_perf_event(pmc, &attr, flags, eidx, evtdata); - if (ret) - return ret; + if (ret) { + sbiret =3D SBI_ERR_NOT_SUPPORTED; + goto out; + } } =20 set_bit(ctr_idx, kvpmu->pmc_in_use); diff --git a/arch/riscv/kvm/vcpu_sbi_pmu.c b/arch/riscv/kvm/vcpu_sbi_pmu.c index 7eca72df2cbd..e1633606c98b 100644 --- a/arch/riscv/kvm/vcpu_sbi_pmu.c +++ b/arch/riscv/kvm/vcpu_sbi_pmu.c @@ -42,9 +42,9 @@ static int kvm_sbi_ext_pmu_handler(struct kvm_vcpu *vcpu,= struct kvm_run *run, #endif /* * This can fail if perf core framework fails to create an event. - * Forward the error to userspace because it's an error which - * happened within the host kernel. The other option would be - * to convert to an SBI error and forward to the guest. + * No need to forward the error to userspace and exit the guest. + * The operation can continue without profiling. Forward the + * appropriate SBI error to the guest. */ ret =3D kvm_riscv_vcpu_pmu_ctr_cfg_match(vcpu, cp->a0, cp->a1, cp->a2, cp->a3, temp, retdata); --=20 2.34.1 From nobody Mon Feb 9 08:54:35 2026 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9215484FD3 for ; Wed, 3 Apr 2024 08:05:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131540; cv=none; b=D4rqqXha8SsJexWQXBdKdCrnKafhpakJJxoLxGYWp4tgXu7rFIBy38jA13pkHyExJkJu3lAzR/ZxaERrUSj5GKXpxQay5G/V2SsdSt4tIA7xl5a3UpOpE34Fwjii09Jr/nj0hWzxZ96QQFAf35g99bVMpq1lSx59atuDkMBRy0U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131540; c=relaxed/simple; bh=fyePwwWWrg8gQXs2oxA5cwzCtZuwvWogsu3Knqj6XRE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QjJgUF4FgL74PcjT3V+e+8sZXqNGwTXskDjlBNRKN/PpprYJphQQWLFykfsRJzLTEbTeQgts6LUQvzeyjEfNeqcPGqglThTtKDq2lLFPlcuDQlQwv+UzAZsc5WIrObIYZVKXRUltlfPsflnhQDPOE+lLt7tQN6rEKr6iHbIoSlc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=h3hEgYBp; arc=none smtp.client-ip=209.85.214.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="h3hEgYBp" Received: by mail-pl1-f172.google.com with SMTP id d9443c01a7336-1e0878b76f3so5697075ad.0 for ; Wed, 03 Apr 2024 01:05:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131537; x=1712736337; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DuA34i2i05BdrpKVxBo9U52t2zQUfVSke6lRxCYCo/Y=; b=h3hEgYBpNfAl9MadzhQDutdRVG4xSm86n0L+6SRRmww8kkV9hAUSNjzdQjoZ1CAILM qA9KgsgUkox+v1cLWlT5sX9iB7F/hwiizCLcGiDJUqhjRkIYoKvxo0pCeFwsdpfHX3Kd MOjEq9XIIIX2DSO4bdtLOvxPyc69gZimSCYCdRYZUqI3QyiTORQefWka5dn5x+0rsPml FavTTvZdPbtBilGu3EVjTumWJS0JXR85Zu3Sr9AfHIna/tWbcVit3OuoEkYKigS8aB0u A++JLOoqRU61mJg6K6NyxxojVnbzqi0vhHsX2nZ9vkf3mdbWe3Mnsc72DafqQQemWLZ1 pXZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131537; x=1712736337; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DuA34i2i05BdrpKVxBo9U52t2zQUfVSke6lRxCYCo/Y=; b=ft9A7dJeqL4ndz5YzqSXL+E8/g8tFHKFYHtSjy3lNc46t0n+WJvSfAPxJ53kvczA0F 9f3OlATPQTnslfXlKpYgxTwsZrysrbGRIzhhO/DStRxJpO2YZJfSTvehvBWE9Ns+XDwH /M6LRoVbD1xYk1KQxGk0/GhcTI8pYAwwasxhJC2SBIB0FR0DT2/jMljZyTefJaiKBpV3 PbcvSkNy40GTJob5NCyDm5N0FWnuqPOTY9fn4jQotbclYsd/PEZu/HpJrzFfWrjdrEaE E41MX3TL4rBAf7SMLQZpB7nZhXylUUGg7ydKtnlSfw0F1Na49ewxCRtRAGsbnOSTjyX+ XMrg== X-Gm-Message-State: AOJu0YzxbHkyIT5gNY9+InWbskRCiSDTY8aDiOi6WG3XNiK8appIdspF edHy6jwYaA8P35UrHV+OxMEkZn72QJYIcJVvJ9eg//3rg22qd6MDYqM0e7FcXaY0Ayd3xGBHWhq T X-Google-Smtp-Source: AGHT+IFBrDynPtuhgjL+hZ1dZyV0Uqc7RiuyZWbbuSRb3GyHkug7a6buerfzOAosBHqmfYwR+/IA1w== X-Received: by 2002:a17:902:a984:b0:1e0:dc6e:45ed with SMTP id bh4-20020a170902a98400b001e0dc6e45edmr2249678plb.15.1712131537573; Wed, 03 Apr 2024 01:05:37 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:36 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 12/22] RISC-V: KVM: Implement SBI PMU Snapshot feature Date: Wed, 3 Apr 2024 01:04:41 -0700 Message-Id: <20240403080452.1007601-13-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" PMU Snapshot function allows to minimize the number of traps when the guest access configures/access the hpmcounters. If the snapshot feature is enabled, the hypervisor updates the shared memory with counter data and state of overflown counters. The guest can just read the shared memory instead of trap & emulate done by the hypervisor. This patch doesn't implement the counter overflow yet. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 7 ++ arch/riscv/kvm/vcpu_pmu.c | 121 +++++++++++++++++++++++++- arch/riscv/kvm/vcpu_sbi_pmu.c | 3 + 3 files changed, 130 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm= /kvm_vcpu_pmu.h index 395518a1664e..77a1fc4d203d 100644 --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -50,6 +50,10 @@ struct kvm_pmu { bool init_done; /* Bit map of all the virtual counter used */ DECLARE_BITMAP(pmc_in_use, RISCV_KVM_MAX_COUNTERS); + /* The address of the counter snapshot area (guest physical address) */ + gpa_t snapshot_addr; + /* The actual data of the snapshot */ + struct riscv_pmu_snapshot_data *sdata; }; =20 #define vcpu_to_pmu(vcpu) (&(vcpu)->arch.pmu_context) @@ -85,6 +89,9 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcp= u, unsigned long ctr_ba int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, struct kvm_vcpu_sbi_return *retdata); void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu); +int kvm_riscv_vcpu_pmu_snapshot_set_shmem(struct kvm_vcpu *vcpu, unsigned = long saddr_low, + unsigned long saddr_high, unsigned long flags, + struct kvm_vcpu_sbi_return *retdata); void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu); =20 diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index 2d9929bbc2c8..f706c688b338 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -14,6 +14,7 @@ #include #include #include +#include #include =20 #define kvm_pmu_num_counters(pmu) ((pmu)->num_hw_ctrs + (pmu)->num_fw_ctrs) @@ -311,6 +312,80 @@ int kvm_riscv_vcpu_pmu_read_hpm(struct kvm_vcpu *vcpu,= unsigned int csr_num, return ret; } =20 +static void kvm_pmu_clear_snapshot_area(struct kvm_vcpu *vcpu) +{ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + int snapshot_area_size =3D sizeof(struct riscv_pmu_snapshot_data); + + if (kvpmu->sdata) { + if (kvpmu->snapshot_addr !=3D INVALID_GPA) { + memset(kvpmu->sdata, 0, snapshot_area_size); + kvm_vcpu_write_guest(vcpu, kvpmu->snapshot_addr, + kvpmu->sdata, snapshot_area_size); + } else { + pr_warn("snapshot address invalid\n"); + } + kfree(kvpmu->sdata); + kvpmu->sdata =3D NULL; + } + kvpmu->snapshot_addr =3D INVALID_GPA; +} + +int kvm_riscv_vcpu_pmu_snapshot_set_shmem(struct kvm_vcpu *vcpu, unsigned = long saddr_low, + unsigned long saddr_high, unsigned long flags, + struct kvm_vcpu_sbi_return *retdata) +{ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + int snapshot_area_size =3D sizeof(struct riscv_pmu_snapshot_data); + int sbiret =3D 0; + gpa_t saddr; + unsigned long hva; + bool writable; + + if (!kvpmu || flags) { + sbiret =3D SBI_ERR_INVALID_PARAM; + goto out; + } + + if (saddr_low =3D=3D SBI_SHMEM_DISABLE && saddr_high =3D=3D SBI_SHMEM_DIS= ABLE) { + kvm_pmu_clear_snapshot_area(vcpu); + return 0; + } + + saddr =3D saddr_low; + + if (saddr_high !=3D 0) { + if (IS_ENABLED(CONFIG_32BIT)) + saddr |=3D ((gpa_t)saddr << 32); + else + sbiret =3D SBI_ERR_INVALID_ADDRESS; + goto out; + } + + hva =3D kvm_vcpu_gfn_to_hva_prot(vcpu, saddr >> PAGE_SHIFT, &writable); + if (kvm_is_error_hva(hva) || !writable) { + sbiret =3D SBI_ERR_INVALID_ADDRESS; + goto out; + } + + kvpmu->sdata =3D kzalloc(snapshot_area_size, GFP_ATOMIC); + if (!kvpmu->sdata) + return -ENOMEM; + + if (kvm_vcpu_write_guest(vcpu, saddr, kvpmu->sdata, snapshot_area_size)) { + kfree(kvpmu->sdata); + sbiret =3D SBI_ERR_FAILURE; + goto out; + } + + kvpmu->snapshot_addr =3D saddr; + +out: + retdata->err_val =3D sbiret; + + return 0; +} + int kvm_riscv_vcpu_pmu_num_ctrs(struct kvm_vcpu *vcpu, struct kvm_vcpu_sbi_return *retdata) { @@ -344,20 +419,38 @@ int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcp= u, unsigned long ctr_base, int i, pmc_index, sbiret =3D 0; struct kvm_pmc *pmc; int fevent_code; + bool snap_flag_set =3D flags & SBI_PMU_START_FLAG_INIT_SNAPSHOT; =20 if (kvm_pmu_validate_counter_mask(kvpmu, ctr_base, ctr_mask) < 0) { sbiret =3D SBI_ERR_INVALID_PARAM; goto out; } =20 + if (snap_flag_set) { + if (kvpmu->snapshot_addr =3D=3D INVALID_GPA) { + sbiret =3D SBI_ERR_NO_SHMEM; + goto out; + } + if (kvm_vcpu_read_guest(vcpu, kvpmu->snapshot_addr, kvpmu->sdata, + sizeof(struct riscv_pmu_snapshot_data))) { + pr_warn("Unable to read snapshot shared memory while starting counters\= n"); + sbiret =3D SBI_ERR_FAILURE; + goto out; + } + } /* Start the counters that have been configured and requested by the gues= t */ for_each_set_bit(i, &ctr_mask, RISCV_MAX_COUNTERS) { pmc_index =3D i + ctr_base; if (!test_bit(pmc_index, kvpmu->pmc_in_use)) continue; pmc =3D &kvpmu->pmc[pmc_index]; - if (flags & SBI_PMU_START_FLAG_SET_INIT_VALUE) + if (flags & SBI_PMU_START_FLAG_SET_INIT_VALUE) { pmc->counter_val =3D ival; + } else if (snap_flag_set) { + /* The counter index in the snapshot are relative to the counter base */ + pmc->counter_val =3D kvpmu->sdata->ctr_values[i]; + } + if (pmc->cinfo.type =3D=3D SBI_PMU_CTR_TYPE_FW) { fevent_code =3D get_event_code(pmc->event_idx); if (fevent_code >=3D SBI_PMU_FW_MAX) { @@ -398,14 +491,22 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu= , unsigned long ctr_base, { struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); int i, pmc_index, sbiret =3D 0; + u64 enabled, running; struct kvm_pmc *pmc; int fevent_code; + bool snap_flag_set =3D flags & SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT; + bool shmem_needs_update =3D false; =20 if (kvm_pmu_validate_counter_mask(kvpmu, ctr_base, ctr_mask) < 0) { sbiret =3D SBI_ERR_INVALID_PARAM; goto out; } =20 + if (snap_flag_set && kvpmu->snapshot_addr =3D=3D INVALID_GPA) { + sbiret =3D SBI_ERR_NO_SHMEM; + goto out; + } + /* Stop the counters that have been configured and requested by the guest= */ for_each_set_bit(i, &ctr_mask, RISCV_MAX_COUNTERS) { pmc_index =3D i + ctr_base; @@ -438,12 +539,28 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu= , unsigned long ctr_base, } else { sbiret =3D SBI_ERR_INVALID_PARAM; } + + if (snap_flag_set && !sbiret) { + if (pmc->cinfo.type =3D=3D SBI_PMU_CTR_TYPE_FW) + pmc->counter_val =3D kvpmu->fw_event[fevent_code].value; + else if (pmc->perf_event) + pmc->counter_val +=3D perf_event_read_value(pmc->perf_event, + &enabled, &running); + /* TODO: Add counter overflow support when sscofpmf support is added */ + kvpmu->sdata->ctr_values[i] =3D pmc->counter_val; + shmem_needs_update =3D true; + } + if (flags & SBI_PMU_STOP_FLAG_RESET) { pmc->event_idx =3D SBI_PMU_EVENT_IDX_INVALID; clear_bit(pmc_index, kvpmu->pmc_in_use); } } =20 + if (shmem_needs_update) + kvm_vcpu_write_guest(vcpu, kvpmu->snapshot_addr, kvpmu->sdata, + sizeof(struct riscv_pmu_snapshot_data)); + out: retdata->err_val =3D sbiret; =20 @@ -566,6 +683,7 @@ void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) kvpmu->num_hw_ctrs =3D num_hw_ctrs + 1; kvpmu->num_fw_ctrs =3D SBI_PMU_FW_MAX; memset(&kvpmu->fw_event, 0, SBI_PMU_FW_MAX * sizeof(struct kvm_fw_event)); + kvpmu->snapshot_addr =3D INVALID_GPA; =20 if (kvpmu->num_hw_ctrs > RISCV_KVM_MAX_HW_CTRS) { pr_warn_once("Limiting the hardware counters to 32 as specified by the I= SA"); @@ -625,6 +743,7 @@ void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu) } bitmap_zero(kvpmu->pmc_in_use, RISCV_MAX_COUNTERS); memset(&kvpmu->fw_event, 0, SBI_PMU_FW_MAX * sizeof(struct kvm_fw_event)); + kvm_pmu_clear_snapshot_area(vcpu); } =20 void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu) diff --git a/arch/riscv/kvm/vcpu_sbi_pmu.c b/arch/riscv/kvm/vcpu_sbi_pmu.c index e1633606c98b..d3e7625fb2d2 100644 --- a/arch/riscv/kvm/vcpu_sbi_pmu.c +++ b/arch/riscv/kvm/vcpu_sbi_pmu.c @@ -64,6 +64,9 @@ static int kvm_sbi_ext_pmu_handler(struct kvm_vcpu *vcpu,= struct kvm_run *run, case SBI_EXT_PMU_COUNTER_FW_READ: ret =3D kvm_riscv_vcpu_pmu_ctr_read(vcpu, cp->a0, retdata); break; + case SBI_EXT_PMU_SNAPSHOT_SET_SHMEM: + ret =3D kvm_riscv_vcpu_pmu_snapshot_set_shmem(vcpu, cp->a0, cp->a1, cp->= a2, retdata); + break; default: retdata->err_val =3D SBI_ERR_NOT_SUPPORTED; } --=20 2.34.1 From nobody Mon Feb 9 08:54:35 2026 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54AB385C70 for ; Wed, 3 Apr 2024 08:05:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131542; cv=none; b=IKrzZIxsSK3YrWA9cR6CKHPB4pJLgcLeoVe14G73Y3ZlxcG07kGnav3TGFmBcwblxkfCaI8E0O9nJX8PW+8QZSVj3lpCYAd2x+u5VpSFGRpQb3MK5KS5iemno9bppOrxK2SaIyV0v3J7qGTN704OwYAvSwoqoZVc9iH1sq//X9g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131542; c=relaxed/simple; bh=k4ht5fPKzHi8dbRtaQAL6ShV2+aw2LqyhRhjF4qZ05w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=lJYKlzlqC31OXuFuXhaW5aYONUacii/WpWSBhgkJ/b58uwlS/1IKQXvYufRztPIcI7er4gMgtWKshkWMN2ukmz7lhcBLTGLKvae/Hf6dswy19x0jTG2UEQT+3bpb3alLQPins0w43XyW6qpVkrRXnRTkxYsTHO6dyZZwX8qEb9w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=uiwcB25f; arc=none smtp.client-ip=209.85.214.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="uiwcB25f" Received: by mail-pl1-f171.google.com with SMTP id d9443c01a7336-1e28856ed7aso8289165ad.0 for ; Wed, 03 Apr 2024 01:05:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131539; x=1712736339; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rXnCfEQr49seHP/FSHmxz/iFr1Wo4k3zkXIMwp9jdU8=; b=uiwcB25f53AjgNd4T44xsjxvXanGR28aI9oKrJswM9KEBqcmNW1sqgt/z5ZZ2x4/qp lv5a9050OPv3yUPu6Tqhjn2SH6rDwK0GnrtcVtT88z//OHbhmcEn5yoL/JAMaFqiUO73 Rtq9jaEyJlDh2hXfl+aF/rCFI7etGorcKsKorlQtNVdkbbpk15ujyyfGqRlXvNMPuJH6 fsLn3eiB8QeZJkRoaGwLnR3n8egxbbwhx16jDfHyWV9Vgm3ldsitgwngXzXSzKdRFkqh AkW3cWu0c5b7EjMNDrh8sWwPzlJnZMYWLvU59SFaH/ZywbFjL/4lIBrtKASTSoW2LDzQ SZ6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131539; x=1712736339; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rXnCfEQr49seHP/FSHmxz/iFr1Wo4k3zkXIMwp9jdU8=; b=uyvRBTSvB0w5N1rY5KPAZg8SGTBaxUzMBfUbQtmGNujnfB1uFek5M3Vk528UwZYS8N V2EfH2cQXz1hBhOylaL2DUB+6DgLiFa4RLwBQBHwQMhcgoBPiBCfTwsPWR3ULg1FatMU tCgwKTDwhXcNSfv4RLRrdyrK1LfHNOhq4HiOLcW0Auywq8m2dKJtuDFcRxfp7mAVW+6r txA2A865O59qHhEcvncZ5emaZ8h3EH4IjPoCxj3d47pA+J5fAxwlvU7NqlsWAWkKQaWU mm92yEvUac9qVuchlfYF5isUB8oTMZJJNmpRWuOBAWfZKD3f7wqPff5IriFpR1JzKLLo 8Q6w== X-Gm-Message-State: AOJu0Yyq+5qKooxHB4qv5c59mYyHwEMdF3Kse9CSgkDtY0WHcW0bz4mS ScrI/8gNuWY9MHHl+15zmgBWPefJ5ovUKzautMZ1DCHjQv8ONSCgNKlluEOZGaHH91omXW4Hvoy i X-Google-Smtp-Source: AGHT+IEKAQtLJdG29phCvANRsKDlhQNvytpbUBwT9LiLceHxJiumwFb6nYVGbmAmgyUeS4Et5t4rgw== X-Received: by 2002:a17:902:eac2:b0:1e2:9ddc:f620 with SMTP id p2-20020a170902eac200b001e29ddcf620mr7808pld.23.1712131539180; Wed, 03 Apr 2024 01:05:39 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:38 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 13/22] RISC-V: KVM: Add perf sampling support for guests Date: Wed, 3 Apr 2024 01:04:42 -0700 Message-Id: <20240403080452.1007601-14-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" KVM enables perf for guest via counter virtualization. However, the sampling can not be supported as there is no mechanism to enabled trap/emulate scountovf in ISA yet. Rely on the SBI PMU snapshot to provide the counter overflow data via the shared memory. In case of sampling event, the host first sets the guest's LCOFI interrupt and injects to the guest via irq filtering mechanism defined in AIA specification. Thus, ssaia must be enabled in the host in order to use perf sampling in the guest. No other AIA dependency w.r.t kernel is required. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/include/asm/csr.h | 3 +- arch/riscv/include/asm/kvm_vcpu_pmu.h | 3 ++ arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/aia.c | 5 ++ arch/riscv/kvm/vcpu.c | 15 ++++-- arch/riscv/kvm/vcpu_onereg.c | 5 ++ arch/riscv/kvm/vcpu_pmu.c | 68 +++++++++++++++++++++++++-- 7 files changed, 92 insertions(+), 8 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 9d1b07932794..25966995da04 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -168,7 +168,8 @@ #define VSIP_TO_HVIP_SHIFT (IRQ_VS_SOFT - IRQ_S_SOFT) #define VSIP_VALID_MASK ((_AC(1, UL) << IRQ_S_SOFT) | \ (_AC(1, UL) << IRQ_S_TIMER) | \ - (_AC(1, UL) << IRQ_S_EXT)) + (_AC(1, UL) << IRQ_S_EXT) | \ + (_AC(1, UL) << IRQ_PMU_OVF)) =20 /* AIA CSR bits */ #define TOPI_IID_SHIFT 16 diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm= /kvm_vcpu_pmu.h index 77a1fc4d203d..257f17641e00 100644 --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -36,6 +36,7 @@ struct kvm_pmc { bool started; /* Monitoring event ID */ unsigned long event_idx; + struct kvm_vcpu *vcpu; }; =20 /* PMU data structure per vcpu */ @@ -50,6 +51,8 @@ struct kvm_pmu { bool init_done; /* Bit map of all the virtual counter used */ DECLARE_BITMAP(pmc_in_use, RISCV_KVM_MAX_COUNTERS); + /* Bit map of all the virtual counter overflown */ + DECLARE_BITMAP(pmc_overflown, RISCV_KVM_MAX_COUNTERS); /* The address of the counter snapshot area (guest physical address) */ gpa_t snapshot_addr; /* The actual data of the snapshot */ diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index b1c503c2959c..e878e7cc3978 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -167,6 +167,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZFA, KVM_RISCV_ISA_EXT_ZTSO, KVM_RISCV_ISA_EXT_ZACAS, + KVM_RISCV_ISA_EXT_SSCOFPMF, KVM_RISCV_ISA_EXT_MAX, }; =20 diff --git a/arch/riscv/kvm/aia.c b/arch/riscv/kvm/aia.c index a944294f6f23..0f0a9d11bb5f 100644 --- a/arch/riscv/kvm/aia.c +++ b/arch/riscv/kvm/aia.c @@ -545,6 +545,9 @@ void kvm_riscv_aia_enable(void) enable_percpu_irq(hgei_parent_irq, irq_get_trigger_type(hgei_parent_irq)); csr_set(CSR_HIE, BIT(IRQ_S_GEXT)); + /* Enable IRQ filtering for overflow interrupt only if sscofpmf is presen= t */ + if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSCOFPMF)) + csr_write(CSR_HVIEN, BIT(IRQ_PMU_OVF)); } =20 void kvm_riscv_aia_disable(void) @@ -558,6 +561,8 @@ void kvm_riscv_aia_disable(void) return; hgctrl =3D get_cpu_ptr(&aia_hgei); =20 + if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSCOFPMF)) + csr_clear(CSR_HVIEN, BIT(IRQ_PMU_OVF)); /* Disable per-CPU SGEI interrupt */ csr_clear(CSR_HIE, BIT(IRQ_S_GEXT)); disable_percpu_irq(hgei_parent_irq); diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index b5ca9f2e98ac..bb10771b2b18 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -365,6 +365,13 @@ void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *v= cpu) } } =20 + /* Sync up the HVIP.LCOFIP bit changes (only clear) by the guest */ + if ((csr->hvip ^ hvip) & (1UL << IRQ_PMU_OVF)) { + if (!(hvip & (1UL << IRQ_PMU_OVF)) && + !test_and_set_bit(IRQ_PMU_OVF, v->irqs_pending_mask)) + clear_bit(IRQ_PMU_OVF, v->irqs_pending); + } + /* Sync-up AIA high interrupts */ kvm_riscv_vcpu_aia_sync_interrupts(vcpu); =20 @@ -382,7 +389,8 @@ int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu,= unsigned int irq) if (irq < IRQ_LOCAL_MAX && irq !=3D IRQ_VS_SOFT && irq !=3D IRQ_VS_TIMER && - irq !=3D IRQ_VS_EXT) + irq !=3D IRQ_VS_EXT && + irq !=3D IRQ_PMU_OVF) return -EINVAL; =20 set_bit(irq, vcpu->arch.irqs_pending); @@ -397,14 +405,15 @@ int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcp= u, unsigned int irq) int kvm_riscv_vcpu_unset_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) { /* - * We only allow VS-mode software, timer, and external + * We only allow VS-mode software, timer, counter overflow and external * interrupts when irq is one of the local interrupts * defined by RISC-V privilege specification. */ if (irq < IRQ_LOCAL_MAX && irq !=3D IRQ_VS_SOFT && irq !=3D IRQ_VS_TIMER && - irq !=3D IRQ_VS_EXT) + irq !=3D IRQ_VS_EXT && + irq !=3D IRQ_PMU_OVF) return -EINVAL; =20 clear_bit(irq, vcpu->arch.irqs_pending); diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index f4a6124d25c9..4da4ed899104 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -36,6 +36,7 @@ static const unsigned long kvm_isa_ext_arr[] =3D { /* Multi letter extensions (alphabetically sorted) */ KVM_ISA_EXT_ARR(SMSTATEEN), KVM_ISA_EXT_ARR(SSAIA), + KVM_ISA_EXT_ARR(SSCOFPMF), KVM_ISA_EXT_ARR(SSTC), KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), @@ -101,6 +102,9 @@ static bool kvm_riscv_vcpu_isa_enable_allowed(unsigned = long ext) return false; case KVM_RISCV_ISA_EXT_V: return riscv_v_vstate_ctrl_user_allowed(); + case KVM_RISCV_ISA_EXT_SSCOFPMF: + /* Sscofpmf depends on interrupt filtering defined in ssaia */ + return __riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSAIA); default: break; } @@ -116,6 +120,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned= long ext) case KVM_RISCV_ISA_EXT_C: case KVM_RISCV_ISA_EXT_I: case KVM_RISCV_ISA_EXT_M: + case KVM_RISCV_ISA_EXT_SSCOFPMF: case KVM_RISCV_ISA_EXT_SSTC: case KVM_RISCV_ISA_EXT_SVINVAL: case KVM_RISCV_ISA_EXT_SVNAPOT: diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index f706c688b338..9fedf9dc498b 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -230,6 +230,47 @@ static int kvm_pmu_validate_counter_mask(struct kvm_pm= u *kvpmu, unsigned long ct return 0; } =20 +static void kvm_riscv_pmu_overflow(struct perf_event *perf_event, + struct perf_sample_data *data, + struct pt_regs *regs) +{ + struct kvm_pmc *pmc =3D perf_event->overflow_handler_context; + struct kvm_vcpu *vcpu =3D pmc->vcpu; + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + struct riscv_pmu *rpmu =3D to_riscv_pmu(perf_event->pmu); + u64 period; + + /* + * Stop the event counting by directly accessing the perf_event. + * Otherwise, this needs to deferred via a workqueue. + * That will introduce skew in the counter value because the actual + * physical counter would start after returning from this function. + * It will be stopped again once the workqueue is scheduled + */ + rpmu->pmu.stop(perf_event, PERF_EF_UPDATE); + + /* + * The hw counter would start automatically when this function returns. + * Thus, the host may continue to interrupt and inject it to the guest + * even without the guest configuring the next event. Depending on the ha= rdware + * the host may have some sluggishness only if privilege mode filtering i= s not + * available. In an ideal world, where qemu is not the only capable hardw= are, + * this can be removed. + * FYI: ARM64 does this way while x86 doesn't do anything as such. + * TODO: Should we keep it for RISC-V ? + */ + period =3D -(local64_read(&perf_event->count)); + + local64_set(&perf_event->hw.period_left, 0); + perf_event->attr.sample_period =3D period; + perf_event->hw.sample_period =3D period; + + set_bit(pmc->idx, kvpmu->pmc_overflown); + kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_PMU_OVF); + + rpmu->pmu.start(perf_event, PERF_EF_RELOAD); +} + static long kvm_pmu_create_perf_event(struct kvm_pmc *pmc, struct perf_eve= nt_attr *attr, unsigned long flags, unsigned long eidx, unsigned long evtdata) @@ -249,7 +290,7 @@ static long kvm_pmu_create_perf_event(struct kvm_pmc *p= mc, struct perf_event_att */ attr->sample_period =3D kvm_pmu_get_sample_period(pmc); =20 - event =3D perf_event_create_kernel_counter(attr, -1, current, NULL, pmc); + event =3D perf_event_create_kernel_counter(attr, -1, current, kvm_riscv_p= mu_overflow, pmc); if (IS_ERR(event)) { pr_err("kvm pmu event creation failed for eidx %lx: %ld\n", eidx, PTR_ER= R(event)); return PTR_ERR(event); @@ -443,6 +484,8 @@ int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcpu,= unsigned long ctr_base, pmc_index =3D i + ctr_base; if (!test_bit(pmc_index, kvpmu->pmc_in_use)) continue; + /* The guest started the counter again. Reset the overflow status */ + clear_bit(pmc_index, kvpmu->pmc_overflown); pmc =3D &kvpmu->pmc[pmc_index]; if (flags & SBI_PMU_START_FLAG_SET_INIT_VALUE) { pmc->counter_val =3D ival; @@ -546,7 +589,13 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu,= unsigned long ctr_base, else if (pmc->perf_event) pmc->counter_val +=3D perf_event_read_value(pmc->perf_event, &enabled, &running); - /* TODO: Add counter overflow support when sscofpmf support is added */ + /* + * The counter and overflow indicies in the snapshot region are w.r.to + * cbase. Modify the set bit in the counter mask instead of the pmc_ind= ex + * which indicates the absolute counter index. + */ + if (test_bit(pmc_index, kvpmu->pmc_overflown)) + kvpmu->sdata->ctr_overflow_mask |=3D BIT(i); kvpmu->sdata->ctr_values[i] =3D pmc->counter_val; shmem_needs_update =3D true; } @@ -554,6 +603,15 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu,= unsigned long ctr_base, if (flags & SBI_PMU_STOP_FLAG_RESET) { pmc->event_idx =3D SBI_PMU_EVENT_IDX_INVALID; clear_bit(pmc_index, kvpmu->pmc_in_use); + clear_bit(pmc_index, kvpmu->pmc_overflown); + if (snap_flag_set) { + /* + * Only clear the given counter as the caller is responsible to + * validate both the overflow mask and configured counters. + */ + kvpmu->sdata->ctr_overflow_mask &=3D ~BIT(i); + shmem_needs_update =3D true; + } } } =20 @@ -703,6 +761,7 @@ void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) pmc =3D &kvpmu->pmc[i]; pmc->idx =3D i; pmc->event_idx =3D SBI_PMU_EVENT_IDX_INVALID; + pmc->vcpu =3D vcpu; if (i < kvpmu->num_hw_ctrs) { pmc->cinfo.type =3D SBI_PMU_CTR_TYPE_HW; if (i < 3) @@ -735,13 +794,14 @@ void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu) if (!kvpmu) return; =20 - for_each_set_bit(i, kvpmu->pmc_in_use, RISCV_MAX_COUNTERS) { + for_each_set_bit(i, kvpmu->pmc_in_use, RISCV_KVM_MAX_COUNTERS) { pmc =3D &kvpmu->pmc[i]; pmc->counter_val =3D 0; kvm_pmu_release_perf_event(pmc); pmc->event_idx =3D SBI_PMU_EVENT_IDX_INVALID; } - bitmap_zero(kvpmu->pmc_in_use, RISCV_MAX_COUNTERS); + bitmap_zero(kvpmu->pmc_in_use, RISCV_KVM_MAX_COUNTERS); + bitmap_zero(kvpmu->pmc_overflown, RISCV_KVM_MAX_COUNTERS); memset(&kvpmu->fw_event, 0, SBI_PMU_FW_MAX * sizeof(struct kvm_fw_event)); kvm_pmu_clear_snapshot_area(vcpu); } --=20 2.34.1 From nobody Mon Feb 9 08:54:35 2026 Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 907DA126F1D for ; Wed, 3 Apr 2024 08:05:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131544; cv=none; b=o6I2cRfwo9lNYjjFF85O3cT8fs8winZ4+F6NHV/0VJqUxE2bIMM1E4PkDIFuqsy1/6bq+1iSdMxp0MU1A3rCkC7ZLkbY7f543vMWjJuINvjtvE9JLXNrfiTXAg2QrT7fLmAELNSq6JneVIbhEGGY3RVrPn3b4koh1rK8fXJa+Uo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131544; c=relaxed/simple; bh=Ior8j+spd+ufLG6mBQquUh2m0UyxRYdYbbEmV926TsE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=gG8NGVa7nD02+mLMfiud9DkZtd8qxq8oxu5rRDKQfOKnsIdIxU3R9vAY+FP7GDb1gH4I9oGsr77d6faeA9V9iW9keSFFivXI4Y0XnqlPEm1BoGvx3QHCMSDxrf+/j+BgiSTO5Kd98HtMjp8aug/JdL5+7RmxXz3QhEZ0GxTzLb8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=lhCg01NT; arc=none smtp.client-ip=209.85.210.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="lhCg01NT" Received: by mail-pf1-f172.google.com with SMTP id d2e1a72fcca58-6e7425a6714so4993786b3a.0 for ; Wed, 03 Apr 2024 01:05:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131541; x=1712736341; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aZ3FkBLSpZeB7lcfW0sTr11VliYr1a02KCqdXY16nx8=; b=lhCg01NTubP1BsDjeFac+bgLlEIzQPTwWTBdI8iK75gfmX1v3OaSSusTEOAHZcqGc3 fGRbV54BYSgYXAakdVppIAmKf+W+IIigd9t73qQovGR+/KmcWJMEMNLYppEOVgDfZSrq 4LhdrnSlXHh/lF1/pnM0QXpGKxeSY00o6VHX+eOKWrOAUroQlno7aGjcX5xiKDnnDnIF ASE49cneT0LZHzPVFpfnwN9vcr4xpEZ2pXTj0HUtAbkdrw48O0i1DpzAB8PwQucwCUb+ OQsAwyN5Asb99VX/hnEDGE04CVF0AzWggq2omoxVbBKGQhy7R/zQ9YDyTG7qGHDq4rUV C8Ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131541; x=1712736341; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aZ3FkBLSpZeB7lcfW0sTr11VliYr1a02KCqdXY16nx8=; b=h4XpJ/+g4FQuVcrz9LNzlq13Vyjzudzh9dMOKsDwJC4gb+D0FXbP2oTN9Vw36Vm+B4 SXdLyW28adUsUNHfBQqKhxev/4jjUnM+QmPh7Yk4AP2kDYAr+w/69KH0QcllV/fx/zH1 giSeqzuGwVzRCfO/6tFSfTY0+uJi3LsdbVq0XzaSAMlTma4GCF7AmCCL9Oyf8w5zpb7A +UtkYsrm6nXJfAQ6Nb6BKqr1blGUJ9LmEh6W/qBDB0AAta4aIxnDE3Q+qHCoQ49e0lZM jvUvpUaZJApAlkUoGr2+3oJ8sAJbVcWqErEsNIa/Rc4uMwnhmkRytE9/DPpybRFmgg9D q73A== X-Gm-Message-State: AOJu0YwhQ+49dL4e+pUr3Z7Y5fT8lQASRRQ+lrdgSRh2I83oc98mxG17 eTcybB/HlJ0IwaKy0ER2mD+Eb+TQdD+29hyYuAb8G6mAbwoImzOnoLrQobDFK/vns0yptJChc0s x X-Google-Smtp-Source: AGHT+IEAq+anA/aMtiO8arRrh2Jnm92J1PBH5kUlEvdhS5op/jw7hZzAqhRtuwLXN5Zk3guWOTaagw== X-Received: by 2002:a05:6a20:9e4c:b0:1a3:ca3c:c62b with SMTP id mt12-20020a056a209e4c00b001a3ca3cc62bmr17369882pzb.19.1712131541148; Wed, 03 Apr 2024 01:05:41 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:40 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 14/22] RISC-V: KVM: Support 64 bit firmware counters on RV32 Date: Wed, 3 Apr 2024 01:04:43 -0700 Message-Id: <20240403080452.1007601-15-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SBI v2.0 introduced a fw_read_hi function to read 64 bit firmware counters for RV32 based systems. Add infrastructure to support that. Reviewed-by: Anup Patel Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 4 ++- arch/riscv/kvm/vcpu_pmu.c | 44 ++++++++++++++++++++++++++- arch/riscv/kvm/vcpu_sbi_pmu.c | 6 ++++ 3 files changed, 52 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm= /kvm_vcpu_pmu.h index 257f17641e00..55861b5d3382 100644 --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -20,7 +20,7 @@ static_assert(RISCV_KVM_MAX_COUNTERS <=3D 64); =20 struct kvm_fw_event { /* Current value of the event */ - unsigned long value; + u64 value; =20 /* Event monitoring status */ bool started; @@ -91,6 +91,8 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcp= u, unsigned long ctr_ba struct kvm_vcpu_sbi_return *retdata); int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, struct kvm_vcpu_sbi_return *retdata); +int kvm_riscv_vcpu_pmu_fw_ctr_read_hi(struct kvm_vcpu *vcpu, unsigned long= cidx, + struct kvm_vcpu_sbi_return *retdata); void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu); int kvm_riscv_vcpu_pmu_snapshot_set_shmem(struct kvm_vcpu *vcpu, unsigned = long saddr_low, unsigned long saddr_high, unsigned long flags, diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index 9fedf9dc498b..ff326152eeff 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -197,6 +197,36 @@ static int pmu_get_pmc_index(struct kvm_pmu *pmu, unsi= gned long eidx, return kvm_pmu_get_programmable_pmc_index(pmu, eidx, cbase, cmask); } =20 +static int pmu_fw_ctr_read_hi(struct kvm_vcpu *vcpu, unsigned long cidx, + unsigned long *out_val) +{ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + struct kvm_pmc *pmc; + int fevent_code; + + if (!IS_ENABLED(CONFIG_32BIT)) { + pr_warn("%s: should be invoked for only RV32\n", __func__); + return -EINVAL; + } + + if (cidx >=3D kvm_pmu_num_counters(kvpmu) || cidx =3D=3D 1) { + pr_warn("Invalid counter id [%ld]during read\n", cidx); + return -EINVAL; + } + + pmc =3D &kvpmu->pmc[cidx]; + + if (pmc->cinfo.type !=3D SBI_PMU_CTR_TYPE_FW) + return -EINVAL; + + fevent_code =3D get_event_code(pmc->event_idx); + pmc->counter_val =3D kvpmu->fw_event[fevent_code].value; + + *out_val =3D pmc->counter_val >> 32; + + return 0; +} + static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, unsigned long *out_val) { @@ -705,6 +735,18 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *= vcpu, unsigned long ctr_ba return 0; } =20 +int kvm_riscv_vcpu_pmu_fw_ctr_read_hi(struct kvm_vcpu *vcpu, unsigned long= cidx, + struct kvm_vcpu_sbi_return *retdata) +{ + int ret; + + ret =3D pmu_fw_ctr_read_hi(vcpu, cidx, &retdata->out_val); + if (ret =3D=3D -EINVAL) + retdata->err_val =3D SBI_ERR_INVALID_PARAM; + + return 0; +} + int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, struct kvm_vcpu_sbi_return *retdata) { @@ -778,7 +820,7 @@ void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) pmc->cinfo.csr =3D CSR_CYCLE + i; } else { pmc->cinfo.type =3D SBI_PMU_CTR_TYPE_FW; - pmc->cinfo.width =3D BITS_PER_LONG - 1; + pmc->cinfo.width =3D 63; } } =20 diff --git a/arch/riscv/kvm/vcpu_sbi_pmu.c b/arch/riscv/kvm/vcpu_sbi_pmu.c index d3e7625fb2d2..cf111de51bdb 100644 --- a/arch/riscv/kvm/vcpu_sbi_pmu.c +++ b/arch/riscv/kvm/vcpu_sbi_pmu.c @@ -64,6 +64,12 @@ static int kvm_sbi_ext_pmu_handler(struct kvm_vcpu *vcpu= , struct kvm_run *run, case SBI_EXT_PMU_COUNTER_FW_READ: ret =3D kvm_riscv_vcpu_pmu_ctr_read(vcpu, cp->a0, retdata); break; + case SBI_EXT_PMU_COUNTER_FW_READ_HI: + if (IS_ENABLED(CONFIG_32BIT)) + ret =3D kvm_riscv_vcpu_pmu_fw_ctr_read_hi(vcpu, cp->a0, retdata); + else + retdata->out_val =3D 0; + break; case SBI_EXT_PMU_SNAPSHOT_SET_SHMEM: ret =3D kvm_riscv_vcpu_pmu_snapshot_set_shmem(vcpu, cp->a0, cp->a1, cp->= a2, retdata); break; --=20 2.34.1 From nobody Mon Feb 9 08:54:35 2026 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01A2F127B45 for ; Wed, 3 Apr 2024 08:05:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131545; cv=none; b=sy7/UPT5Tl/6m+A2FOQW0sdK7pIRbB/+AKPHfH8Tl39tgxVWJ7fO8dDbM74FpHycLY+1cDatYYZN+rz2yriNCSN5llBSltZbs1UUdFvOPJ/auuXS2VCNMyJbWeu2K8o7ICHpPVNQQ8ywcCOZNdaVvRp0WMLKb+EgA1ZzjpFycPI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131545; c=relaxed/simple; bh=bM8YEfWLGTqv0xxOOBxSCTgoJM3x8dV7ewXvwA2n16I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Gsyfui+Kx9oGf4sYWaCYlUird9U4DyUoCvEq86PXM4+C31ORvLwfkF1LkeTX/z9LfcWwChOu9yIgGQLDQ9opOnYOmuUpDBg8H+GoMjacBBzlnA/1Bxq3+NAuwh/GiraJZpWyOnhUN6QVurZ2hj6kyVOhJ/k72dbwiX3my0bAVzk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=FG6TLL8M; arc=none smtp.client-ip=209.85.214.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="FG6TLL8M" Received: by mail-pl1-f181.google.com with SMTP id d9443c01a7336-1e0fa980d55so49276705ad.3 for ; Wed, 03 Apr 2024 01:05:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131543; x=1712736343; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qwALXHKqCD9Iy5mIzImMbfILjpXmZkM44DIWXWIBe7w=; b=FG6TLL8M8EddF7b09NZAX4sghUKreVKn+OQPBt7iN4Urg/HX4tg7ZfI3vS1yCepBfh 1VMwqZ1OmCtwoW8b4W7mS7bPbpRKXQ/c6Z34MRqmhhyHGh1cmZSzc0k0OQZ3U3t7vaui SKc5CjnFciPh5SMKULT1b2KTH8BJ1SM8JCG1BYTv3hv04416kzHVzwoMlNciH0Ku36M+ dNdHBG2945liMqBBaxxSYhdItRZekvRekwPA4vdlKDQyoBUfKn+HjvliTjvsXSeQh5ka LkbfgJPMLXchVezjz5n5hHrW5XNaXkdjznqFKXhJ4+kUWi3fuN76+kwpXnIcHvbd6qf3 Po6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131543; x=1712736343; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qwALXHKqCD9Iy5mIzImMbfILjpXmZkM44DIWXWIBe7w=; b=IwayJ1GZEsQu4lsgfqlUrgKF/OW0wC5sWtva7boul1QLwRI/Ex/fXHL7R7icMsssDy R5Ijyo7FFOuPCdFtFtqMK+qsoqdCMFAlgPF/zjOsr9FgzPEoV17ZhuLB3Yh2X6G+NA8/ kTvIVTzdL4xp7AysxtVrGBnPoSIInKZuGVfGDoRA/t93gN4JdZACdmZWSFUmC7CuSG5D jZq4UgQ6Vby0LJA16vQUAoACn7QgTCxPqwVtv7eu+fB23cC60ykRzlURpkeJEDs52u1J 2maVVaGaGaCVzZDeayo9NIcseD7d6P0oCgOjL1mw31HACzGQUA+BqRWtnGEqs8aS8AXo Qsrw== X-Gm-Message-State: AOJu0YwjMLRwQIGAADdDdIj2XWS+cDiqHNKk3DhtTkd10sURBQT/WVIq 2McW4wm/JCdI1v572pnT2SuFwy4Txb+BJyoIFqCfRwQT5Zq6AtVIAREm8Urx1el51l+AjwJdp2s E X-Google-Smtp-Source: AGHT+IFqbJuXOQnG+Kx5BB+hJvgv/ZybZvtn14tS9BuaWyH/U/F2Vi2RSE0rwqy3IKMxLYQ7u8QtTQ== X-Received: by 2002:a17:903:2283:b0:1e0:b60e:1a33 with SMTP id b3-20020a170903228300b001e0b60e1a33mr2264737plh.31.1712131543069; Wed, 03 Apr 2024 01:05:43 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:42 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Anup Patel , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 15/22] RISC-V: KVM: Improve firmware counter read function Date: Wed, 3 Apr 2024 01:04:44 -0700 Message-Id: <20240403080452.1007601-16-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename the function to indicate that it is meant for firmware counter read. While at it, add a range sanity check for it as well. Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 2 +- arch/riscv/kvm/vcpu_pmu.c | 7 ++++++- arch/riscv/kvm/vcpu_sbi_pmu.c | 2 +- 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm= /kvm_vcpu_pmu.h index 55861b5d3382..fa0f535bbbf0 100644 --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -89,7 +89,7 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcp= u, unsigned long ctr_ba unsigned long ctr_mask, unsigned long flags, unsigned long eidx, u64 evtdata, struct kvm_vcpu_sbi_return *retdata); -int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, +int kvm_riscv_vcpu_pmu_fw_ctr_read(struct kvm_vcpu *vcpu, unsigned long ci= dx, struct kvm_vcpu_sbi_return *retdata); int kvm_riscv_vcpu_pmu_fw_ctr_read_hi(struct kvm_vcpu *vcpu, unsigned long= cidx, struct kvm_vcpu_sbi_return *retdata); diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index ff326152eeff..94efa88d054d 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -235,6 +235,11 @@ static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsigne= d long cidx, u64 enabled, running; int fevent_code; =20 + if (cidx >=3D kvm_pmu_num_counters(kvpmu) || cidx =3D=3D 1) { + pr_warn("Invalid counter id [%ld] during read\n", cidx); + return -EINVAL; + } + pmc =3D &kvpmu->pmc[cidx]; =20 if (pmc->cinfo.type =3D=3D SBI_PMU_CTR_TYPE_FW) { @@ -747,7 +752,7 @@ int kvm_riscv_vcpu_pmu_fw_ctr_read_hi(struct kvm_vcpu *= vcpu, unsigned long cidx, return 0; } =20 -int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, +int kvm_riscv_vcpu_pmu_fw_ctr_read(struct kvm_vcpu *vcpu, unsigned long ci= dx, struct kvm_vcpu_sbi_return *retdata) { int ret; diff --git a/arch/riscv/kvm/vcpu_sbi_pmu.c b/arch/riscv/kvm/vcpu_sbi_pmu.c index cf111de51bdb..e4be34e03e83 100644 --- a/arch/riscv/kvm/vcpu_sbi_pmu.c +++ b/arch/riscv/kvm/vcpu_sbi_pmu.c @@ -62,7 +62,7 @@ static int kvm_sbi_ext_pmu_handler(struct kvm_vcpu *vcpu,= struct kvm_run *run, ret =3D kvm_riscv_vcpu_pmu_ctr_stop(vcpu, cp->a0, cp->a1, cp->a2, retdat= a); break; case SBI_EXT_PMU_COUNTER_FW_READ: - ret =3D kvm_riscv_vcpu_pmu_ctr_read(vcpu, cp->a0, retdata); + ret =3D kvm_riscv_vcpu_pmu_fw_ctr_read(vcpu, cp->a0, retdata); break; case SBI_EXT_PMU_COUNTER_FW_READ_HI: if (IS_ENABLED(CONFIG_32BIT)) --=20 2.34.1 From nobody Mon Feb 9 08:54:35 2026 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EFA70129A66 for ; Wed, 3 Apr 2024 08:05:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131547; cv=none; b=CYerQxKmMuRZEidOaRuwh2BnVHFRfANhuyRE/zJjoYzd8H2Z2rrFZ37lxHVXf9eyZjYSW22lX3fEq2lIiW89mLO5v1Hoq+XXSqfI6uTE1Qj4A0A08e5UziL+sQkkjAB7H1a74Tv5Us1RpINmdHb33TzSO6pl6EJiv5FkfwJaOb8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131547; c=relaxed/simple; bh=BAJjj9DUFC41oCUghV1zdmiJwIpGKHSqJMMsbfwWnaA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Npl9txjz11n4qW5jxa62Pq4mdB2zzomQx3z16nsRemA1yIz9fglz02nfBh9YwjqLgzqrtuB03wgrrLfYWb62q9Rqk4a3/Ydx2/FMFmnJ9DAFiM1lvy0LP/s7lyOfOgH0IYHJ14qqllxj2LIAsACyFHO0paxJDCLsYhACKw7Uufk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=GjXjuL1Z; arc=none smtp.client-ip=209.85.214.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="GjXjuL1Z" Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-1e223025ccbso26998925ad.3 for ; Wed, 03 Apr 2024 01:05:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131545; x=1712736345; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UKKIkxhVPzlR31GWSQWSWFD216hXiUzA8utaOE+u8sQ=; b=GjXjuL1Zw90DuXBP2Bwb4uoBEPovPetVR1iMXta2j104mzYBQTmzanz18Wt7KN1lIS GeGuqOeDXqAd8PK4vdYDXbBDqYcxbe0XWickXEaGGn/o6UShGJ7W+/EoZvf9YYGw3+eA lYy0CC+e5bcZXE+hzDrE6rCIAW9/Jv0kDAHUbPMy3MvbV3vEtwou0fb4kUF0YtaH2Cv5 dIA6+P+ZcUNLYdmDYp7qcLbAcsycu3IsVLmM2hKT2Q+0sBb13ONEMEsJ95mX3dQrdz5g OYXoYoqeN405t2KuWrflXkoeB1Akx7mOdV0RrdxZE/fs5LMe9QoWWDtmNWYmVqt0tYZh xFcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131545; x=1712736345; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UKKIkxhVPzlR31GWSQWSWFD216hXiUzA8utaOE+u8sQ=; b=xQ3+Qvndn5UmhinYZeNsufZKtuHa0L+Ct4VNs6TpW7GlZQJDdSwzLmSa13/1RoEWvb 4lt8Y4F8bPA9O5gBfDRoWsHEs3ok91JD/5rc6ARYorAi+d8ZGVModJsxM1uQMs6p12vQ 1BK4xXIybZi7jzqErbOEs9g+MEr3F57IflmqAkA1yrfiMiTdlzMv7KBAOFUhB4F2vOhw aUxm2ZYrpVtrDSvj8U32Jx9p1FR+xq4JUbEpomEsXhFgCHF2+tMluaFbdUmAjbaAj+Eo +T70Vv99I+p6DKZgYETY/0f6xQytv61bJ6fBZk4l0RwogjW/liZxmZaQWdupS4dowhUV I/4g== X-Gm-Message-State: AOJu0Yy/xiYdEjdYNC/pnDw4CA0purNWxkn4Jd90L5comG4upc/eZijL w0LENhbiz6LNlVgoDiDKQlGOSxk/ARBcMp59FTcbNOAxVqSNu0bolBJLtbNFZQlmie4cKfbqhq0 F X-Google-Smtp-Source: AGHT+IEHII7tSGtUqO5wpO59JDooIKUZaJc45tvRQjDzAvEN2jSXssf4AqTMGpJ/lHoLRFAsmkx1xA== X-Received: by 2002:a17:902:bf04:b0:1e0:115c:e03c with SMTP id bi4-20020a170902bf0400b001e0115ce03cmr11696876plb.53.1712131545155; Wed, 03 Apr 2024 01:05:45 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:44 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Andrew Jones , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Anup Patel , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 16/22] KVM: riscv: selftests: Move sbi definitions to its own header file Date: Wed, 3 Apr 2024 01:04:45 -0700 Message-Id: <20240403080452.1007601-17-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SBI definitions will continue to grow. Move the sbi related definitions to its own header file from processor.h Suggested-by: Andrew Jones Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- .../selftests/kvm/include/riscv/processor.h | 39 --------------- .../testing/selftests/kvm/include/riscv/sbi.h | 50 +++++++++++++++++++ .../selftests/kvm/include/riscv/ucall.h | 1 + tools/testing/selftests/kvm/steal_time.c | 4 +- 4 files changed, 54 insertions(+), 40 deletions(-) create mode 100644 tools/testing/selftests/kvm/include/riscv/sbi.h diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/= testing/selftests/kvm/include/riscv/processor.h index ce473fe251dd..3b9cb39327ff 100644 --- a/tools/testing/selftests/kvm/include/riscv/processor.h +++ b/tools/testing/selftests/kvm/include/riscv/processor.h @@ -154,45 +154,6 @@ void vm_install_interrupt_handler(struct kvm_vm *vm, e= xception_handler_fn handle #define PGTBL_PAGE_SIZE PGTBL_L0_BLOCK_SIZE #define PGTBL_PAGE_SIZE_SHIFT PGTBL_L0_BLOCK_SHIFT =20 -/* SBI return error codes */ -#define SBI_SUCCESS 0 -#define SBI_ERR_FAILURE -1 -#define SBI_ERR_NOT_SUPPORTED -2 -#define SBI_ERR_INVALID_PARAM -3 -#define SBI_ERR_DENIED -4 -#define SBI_ERR_INVALID_ADDRESS -5 -#define SBI_ERR_ALREADY_AVAILABLE -6 -#define SBI_ERR_ALREADY_STARTED -7 -#define SBI_ERR_ALREADY_STOPPED -8 - -#define SBI_EXT_EXPERIMENTAL_START 0x08000000 -#define SBI_EXT_EXPERIMENTAL_END 0x08FFFFFF - -#define KVM_RISCV_SELFTESTS_SBI_EXT SBI_EXT_EXPERIMENTAL_END -#define KVM_RISCV_SELFTESTS_SBI_UCALL 0 -#define KVM_RISCV_SELFTESTS_SBI_UNEXP 1 - -enum sbi_ext_id { - SBI_EXT_BASE =3D 0x10, - SBI_EXT_STA =3D 0x535441, -}; - -enum sbi_ext_base_fid { - SBI_EXT_BASE_PROBE_EXT =3D 3, -}; - -struct sbiret { - long error; - long value; -}; - -struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, - unsigned long arg1, unsigned long arg2, - unsigned long arg3, unsigned long arg4, - unsigned long arg5); - -bool guest_sbi_probe_extension(int extid, long *out_val); - static inline void local_irq_enable(void) { csr_set(CSR_SSTATUS, SR_SIE); diff --git a/tools/testing/selftests/kvm/include/riscv/sbi.h b/tools/testin= g/selftests/kvm/include/riscv/sbi.h new file mode 100644 index 000000000000..ba04f2dec7b5 --- /dev/null +++ b/tools/testing/selftests/kvm/include/riscv/sbi.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * RISC-V SBI specific definitions + * + * Copyright (C) 2024 Rivos Inc. + */ + +#ifndef SELFTEST_KVM_SBI_H +#define SELFTEST_KVM_SBI_H + +/* SBI return error codes */ +#define SBI_SUCCESS 0 +#define SBI_ERR_FAILURE -1 +#define SBI_ERR_NOT_SUPPORTED -2 +#define SBI_ERR_INVALID_PARAM -3 +#define SBI_ERR_DENIED -4 +#define SBI_ERR_INVALID_ADDRESS -5 +#define SBI_ERR_ALREADY_AVAILABLE -6 +#define SBI_ERR_ALREADY_STARTED -7 +#define SBI_ERR_ALREADY_STOPPED -8 + +#define SBI_EXT_EXPERIMENTAL_START 0x08000000 +#define SBI_EXT_EXPERIMENTAL_END 0x08FFFFFF + +#define KVM_RISCV_SELFTESTS_SBI_EXT SBI_EXT_EXPERIMENTAL_END +#define KVM_RISCV_SELFTESTS_SBI_UCALL 0 +#define KVM_RISCV_SELFTESTS_SBI_UNEXP 1 + +enum sbi_ext_id { + SBI_EXT_BASE =3D 0x10, + SBI_EXT_STA =3D 0x535441, +}; + +enum sbi_ext_base_fid { + SBI_EXT_BASE_PROBE_EXT =3D 3, +}; + +struct sbiret { + long error; + long value; +}; + +struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, + unsigned long arg1, unsigned long arg2, + unsigned long arg3, unsigned long arg4, + unsigned long arg5); + +bool guest_sbi_probe_extension(int extid, long *out_val); + +#endif /* SELFTEST_KVM_SBI_H */ diff --git a/tools/testing/selftests/kvm/include/riscv/ucall.h b/tools/test= ing/selftests/kvm/include/riscv/ucall.h index be46eb32ec27..a695ae36f3e0 100644 --- a/tools/testing/selftests/kvm/include/riscv/ucall.h +++ b/tools/testing/selftests/kvm/include/riscv/ucall.h @@ -3,6 +3,7 @@ #define SELFTEST_KVM_UCALL_H =20 #include "processor.h" +#include "sbi.h" =20 #define UCALL_EXIT_REASON KVM_EXIT_RISCV_SBI =20 diff --git a/tools/testing/selftests/kvm/steal_time.c b/tools/testing/selft= ests/kvm/steal_time.c index bae0c5026f82..2ff82c7fd926 100644 --- a/tools/testing/selftests/kvm/steal_time.c +++ b/tools/testing/selftests/kvm/steal_time.c @@ -11,7 +11,9 @@ #include #include #include -#ifndef __riscv +#ifdef __riscv +#include "sbi.h" +#else #include #endif =20 --=20 2.34.1 From nobody Mon Feb 9 08:54:35 2026 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AA1512C80F for ; Wed, 3 Apr 2024 08:05:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131550; cv=none; b=FJpqpKBfUB+JM6j/s4CB8DyvNW2YkNaqsH3GDZoDOXG4M9HEvhehJZtU8h9SEgoTIWbu+WsPzANKK0AaU5PnxDMIgY+zqKn63LTSO6A2ycqx7jL+yK0JiuMhvCqRDw6PNjQoiHXZDjrsvOJXjYr4ssqTMgpZgaMqHmltmbKCydc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131550; c=relaxed/simple; bh=evlE8hTl45MyJIsfxvr/2bRxoIA3bwQv3sS8gzvU/GA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=E8NuH32OI/9ZzKkq067WaKU8s+k1IBY1TBkO/wt8+AShFVrdMBhMV2xhLx/kraMIsGq2X/Vy/oShoVGGzmOWW/CF+1Ij2xT3yUy9MGeF5nGmAugiMoErnckKiZNrFR2SP68mf/fu2miYoZzkMNGbNqebCW7J5Q1LtIZrnrS9+lw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=qrZNpmB4; arc=none smtp.client-ip=209.85.214.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="qrZNpmB4" Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-1e0878b76f3so5697995ad.0 for ; Wed, 03 Apr 2024 01:05:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131548; x=1712736348; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iiceCABnvA1jknfstt9FkxftBmpWokdNdmMlEhNsfyg=; b=qrZNpmB4r8FVIKopd0jjyxjIxIdnf4x4wviyHS9shXYzJV4XaMpmInQsbIFO0XCMSs a94P0h5iGIIKHFlWZf8KtZDQ7MDxG0CWZXXuNBJza2XxApNnP+hdqFwCT5PPtmpZacVH xaHpwZdF2wubbvVBI8C3DKvqXGiDebPLtnMnLF87Q1bguL9C+LQoD3A3Jf73cG03/Cii ymIS0+W90OiS4SjSwbWIaPAl/fSnaNxDPnc1+fQktlJvDTdFukiNMokDb5FHosJBSHmD IH6bQUJ/82pF4J1cLtua3sSMak+Ey9ntxdkVD0kaETrkjaGmUtY0nhukh38YHqeVfUaO GOKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131548; x=1712736348; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iiceCABnvA1jknfstt9FkxftBmpWokdNdmMlEhNsfyg=; b=kudc5E9ipfN9y1W4S0cX/K4xmQOQetV60trQPQ1by92RGKByoeXwDKnqDaCoWVQoPB qcQzR/XqN24SnBf1Uj0fti5898s99zD/I2OLgn7PaXpHW4zk0Ksx462gEcix/GPcnTB2 hByeKbwioU55bmqMZpfS7qe3K2kvJzAh1NLX8HE/wAzdlnJhzLYgwQrqPJhO1JED/mBi jDOno3OxinMRDYdyWva1t7dSF7FNY0VTEmSOSLORGrKP+/zWBlYheUWgyhDB/Zmrb2UA 1tMg2DEBNcTM4s7+TmhLwK7qP97eCPk7XFg3LGYRUO1yFDcAm+MzgxXQVV1vC1lDNDZ2 milg== X-Gm-Message-State: AOJu0YwjQgXjJQfysD3YHicJcYFMJQWLDT/vPQ5EoPk8UFW4/5IESd3X knvIoz8M6WCSQ7n78r9A8H+fiA64gM1IAOMTlOSNR4qP4eQlzJUnnCXiyagilnEFq5uxgTJxXl6 q X-Google-Smtp-Source: AGHT+IEPeMI0z43MjvlBXsAsUdkQGTsWnPaqF+QUoQ1JhMqwDtA7d+BW/HuEGoVFyjEvifPOaGIfHg== X-Received: by 2002:a17:903:181:b0:1e0:e85c:72dc with SMTP id z1-20020a170903018100b001e0e85c72dcmr2464037plg.19.1712131548509; Wed, 03 Apr 2024 01:05:48 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:46 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Anup Patel , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 17/22] KVM: riscv: selftests: Add helper functions for extension checks Date: Wed, 3 Apr 2024 01:04:46 -0700 Message-Id: <20240403080452.1007601-18-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" __vcpu_has_ext can check both SBI and ISA extensions when the first argument is properly converted to SBI/ISA extension IDs. Introduce two helper functions to make life easier for developers so they don't have to worry about the conversions. Replace the current usages as well with new helpers. Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- tools/testing/selftests/kvm/include/riscv/processor.h | 10 ++++++++++ tools/testing/selftests/kvm/riscv/arch_timer.c | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/= testing/selftests/kvm/include/riscv/processor.h index 3b9cb39327ff..5f389166338c 100644 --- a/tools/testing/selftests/kvm/include/riscv/processor.h +++ b/tools/testing/selftests/kvm/include/riscv/processor.h @@ -50,6 +50,16 @@ static inline uint64_t __kvm_reg_id(uint64_t type, uint6= 4_t subtype, =20 bool __vcpu_has_ext(struct kvm_vcpu *vcpu, uint64_t ext); =20 +static inline bool __vcpu_has_isa_ext(struct kvm_vcpu *vcpu, uint64_t isa_= ext) +{ + return __vcpu_has_ext(vcpu, RISCV_ISA_EXT_REG(isa_ext)); +} + +static inline bool __vcpu_has_sbi_ext(struct kvm_vcpu *vcpu, uint64_t sbi_= ext) +{ + return __vcpu_has_ext(vcpu, RISCV_SBI_EXT_REG(sbi_ext)); +} + struct ex_regs { unsigned long ra; unsigned long sp; diff --git a/tools/testing/selftests/kvm/riscv/arch_timer.c b/tools/testing= /selftests/kvm/riscv/arch_timer.c index e22848f747c0..6a3e97ead824 100644 --- a/tools/testing/selftests/kvm/riscv/arch_timer.c +++ b/tools/testing/selftests/kvm/riscv/arch_timer.c @@ -85,7 +85,7 @@ struct kvm_vm *test_vm_create(void) int nr_vcpus =3D test_args.nr_vcpus; =20 vm =3D vm_create_with_vcpus(nr_vcpus, guest_code, vcpus); - __TEST_REQUIRE(__vcpu_has_ext(vcpus[0], RISCV_ISA_EXT_REG(KVM_RISCV_ISA_E= XT_SSTC)), + __TEST_REQUIRE(__vcpu_has_isa_ext(vcpus[0], KVM_RISCV_ISA_EXT_SSTC), "SSTC not available, skipping test\n"); =20 vm_init_vector_tables(vm); --=20 2.34.1 From nobody Mon Feb 9 08:54:35 2026 Received: from mail-pf1-f173.google.com (mail-pf1-f173.google.com [209.85.210.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2395212E1D9 for ; Wed, 3 Apr 2024 08:05:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131553; cv=none; b=gX+pnVV8Rkbrj4Wlc4UcDg1wJGoe1AHZsjsZvBXnRm8Lv8VPxlL9t4ab9Q4wOXgr/XwXXwNdx4sIomXbxGfrkeEtbLt+rtoZrGIGceeNKJJlsMCHpoTYoD7eb1vjiGwjSgCYWZsJROm1si0eGYkJALPk9qdD5sgVNFxKEL75cZ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131553; c=relaxed/simple; bh=kGDqdfAz5O6jd2BlwqWEgDKuhCYmFyrLfaexp9eWGuU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RexG/V7putpQtacBwRx4hwMXylKISlHu2HPTRiPFjr8taayQp18g8xmwzu1gE2ajXFi9VHG+XbTEC/V/cAWePTkT2bO2WhRoyITh8qQeeONFmqV0JypRIA2ZMOSnWRKYPTll3559owMSMVq8Iq3Sbb/JR9tCgCmkgUfMdzRTnQw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=LdBw8BgT; arc=none smtp.client-ip=209.85.210.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="LdBw8BgT" Received: by mail-pf1-f173.google.com with SMTP id d2e1a72fcca58-6e88e4c8500so4876936b3a.2 for ; Wed, 03 Apr 2024 01:05:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131551; x=1712736351; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xZMdAGbGUb3Pn/mM6S9aCTNbs+MKWuMa25SVPrHMqxo=; b=LdBw8BgTRjdulDIn7wXB1R3v4x4eUeKxA2/1h6H5IQ+CQtJXt6hGI9JxX/HAEjpnxG w23B6HR/GJcTq73l1YPnHhjE9yLy53uAYy38OuYjRYcSDdwdwZvNnTC2rCo1h0eYGmne uk8cMGJ7AIRMYy/c+NPo07h/6O3MR0hwJK9km43fK3y2qraJxD/oXJiiXT/Zzj/4c2mu vfFpXX5bdl9pgTHK58ZVEme4IBYCj9HYrq8ClK7DImOtOr0QZVKGZwBCaDRWvzKHoAUJ kfFHXh4JO4PWC4v4ncBUa8OamMase3pvhZhR8Lh7ny+mdjHdoYHSya1bzDzf7/v2s3Ze 6Yyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131551; x=1712736351; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xZMdAGbGUb3Pn/mM6S9aCTNbs+MKWuMa25SVPrHMqxo=; b=RQsxwRaAnl0iEXBtmn16mqjNN/bFnpp0AIqFtkP4KQCN2449WeCk37ZR+J/3LL2j9O buAbLH8WaX6gZtULa8QvynutIy0dVTl6jYKL/Ow6lSWz/TsF8T1Wln8+zhfg5KXdJjoA otPWJUCMT6F8sdaoMRHWUvTdLlhiRhZBsUwGHnWLyI5hwKqyiVQIVOAzNDrWGVO+6Xnk IBSxjIsmD/p4KtMoSRnNWRPVhLFdz0X0sTJ/x8ZI/0AIHFwNy8HQ89PJorW6nwBI2XaL QsMTHm0g7s9H3OUOpyChJyn+zJK+pgWsPgUkcNR/TPH3F5noQgyCzhe5QdyPpwpYdSWN C+Ig== X-Gm-Message-State: AOJu0YxnKUpx0ux5hl3VeGdiXvFmyhKUeML7oclHn8bEfMYCIj1Y+tqU zOM1/FPnCEZK2fetwoaDjIvGZKsT7g+QpttIDtdNt/sraiiOFuv/Rc+AiPq9NuT+stwJNULxD3D g X-Google-Smtp-Source: AGHT+IFHku/sICvAenYJFC+cS7PaObyEd64lSbck4sFkQiPnTcMjwhsfqy4pdW/5l9uIy4qG4AZ0Fg== X-Received: by 2002:a05:6a20:94cf:b0:1a7:377:b867 with SMTP id ht15-20020a056a2094cf00b001a70377b867mr11062652pzb.57.1712131551038; Wed, 03 Apr 2024 01:05:51 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:49 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Andrew Jones , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 18/22] KVM: riscv: selftests: Add Sscofpmf to get-reg-list test Date: Wed, 3 Apr 2024 01:04:47 -0700 Message-Id: <20240403080452.1007601-19-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The KVM RISC-V allows Sscofpmf extension for Guest/VM so let us add this extension to get-reg-list test. Reviewed-by: Anup Patel Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testi= ng/selftests/kvm/riscv/get-reg-list.c index b882b7b9b785..222198dd6d04 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -43,6 +43,7 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _V: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SMSTATEEN: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SSAIA: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SSCOFPMF: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SSTC: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SVINVAL: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SVNAPOT: @@ -408,6 +409,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_o= ff) KVM_ISA_EXT_ARR(V), KVM_ISA_EXT_ARR(SMSTATEEN), KVM_ISA_EXT_ARR(SSAIA), + KVM_ISA_EXT_ARR(SSCOFPMF), KVM_ISA_EXT_ARR(SSTC), KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), @@ -931,6 +933,7 @@ KVM_ISA_EXT_SUBLIST_CONFIG(fp_f, FP_F); KVM_ISA_EXT_SUBLIST_CONFIG(fp_d, FP_D); KVM_ISA_EXT_SIMPLE_CONFIG(h, H); KVM_ISA_EXT_SUBLIST_CONFIG(smstateen, SMSTATEEN); +KVM_ISA_EXT_SIMPLE_CONFIG(sscofpmf, SSCOFPMF); KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC); KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL); KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT); @@ -986,6 +989,7 @@ struct vcpu_reg_list *vcpu_configs[] =3D { &config_fp_d, &config_h, &config_smstateen, + &config_sscofpmf, &config_sstc, &config_svinval, &config_svnapot, --=20 2.34.1 From nobody Mon Feb 9 08:54:35 2026 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10EA712FB2B for ; Wed, 3 Apr 2024 08:05:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131556; cv=none; b=Ox++xTgpaOjZMxiEOu2n4pEab+i9zlwzsNleuf37yhZqeNhoZopk6sFMwqV4hRkT2o//C4ujBOAaT6AF+smA5qASW7o0vM5zgNmZU5QGUEeKbs51jsO2dgFJWvXm8ATaR21bZlaeJORsHJjFoipFmRyoyboELEcfgZi9vbq2z2s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131556; c=relaxed/simple; bh=780bxI6naAUr6IQqUhjJBAL1yGnj9U7hJOgqG70RfWQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=twQFdebJct+C//rxsv2tvgYCwwbAjxM85kZDfWgdxNS4uxQWaW2Y0ToPeKKQILhE2Otdw9shQGCV0sP/OitHKCAGG377hGXtORzQjuOS/bfSxpiVKPL7lza6uRfa0bq2fouOs/Ah2lZkS2KHMTdsby86h2OiDV4klr3xUEYSUlw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=dyw6GbFn; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="dyw6GbFn" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-1e0f0398553so54198435ad.3 for ; Wed, 03 Apr 2024 01:05:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131554; x=1712736354; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GkhEh3Kwi0UVSPm+lxEXp9oZg2L7eBy2zYGiPlgLtso=; b=dyw6GbFnCpaATK6fytex7MkAcS1lptmbvXUaUMbUoe9vEhDn+bu5LG2/1i9Jz3OP3J dlQaD+FPXCPjyYwvsKUt6bptozlscgtbcJLlB5Br8nkEcfdZG+W1TREVkASQ/7a6Z2ZP fvmUKrli8p/MJn1Qi/gaxhG3BK7eVs9dMjhGw9Ui+LUFrLpJdX6tDXWia0Xa6fO3yCWp cPZoejXsu9nsk60juTbWuM1RmOR+kglX2E6zDkFjSSh5Op0gqdc+OB2emkhL+OjEgwyC lcTJU4lXypUABPT7Buw/+1FSUFziNKYeFvgXXeXwa+suL2d5cj9aRDzf6peU4oq5y5h5 jnxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131554; x=1712736354; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GkhEh3Kwi0UVSPm+lxEXp9oZg2L7eBy2zYGiPlgLtso=; b=hFg9HopEOzMrkRooPJJK2JyeuuFAfDk+G4Ku0mB3oksMG4Vnu8Iz504FjKqyOQ1RTV z+yu1PZ/QBjt0r7FJG/HX2FIhFA195DwZu4gVBlEo4g8H+m0wuQktysNqdvUaozXHdDJ OlpJjXRP/gmLzoEY0p17Y0EcMJZhemxhwbsSFWxLl1ARBPnlETFSqqH1eLdNh/evm/Bh w2I0gqSiHj0+g5iGhVCCSlLrz1ES2WCZ3Fta2s41ZKzjn5857niWE8bG7bnBCufCP9a6 WDV1aESqdvEnFjScNfFQWCghC6yapiUWyShKB73WMVeTieUZ/unwZFzrT/UXNgJUj09f jIww== X-Gm-Message-State: AOJu0YxreHIpN4IAkkHRhMIo4YDQA8lxtVTN3GIFs8ySqsfox1owRdor Hy1NmqGzGpJPlENpeOLj0JgzUa8y5kbZm4j+2qpXGKvI+x+o5WVove1SWfRg2VyZKr97PZ9Xuxk 5 X-Google-Smtp-Source: AGHT+IHXyVuhd2UN6DaFS3pRiDjXF6BBqw4nhkvMX8+6lolbeavqTSelxKMWeizm1rfTvMdNdGFtWA== X-Received: by 2002:a17:903:292:b0:1e2:6240:72e7 with SMTP id j18-20020a170903029200b001e2624072e7mr5867168plr.53.1712131554171; Wed, 03 Apr 2024 01:05:54 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:52 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 19/22] KVM: riscv: selftests: Add SBI PMU extension definitions Date: Wed, 3 Apr 2024 01:04:48 -0700 Message-Id: <20240403080452.1007601-20-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SBI PMU extension definition is required for upcoming SBI PMU selftests. Reviewed-by: Anup Patel Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- .../testing/selftests/kvm/include/riscv/sbi.h | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/tools/testing/selftests/kvm/include/riscv/sbi.h b/tools/testin= g/selftests/kvm/include/riscv/sbi.h index ba04f2dec7b5..6675ca673c77 100644 --- a/tools/testing/selftests/kvm/include/riscv/sbi.h +++ b/tools/testing/selftests/kvm/include/riscv/sbi.h @@ -29,17 +29,83 @@ enum sbi_ext_id { SBI_EXT_BASE =3D 0x10, SBI_EXT_STA =3D 0x535441, + SBI_EXT_PMU =3D 0x504D55, }; =20 enum sbi_ext_base_fid { SBI_EXT_BASE_PROBE_EXT =3D 3, }; +enum sbi_ext_pmu_fid { + SBI_EXT_PMU_NUM_COUNTERS =3D 0, + SBI_EXT_PMU_COUNTER_GET_INFO, + SBI_EXT_PMU_COUNTER_CFG_MATCH, + SBI_EXT_PMU_COUNTER_START, + SBI_EXT_PMU_COUNTER_STOP, + SBI_EXT_PMU_COUNTER_FW_READ, + SBI_EXT_PMU_COUNTER_FW_READ_HI, + SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, +}; + +union sbi_pmu_ctr_info { + unsigned long value; + struct { + unsigned long csr:12; + unsigned long width:6; +#if __riscv_xlen =3D=3D 32 + unsigned long reserved:13; +#else + unsigned long reserved:45; +#endif + unsigned long type:1; + }; +}; =20 struct sbiret { long error; long value; }; =20 +/** General pmu event codes specified in SBI PMU extension */ +enum sbi_pmu_hw_generic_events_t { + SBI_PMU_HW_NO_EVENT =3D 0, + SBI_PMU_HW_CPU_CYCLES =3D 1, + SBI_PMU_HW_INSTRUCTIONS =3D 2, + SBI_PMU_HW_CACHE_REFERENCES =3D 3, + SBI_PMU_HW_CACHE_MISSES =3D 4, + SBI_PMU_HW_BRANCH_INSTRUCTIONS =3D 5, + SBI_PMU_HW_BRANCH_MISSES =3D 6, + SBI_PMU_HW_BUS_CYCLES =3D 7, + SBI_PMU_HW_STALLED_CYCLES_FRONTEND =3D 8, + SBI_PMU_HW_STALLED_CYCLES_BACKEND =3D 9, + SBI_PMU_HW_REF_CPU_CYCLES =3D 10, + + SBI_PMU_HW_GENERAL_MAX, +}; + +/* SBI PMU counter types */ +enum sbi_pmu_ctr_type { + SBI_PMU_CTR_TYPE_HW =3D 0x0, + SBI_PMU_CTR_TYPE_FW, +}; + +/* Flags defined for config matching function */ +#define SBI_PMU_CFG_FLAG_SKIP_MATCH BIT(0) +#define SBI_PMU_CFG_FLAG_CLEAR_VALUE BIT(1) +#define SBI_PMU_CFG_FLAG_AUTO_START BIT(2) +#define SBI_PMU_CFG_FLAG_SET_VUINH BIT(3) +#define SBI_PMU_CFG_FLAG_SET_VSINH BIT(4) +#define SBI_PMU_CFG_FLAG_SET_UINH BIT(5) +#define SBI_PMU_CFG_FLAG_SET_SINH BIT(6) +#define SBI_PMU_CFG_FLAG_SET_MINH BIT(7) + +/* Flags defined for counter start function */ +#define SBI_PMU_START_FLAG_SET_INIT_VALUE BIT(0) +#define SBI_PMU_START_FLAG_INIT_SNAPSHOT BIT(1) + +/* Flags defined for counter stop function */ +#define SBI_PMU_STOP_FLAG_RESET BIT(0) +#define SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT BIT(1) + struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, unsigned long arg1, unsigned long arg2, unsigned long arg3, unsigned long arg4, --=20 2.34.1 From nobody Mon Feb 9 08:54:35 2026 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34F1313048F for ; Wed, 3 Apr 2024 08:05:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131560; cv=none; b=HIw9wshl8j7kk/18/tFsInpuCet8UBThIlan7S/LoyT6sfbXonfthOb47l5+Cpx5PEuZMVCcMzY17tDgQSRwJVi1fAHLIIR/LVzcH9abao8zLcu4zKl/XM3zcouEbER3utxXGR1v7hT/OluXPTnyrrgp16YC9dsmUgXF1d4kWGM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131560; c=relaxed/simple; bh=N+QErxxX5mOgaKaB2qbACqencWeCdxw78rjj/XkuHww=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PEuMG8gIR9Va19erP8W93kj22ThcLwxGll4dGaZa7nrEovEvtb6nldZagLHPhjITgQGV/Dqr8RKOEe4tQiTfOjh3Vy/0Fl29dNz7lYpT9RfzUsDum/BwiY8woEM8AhvZicsYqKPWvF8MYpl6Hi0IP3BE57icWJkFWmTvoYtNVUg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=UwFA/kPT; arc=none smtp.client-ip=209.85.214.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="UwFA/kPT" Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-1def89f0cfdso5308335ad.0 for ; Wed, 03 Apr 2024 01:05:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131557; x=1712736357; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LCMipi4iMwcecw5jkK7vSbrK4Smr7cw1nRJDkHi5YgY=; b=UwFA/kPT9J3CZiOX6PF8Mu/QMK77dn2B6BEA2wEAjtEGogdqwBr/wiWS33CLMCm4OI 0GcTi3NUlVH5E4eZU6I23PgKIzVmhSxpSLQCWdBjRX6xNKDFyc4/sNa5GPzGsPLfjnQc wF0Bu8rNo+vIJymfLSZl5BGd0wmnZwMLQFslTd0LvGyk1Z9JSBWFgEN8UT/a1i+iC1uc 3aPxfiRitM5wHaANr5m/fyBgag28s1BoCEfigq+4FEBS0uqYTkZVjOhBrOcGkL+E9i6u EHPHxj3BruBDHNZ5GKIs0ucRVoAs09J+cMMNo2TH6gKhPU9onerRX6nnQvCQ/k5zhjSZ x0Qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131557; x=1712736357; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LCMipi4iMwcecw5jkK7vSbrK4Smr7cw1nRJDkHi5YgY=; b=tA1HBw8und9gjdbj6f2y3GF1MHuapfyQ+qLPhXPkYq+dBjYeeQIfr5MJkuy6p/sgMs 0L1TULQXSC/pOnxJZfKvEIrseEjPd6anxsgoZis30xo9/CazkAVBprwegFfmZIm2qNha xtrQnH93On3NOVmjCaiYHVC5erQDOpMKtz1DpskHy7PjlW9HpTx5wCybdZo5cIKjnf3D GPc6q7r0cbr80sRUqODVVg98cy1OCgB+jC1+AcGLz+XsMqyUj9h5MShL0olA2OJuJPAZ sF4AV9UmJ/c7YboLbYUljJVQ4efbVw5MKDjFBYYoFFocEDJLdNFuiPgXuBuKeX3jy+Vr /30A== X-Gm-Message-State: AOJu0YwX8Qv5r8E67Ha661W8IsRSY/whk82sOGnnU+nqUSMKUggPItrS m131B59FTFZPRXtfRc3PXYyST0nolU/7DNDRMr2X9siypFWMl6o6dH/41n7QK/+jtxBFcjk/Kuf m X-Google-Smtp-Source: AGHT+IHpyx5a6XqGmtOIk6bFUng2qDzlcvAJJ7ibWLTxJ0Xo8UDyEPRszXuJnMno9PGr0QMK56dlfw== X-Received: by 2002:a17:902:d4d1:b0:1e0:ab65:85e5 with SMTP id o17-20020a170902d4d100b001e0ab6585e5mr2774053plg.1.1712131556762; Wed, 03 Apr 2024 01:05:56 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:55 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 20/22] KVM: riscv: selftests: Add SBI PMU selftest Date: Wed, 3 Apr 2024 01:04:49 -0700 Message-Id: <20240403080452.1007601-21-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This test implements basic sanity test and cycle/instret event counting tests. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- tools/testing/selftests/kvm/Makefile | 1 + .../selftests/kvm/riscv/sbi_pmu_test.c | 340 ++++++++++++++++++ 2 files changed, 341 insertions(+) create mode 100644 tools/testing/selftests/kvm/riscv/sbi_pmu_test.c diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests= /kvm/Makefile index 741c7dc16afc..1cfcd2797ee4 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -189,6 +189,7 @@ TEST_GEN_PROGS_s390x +=3D rseq_test TEST_GEN_PROGS_s390x +=3D set_memory_region_test TEST_GEN_PROGS_s390x +=3D kvm_binary_stats_test =20 +TEST_GEN_PROGS_riscv +=3D riscv/sbi_pmu_test TEST_GEN_PROGS_riscv +=3D arch_timer TEST_GEN_PROGS_riscv +=3D demand_paging_test TEST_GEN_PROGS_riscv +=3D dirty_log_test diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c b/tools/testi= ng/selftests/kvm/riscv/sbi_pmu_test.c new file mode 100644 index 000000000000..8e7c7a3172d8 --- /dev/null +++ b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c @@ -0,0 +1,340 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * sbi_pmu_test.c - Tests the riscv64 SBI PMU functionality. + * + * Copyright (c) 2024, Rivos Inc. + */ + +#include +#include +#include +#include +#include +#include "kvm_util.h" +#include "test_util.h" +#include "processor.h" +#include "sbi.h" + +/* Maximum counters(firmware + hardware) */ +#define RISCV_MAX_PMU_COUNTERS 64 +union sbi_pmu_ctr_info ctrinfo_arr[RISCV_MAX_PMU_COUNTERS]; + +/* Cache the available counters in a bitmask */ +static unsigned long counter_mask_available; + +unsigned long pmu_csr_read_num(int csr_num) +{ +#define switchcase_csr_read(__csr_num, __val) {\ + case __csr_num: \ + __val =3D csr_read(__csr_num); \ + break; } +#define switchcase_csr_read_2(__csr_num, __val) {\ + switchcase_csr_read(__csr_num + 0, __val) \ + switchcase_csr_read(__csr_num + 1, __val)} +#define switchcase_csr_read_4(__csr_num, __val) {\ + switchcase_csr_read_2(__csr_num + 0, __val) \ + switchcase_csr_read_2(__csr_num + 2, __val)} +#define switchcase_csr_read_8(__csr_num, __val) {\ + switchcase_csr_read_4(__csr_num + 0, __val) \ + switchcase_csr_read_4(__csr_num + 4, __val)} +#define switchcase_csr_read_16(__csr_num, __val) {\ + switchcase_csr_read_8(__csr_num + 0, __val) \ + switchcase_csr_read_8(__csr_num + 8, __val)} +#define switchcase_csr_read_32(__csr_num, __val) {\ + switchcase_csr_read_16(__csr_num + 0, __val) \ + switchcase_csr_read_16(__csr_num + 16, __val)} + + unsigned long ret =3D 0; + + switch (csr_num) { + switchcase_csr_read_32(CSR_CYCLE, ret) + switchcase_csr_read_32(CSR_CYCLEH, ret) + default : + break; + } + + return ret; +#undef switchcase_csr_read_32 +#undef switchcase_csr_read_16 +#undef switchcase_csr_read_8 +#undef switchcase_csr_read_4 +#undef switchcase_csr_read_2 +#undef switchcase_csr_read +} + +static inline void dummy_func_loop(uint64_t iter) +{ + int i =3D 0; + + while (i < iter) { + asm volatile("nop"); + i++; + } +} + +static void start_counter(unsigned long counter, unsigned long start_flags, + unsigned long ival) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, counter, 1, sta= rt_flags, + ival, 0, 0); + __GUEST_ASSERT(ret.error =3D=3D 0, "Unable to start counter %ld\n", count= er); +} + +/* This should be invoked only for reset counter use case */ +static void stop_reset_counter(unsigned long counter, unsigned long stop_f= lags) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, counter, 1, + stop_flags | SBI_PMU_STOP_FLAG_RESET, 0, 0, 0); + __GUEST_ASSERT(ret.error =3D=3D SBI_ERR_ALREADY_STOPPED, + "Unable to stop counter %ld\n", counter); +} + +static void stop_counter(unsigned long counter, unsigned long stop_flags) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, counter, 1, stop= _flags, + 0, 0, 0); + __GUEST_ASSERT(ret.error =3D=3D 0, "Unable to stop counter %ld error %ld\= n", + counter, ret.error); +} + +static void guest_illegal_exception_handler(struct ex_regs *regs) +{ + __GUEST_ASSERT(regs->cause =3D=3D EXC_INST_ILLEGAL, + "Unexpected exception handler %lx\n", regs->cause); + + /* skip the trapping instruction */ + regs->epc +=3D 4; +} + +static unsigned long get_counter_index(unsigned long cbase, unsigned long = cmask, + unsigned long cflags, + unsigned long event) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, cmas= k, + cflags, event, 0, 0); + __GUEST_ASSERT(ret.error =3D=3D 0, "config matching failed %ld\n", ret.er= ror); + GUEST_ASSERT(ret.value < RISCV_MAX_PMU_COUNTERS); + GUEST_ASSERT(BIT(ret.value) & counter_mask_available); + + return ret.value; +} + +static unsigned long get_num_counters(void) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_NUM_COUNTERS, 0, 0, 0, 0, 0, 0= ); + + __GUEST_ASSERT(ret.error =3D=3D 0, "Unable to retrieve number of counters= from SBI PMU"); + __GUEST_ASSERT(ret.value < RISCV_MAX_PMU_COUNTERS, + "Invalid number of counters %ld\n", ret.value); + + return ret.value; +} + +static void update_counter_info(int num_counters) +{ + int i =3D 0; + struct sbiret ret; + + for (i =3D 0; i < num_counters; i++) { + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_GET_INFO, i, 0, 0, 0,= 0, 0); + + /* There can be gaps in logical counter indicies*/ + if (ret.error) + continue; + GUEST_ASSERT_NE(ret.value, 0); + + ctrinfo_arr[i].value =3D ret.value; + counter_mask_available |=3D BIT(i); + } + + GUEST_ASSERT(counter_mask_available > 0); +} + +static unsigned long read_counter(int idx, union sbi_pmu_ctr_info ctrinfo) +{ + unsigned long counter_val =3D 0; + struct sbiret ret; + + __GUEST_ASSERT(ctrinfo.type < 2, "Invalid counter type %d", ctrinfo.type); + + if (ctrinfo.type =3D=3D SBI_PMU_CTR_TYPE_HW) { + counter_val =3D pmu_csr_read_num(ctrinfo.csr); + } else if (ctrinfo.type =3D=3D SBI_PMU_CTR_TYPE_FW) { + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ, idx, 0, 0, 0= , 0, 0); + GUEST_ASSERT(ret.error =3D=3D 0); + counter_val =3D ret.value; + } + + return counter_val; +} + +static void test_pmu_event(unsigned long event) +{ + unsigned long counter; + unsigned long counter_value_pre, counter_value_post; + unsigned long counter_init_value =3D 100; + + counter =3D get_counter_index(0, counter_mask_available, 0, event); + counter_value_pre =3D read_counter(counter, ctrinfo_arr[counter]); + + /* Do not set the initial value */ + start_counter(counter, 0, counter_init_value); + dummy_func_loop(10000); + stop_counter(counter, 0); + + counter_value_post =3D read_counter(counter, ctrinfo_arr[counter]); + __GUEST_ASSERT(counter_value_post > counter_value_pre, + "counter_value_post %lx counter_value_pre %lx\n", + counter_value_post, counter_value_pre); + + /* Now set the initial value and compare */ + start_counter(counter, SBI_PMU_START_FLAG_SET_INIT_VALUE, counter_init_va= lue); + dummy_func_loop(10000); + stop_counter(counter, 0); + + counter_value_post =3D read_counter(counter, ctrinfo_arr[counter]); + __GUEST_ASSERT(counter_value_post > counter_init_value, + "counter_value_post %lx counter_init_value %lx\n", + counter_value_post, counter_init_value); + + stop_reset_counter(counter, 0); +} + +static void test_invalid_event(void) +{ + struct sbiret ret; + unsigned long event =3D 0x1234; /* A random event */ + + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, 0, + counter_mask_available, 0, event, 0, 0); + GUEST_ASSERT_EQ(ret.error, SBI_ERR_NOT_SUPPORTED); +} + +static void test_pmu_events(void) +{ + int num_counters =3D 0; + + /* Get the counter details */ + num_counters =3D get_num_counters(); + update_counter_info(num_counters); + + /* Sanity testing for any random invalid event */ + test_invalid_event(); + + /* Only these two events are guaranteed to be present */ + test_pmu_event(SBI_PMU_HW_CPU_CYCLES); + test_pmu_event(SBI_PMU_HW_INSTRUCTIONS); + + GUEST_DONE(); +} + +static void test_pmu_basic_sanity(void) +{ + long out_val =3D 0; + bool probe; + struct sbiret ret; + int num_counters =3D 0, i; + union sbi_pmu_ctr_info ctrinfo; + + probe =3D guest_sbi_probe_extension(SBI_EXT_PMU, &out_val); + GUEST_ASSERT(probe && out_val =3D=3D 1); + + num_counters =3D get_num_counters(); + + for (i =3D 0; i < num_counters; i++) { + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_GET_INFO, i, + 0, 0, 0, 0, 0); + + /* There can be gaps in logical counter indicies*/ + if (ret.error) + continue; + GUEST_ASSERT_NE(ret.value, 0); + + ctrinfo.value =3D ret.value; + + /** + * Accesibillity check of hardware and read capability of firmware count= ers. + * The spec doesn't mandate any initial value. No need to check any valu= e. + */ + read_counter(i, ctrinfo); + } + + GUEST_DONE(); +} + +static void run_vcpu(struct kvm_vcpu *vcpu) +{ + struct ucall uc; + + vcpu_run(vcpu); + switch (get_ucall(vcpu, &uc)) { + case UCALL_ABORT: + REPORT_GUEST_ASSERT(uc); + break; + case UCALL_DONE: + case UCALL_SYNC: + break; + default: + TEST_FAIL("Unknown ucall %lu", uc.cmd); + break; + } +} + +void test_vm_destroy(struct kvm_vm *vm) +{ + memset(ctrinfo_arr, 0, sizeof(union sbi_pmu_ctr_info) * RISCV_MAX_PMU_COU= NTERS); + counter_mask_available =3D 0; + kvm_vm_free(vm); +} + +static void test_vm_basic_test(void *guest_code) +{ + struct kvm_vm *vm; + struct kvm_vcpu *vcpu; + + vm =3D vm_create_with_one_vcpu(&vcpu, guest_code); + __TEST_REQUIRE(__vcpu_has_sbi_ext(vcpu, KVM_RISCV_SBI_EXT_PMU), + "SBI PMU not available, skipping test"); + vm_init_vector_tables(vm); + /* Illegal instruction handler is required to verify read access without = configuration */ + vm_install_exception_handler(vm, EXC_INST_ILLEGAL, guest_illegal_exceptio= n_handler); + + vcpu_init_vector_tables(vcpu); + run_vcpu(vcpu); + + test_vm_destroy(vm); +} + +static void test_vm_events_test(void *guest_code) +{ + struct kvm_vm *vm =3D NULL; + struct kvm_vcpu *vcpu =3D NULL; + + vm =3D vm_create_with_one_vcpu(&vcpu, guest_code); + __TEST_REQUIRE(__vcpu_has_sbi_ext(vcpu, KVM_RISCV_SBI_EXT_PMU), + "SBI PMU not available, skipping test"); + run_vcpu(vcpu); + + test_vm_destroy(vm); +} + +int main(void) +{ + test_vm_basic_test(test_pmu_basic_sanity); + pr_info("SBI PMU basic test : PASS\n"); + + test_vm_events_test(test_pmu_events); + pr_info("SBI PMU event verification test : PASS\n"); + + return 0; +} --=20 2.34.1 From nobody Mon Feb 9 08:54:35 2026 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9516B131723 for ; Wed, 3 Apr 2024 08:06:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131562; cv=none; b=Nsfli19yBxN0nCnQDm4X6dNivB68lDxCeq5V9HIoiD0uk11J3gylWpuh5UTta5E5pxb04isCResZJjQnBUe/TDvygAs0lJmPVq8ilJbrlNkorIt4eaD4TIfJRBRPX1MVsMBotyr+dROzHJBwW1+WnCcKwBZPQLnDB+F1plWX+fw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131562; c=relaxed/simple; bh=6HAvbs/h+QFBMjYu2uv3IloV02R7hD+zw2JghX3dVNk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=IJhsg0JylgfYC0GhAeLyYE8bUAbVYNdNFx5JuEAw6pKZa4/ZcD0vy7FPmmSbF0olbjGa19wivRxH4dgclLb+jC4OZhqGdzkOnsdqv9qk7MSkRTkiAO9bU3XE6JupLWx0aaQmAB5aRUSnp2rhsa7eG2IkPsoZWhaBEODjLjmoZhc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=EmKg+oA0; arc=none smtp.client-ip=209.85.214.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="EmKg+oA0" Received: by mail-pl1-f171.google.com with SMTP id d9443c01a7336-1e267238375so5042075ad.1 for ; Wed, 03 Apr 2024 01:06:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131559; x=1712736359; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QiRGaFoKeEXKkn+uQbOU1j6rVkfyQcqx7Ktuzq541sw=; b=EmKg+oA0p7nSMGGNwlUaVii/dUdMxQWY2LfLU4P/MyiMRSVmcpTtQeZgeZfWjS+iXQ E17fsOV2KXANk/dj7AvNaYf2WHC+WOMaLrpn1xmebRMz51ZLO0BHkve/I8PU61tfhqnw ldX29HJ4hl3zqnXkPQ9cBM5VYLRhEIRrN5yFh1Occ00emgWQwlxeCM0K9Mdkkj+U4GqJ lPiiRvXzwq6SCccMxXDcK1ug4V5HbMDKEZqsXCqs3HyM/072WPVdBYqxKusAkhVStGYG 2uuEpj4JIsSyRHP2XeWv2M2wM479K6heHj91Fu6Ybx837OZsnV/+pYi1kR5XP002i2Y/ 2Q9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131559; x=1712736359; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QiRGaFoKeEXKkn+uQbOU1j6rVkfyQcqx7Ktuzq541sw=; b=Y0AfHSkaSFQe13+kB67DNFxsNs1EgfN8Quz/tXr88fwC5OViHgpZNIlL3pOLTtPDEZ QO8KKnEj3rFPkn0ohS47eiZhvBMUEAAPy2+kDJJU+PmQLY9tRqOZxAQZZpL3tCI6+qhp so2WjEBFjLTSY/bIozy+VU8Tibk6pZzD5oE0H3bb5jbmi8F+ZGvkouhxSodz1d25dbl2 /vlfwj/G2g9Uf1FKOdYSNYsfMvRP5e2gBjb1gvfLdBioUfOyhwY8nWJwK0rof/jkruZT rvezhTB+FZOxzQ+VZ7bgZ1HFXfqOQApBS16jif+tWotgE38uHXs9jX//x20v2MfOe2UF 7wcQ== X-Gm-Message-State: AOJu0Yxe7Qga0XJgkecYBdBpeAAKobp/FPR7TiQjOrdVTCSZ/329F9YU sfQNbohs+yy9Zal++Oc83+wwEaPswBYbal0aXDh7M0dcrDfqIe4IYoBRQ8vyIpAijBrnZVuNLLR P X-Google-Smtp-Source: AGHT+IFXXTLLFkv43kYTnbNPYdO7OcKcoIWVKkiXhLEEPUmEqBIkqvXfcIj5Q46ZbmbSydNL7e6NQg== X-Received: by 2002:a17:902:e747:b0:1e0:e8b5:3225 with SMTP id p7-20020a170902e74700b001e0e8b53225mr3012611plf.12.1712131559154; Wed, 03 Apr 2024 01:05:59 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:57 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 21/22] KVM: riscv: selftests: Add a test for PMU snapshot functionality Date: Wed, 3 Apr 2024 01:04:50 -0700 Message-Id: <20240403080452.1007601-22-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Verify PMU snapshot functionality by setting up the shared memory correctly and reading the counter values from the shared memory instead of the CSR. Reviewed-by: Anup Patel Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- .../testing/selftests/kvm/include/riscv/sbi.h | 25 ++++ .../selftests/kvm/lib/riscv/processor.c | 12 ++ .../selftests/kvm/riscv/sbi_pmu_test.c | 127 ++++++++++++++++++ 3 files changed, 164 insertions(+) diff --git a/tools/testing/selftests/kvm/include/riscv/sbi.h b/tools/testin= g/selftests/kvm/include/riscv/sbi.h index 6675ca673c77..8c98bd99d450 100644 --- a/tools/testing/selftests/kvm/include/riscv/sbi.h +++ b/tools/testing/selftests/kvm/include/riscv/sbi.h @@ -8,6 +8,12 @@ #ifndef SELFTEST_KVM_SBI_H #define SELFTEST_KVM_SBI_H =20 +/* SBI spec version fields */ +#define SBI_SPEC_VERSION_DEFAULT 0x1 +#define SBI_SPEC_VERSION_MAJOR_SHIFT 24 +#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f +#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff + /* SBI return error codes */ #define SBI_SUCCESS 0 #define SBI_ERR_FAILURE -1 @@ -33,6 +39,9 @@ enum sbi_ext_id { }; =20 enum sbi_ext_base_fid { + SBI_EXT_BASE_GET_SPEC_VERSION =3D 0, + SBI_EXT_BASE_GET_IMP_ID, + SBI_EXT_BASE_GET_IMP_VERSION, SBI_EXT_BASE_PROBE_EXT =3D 3, }; enum sbi_ext_pmu_fid { @@ -60,6 +69,12 @@ union sbi_pmu_ctr_info { }; }; =20 +struct riscv_pmu_snapshot_data { + u64 ctr_overflow_mask; + u64 ctr_values[64]; + u64 reserved[447]; +}; + struct sbiret { long error; long value; @@ -113,4 +128,14 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned lon= g arg0, =20 bool guest_sbi_probe_extension(int extid, long *out_val); =20 +/* Make SBI version */ +static inline unsigned long sbi_mk_version(unsigned long major, + unsigned long minor) +{ + return ((major & SBI_SPEC_VERSION_MAJOR_MASK) << + SBI_SPEC_VERSION_MAJOR_SHIFT) | minor; +} + +unsigned long get_host_sbi_spec_version(void); + #endif /* SELFTEST_KVM_SBI_H */ diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/test= ing/selftests/kvm/lib/riscv/processor.c index e8211f5d6863..ccb35573749c 100644 --- a/tools/testing/selftests/kvm/lib/riscv/processor.c +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c @@ -502,3 +502,15 @@ bool guest_sbi_probe_extension(int extid, long *out_va= l) =20 return true; } + +unsigned long get_host_sbi_spec_version(void) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION, 0, + 0, 0, 0, 0, 0); + + GUEST_ASSERT(!ret.error); + + return ret.value; +} diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c b/tools/testi= ng/selftests/kvm/riscv/sbi_pmu_test.c index 8e7c7a3172d8..7d195be5c3d9 100644 --- a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c +++ b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c @@ -19,6 +19,11 @@ #define RISCV_MAX_PMU_COUNTERS 64 union sbi_pmu_ctr_info ctrinfo_arr[RISCV_MAX_PMU_COUNTERS]; =20 +/* Snapshot shared memory data */ +#define PMU_SNAPSHOT_GPA_BASE BIT(30) +static void *snapshot_gva; +static vm_paddr_t snapshot_gpa; + /* Cache the available counters in a bitmask */ static unsigned long counter_mask_available; =20 @@ -178,6 +183,32 @@ static unsigned long read_counter(int idx, union sbi_p= mu_ctr_info ctrinfo) return counter_val; } =20 +static inline void verify_sbi_requirement_assert(void) +{ + long out_val =3D 0; + bool probe; + + probe =3D guest_sbi_probe_extension(SBI_EXT_PMU, &out_val); + GUEST_ASSERT(probe && out_val =3D=3D 1); + + if (get_host_sbi_spec_version() < sbi_mk_version(2, 0)) + __GUEST_ASSERT(0, "SBI implementation version doesn't support PMU Snapsh= ot"); +} + +static void snapshot_set_shmem(vm_paddr_t gpa, unsigned long flags) +{ + unsigned long lo =3D (unsigned long)gpa; +#if __riscv_xlen =3D=3D 32 + unsigned long hi =3D (unsigned long)(gpa >> 32); +#else + unsigned long hi =3D gpa =3D=3D -1 ? -1 : 0; +#endif + struct sbiret ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHM= EM, + lo, hi, flags, 0, 0, 0); + + GUEST_ASSERT(ret.value =3D=3D 0 && ret.error =3D=3D 0); +} + static void test_pmu_event(unsigned long event) { unsigned long counter; @@ -210,6 +241,41 @@ static void test_pmu_event(unsigned long event) stop_reset_counter(counter, 0); } =20 +static void test_pmu_event_snapshot(unsigned long event) +{ + unsigned long counter; + unsigned long counter_value_pre, counter_value_post; + unsigned long counter_init_value =3D 100; + struct riscv_pmu_snapshot_data *snapshot_data =3D snapshot_gva; + + counter =3D get_counter_index(0, counter_mask_available, 0, event); + counter_value_pre =3D read_counter(counter, ctrinfo_arr[counter]); + + /* Do not set the initial value */ + start_counter(counter, 0, 0); + dummy_func_loop(10000); + stop_counter(counter, SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT); + + /* The counter value is updated w.r.t relative index of cbase */ + counter_value_post =3D READ_ONCE(snapshot_data->ctr_values[0]); + __GUEST_ASSERT(counter_value_post > counter_value_pre, + "counter_value_post %lx counter_value_pre %lx\n", + counter_value_post, counter_value_pre); + + /* Now set the initial value and compare */ + WRITE_ONCE(snapshot_data->ctr_values[0], counter_init_value); + start_counter(counter, SBI_PMU_START_FLAG_INIT_SNAPSHOT, 0); + dummy_func_loop(10000); + stop_counter(counter, SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT); + + counter_value_post =3D READ_ONCE(snapshot_data->ctr_values[0]); + __GUEST_ASSERT(counter_value_post > counter_init_value, + "counter_value_post %lx counter_init_value %lx for counter\n", + counter_value_post, counter_init_value); + + stop_reset_counter(counter, 0); +} + static void test_invalid_event(void) { struct sbiret ret; @@ -272,6 +338,34 @@ static void test_pmu_basic_sanity(void) GUEST_DONE(); } =20 +static void test_pmu_events_snaphost(void) +{ + int num_counters =3D 0; + struct riscv_pmu_snapshot_data *snapshot_data =3D snapshot_gva; + int i; + + /* Verify presence of SBI PMU and minimum requrired SBI version */ + verify_sbi_requirement_assert(); + + snapshot_set_shmem(snapshot_gpa, 0); + + /* Get the counter details */ + num_counters =3D get_num_counters(); + update_counter_info(num_counters); + + /* Validate shared memory access */ + GUEST_ASSERT_EQ(READ_ONCE(snapshot_data->ctr_overflow_mask), 0); + for (i =3D 0; i < num_counters; i++) { + if (counter_mask_available & (BIT(i))) + GUEST_ASSERT_EQ(READ_ONCE(snapshot_data->ctr_values[i]), 0); + } + /* Only these two events are guranteed to be present */ + test_pmu_event_snapshot(SBI_PMU_HW_CPU_CYCLES); + test_pmu_event_snapshot(SBI_PMU_HW_INSTRUCTIONS); + + GUEST_DONE(); +} + static void run_vcpu(struct kvm_vcpu *vcpu) { struct ucall uc; @@ -328,13 +422,46 @@ static void test_vm_events_test(void *guest_code) test_vm_destroy(vm); } =20 +static void test_vm_setup_snapshot_mem(struct kvm_vm *vm, struct kvm_vcpu = *vcpu) +{ + /* PMU Snapshot requires single page only */ + vm_userspace_mem_region_add(vm, VM_MEM_SRC_ANONYMOUS, PMU_SNAPSHOT_GPA_BA= SE, 1, 1, 0); + /* PMU_SNAPSHOT_GPA_BASE is identity mapped */ + virt_map(vm, PMU_SNAPSHOT_GPA_BASE, PMU_SNAPSHOT_GPA_BASE, 1); + + snapshot_gva =3D (void *)(PMU_SNAPSHOT_GPA_BASE); + snapshot_gpa =3D addr_gva2gpa(vcpu->vm, (vm_vaddr_t)snapshot_gva); + sync_global_to_guest(vcpu->vm, snapshot_gva); + sync_global_to_guest(vcpu->vm, snapshot_gpa); +} + +static void test_vm_events_snapshot_test(void *guest_code) +{ + struct kvm_vm *vm =3D NULL; + struct kvm_vcpu *vcpu; + + vm =3D vm_create_with_one_vcpu(&vcpu, guest_code); + __TEST_REQUIRE(__vcpu_has_sbi_ext(vcpu, KVM_RISCV_SBI_EXT_PMU), + "SBI PMU not available, skipping test"); + + test_vm_setup_snapshot_mem(vm, vcpu); + + run_vcpu(vcpu); + + test_vm_destroy(vm); +} + int main(void) { + pr_info("SBI PMU basic test : starting\n"); test_vm_basic_test(test_pmu_basic_sanity); pr_info("SBI PMU basic test : PASS\n"); =20 test_vm_events_test(test_pmu_events); pr_info("SBI PMU event verification test : PASS\n"); =20 + test_vm_events_snapshot_test(test_pmu_events_snaphost); + pr_info("SBI PMU event verification with snapshot test : PASS\n"); + return 0; } --=20 2.34.1 From nobody Mon Feb 9 08:54:35 2026 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE46113248C for ; Wed, 3 Apr 2024 08:06:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131565; cv=none; b=YH9+aRADC3Ebu/xOQti0VbwEMdj7xEIf8vp/ZfkL722qVgndvGLZj11DnXf4IMLHnlgGQMZMmISTxPZ0DxGdQBzDIjecIzeHI31evHvQdxGReqwN6bDnqmwzvLgvxCxL3k1kL0TEeaN6Fq/Pa24hPzE9KOOjBUv8G4Sn6SzusW4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712131565; c=relaxed/simple; bh=HPH+bQ+ud9CPVlAAxj5MJgVXSyPuFRNLxCzCWuT8AhI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kddFefRkqEc2Ck5tyAMcdtpYKneegKtzdKeASLSDCAty81Y31o/xcENQomgGmX+rauwHjbp1AorJWM31GxXkzQIKvTVIeK53qincVN1omCB7B3yjDSlTybp6ELW0YKJNF5S+44C1B5zqJOP/wDpZwj8JkrmhRnIE1w/UGOXwvY4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=jdbomHNx; arc=none smtp.client-ip=209.85.214.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="jdbomHNx" Received: by mail-pl1-f172.google.com with SMTP id d9443c01a7336-1e2232e30f4so46287625ad.2 for ; Wed, 03 Apr 2024 01:06:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131562; x=1712736362; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=08Ow0qzJAlLAfVOdK6hW39Nfp7LW+caK9DtQyZhdmmU=; b=jdbomHNxWRoJF8JB0GQwG0pHOqOck26F5NSM56B0Jm8FZpSD+jVrhh6hu1VvOhtr7p jsjGiRh1HQ1OcIUn12uIaQt/3Un2I/69i5rgBV6wQSV2Q0AuLy/ocx6IpHsCOgLHizqk ZIKcjZ+bVRdzr4m0jcNXQ7Au/QVKY0Pv6kZeNkXDNaq6d0HWHst9DoUFe7HJsMeNuji2 Qar4ISO8dzeT5VgQ5M24r249M905vccCCloTideXK5krKnLO1fSGEnLK5cYfKjVJH9oh ea0CKHBI+tHtLQwO7of5UDEW0KXdQ8yeTnOu3KTouzeDENcvWRWC4WTpyE66d5UdYoPb AbqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131562; x=1712736362; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=08Ow0qzJAlLAfVOdK6hW39Nfp7LW+caK9DtQyZhdmmU=; b=O17QZ/fLrospB00nphTxWrYW87PzQDjBLHa7qzHkHBNYpNRC7asFlwDrFP9l717tfv 2kGgvW05GFO+PV2WSFXWFmolaGV86IfFQZrKbM4YM6S2/ZCVbJqdXwbvrSqBIn1aEBGe /Nv2RI6PiBkmDSxptUGjR15GPSJJ/+1Dked+pdzOascJH8datnrfSUqf1GAWLGNu2RJa uHegMmUP0Gss7WHJ+MMR45F1IMZEC4Q3JF0KMV7B3U8FO0B91Rug1lH29nV23lLSuiNU unORf+y75jeEmNUNVWpQlWTly1fk0tZC4p5KXC73km0Gcr2MhpBvS6C74mo6xD8nFif7 PXww== X-Gm-Message-State: AOJu0YwI/IwxLPNut3pweeEXKMEWb0qiPxoXG2dD7kN/1UDltXbXrAhy 7E2m8DycJsdTNtmFiaIcaTOy0UTUIKkjU2c5yxSJGwWeEBNKtjOsj/S7/feXN2xPb6fu05osidA N X-Google-Smtp-Source: AGHT+IE72ENkNXFbTzbhg6SzqOY0byxQCRn9OXM0YoFZNh+Y8OZZcNtpF6ZIM4eDWD3GUsrp+79BKw== X-Received: by 2002:a17:902:ea10:b0:1e0:e6b0:2364 with SMTP id s16-20020a170902ea1000b001e0e6b02364mr14335253plg.64.1712131562243; Wed, 03 Apr 2024 01:06:02 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:06:00 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 22/22] KVM: riscv: selftests: Add a test for counter overflow Date: Wed, 3 Apr 2024 01:04:51 -0700 Message-Id: <20240403080452.1007601-23-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a test for verifying overflow interrupt. Currently, it relies on overflow support on cycle/instret events. This test works for cycle/ instret events which support sampling via hpmcounters on the platform. There are no ISA extensions to detect if a platform supports that. Thus, this test will fail on platform with virtualization but doesn't support overflow on these two events. Reviewed-by: Anup Patel Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- .../selftests/kvm/riscv/sbi_pmu_test.c | 114 ++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c b/tools/testi= ng/selftests/kvm/riscv/sbi_pmu_test.c index 7d195be5c3d9..451db956b885 100644 --- a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c +++ b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c @@ -14,6 +14,7 @@ #include "test_util.h" #include "processor.h" #include "sbi.h" +#include "arch_timer.h" =20 /* Maximum counters(firmware + hardware) */ #define RISCV_MAX_PMU_COUNTERS 64 @@ -24,6 +25,9 @@ union sbi_pmu_ctr_info ctrinfo_arr[RISCV_MAX_PMU_COUNTERS= ]; static void *snapshot_gva; static vm_paddr_t snapshot_gpa; =20 +static int vcpu_shared_irq_count; +static int counter_in_use; + /* Cache the available counters in a bitmask */ static unsigned long counter_mask_available; =20 @@ -117,6 +121,31 @@ static void guest_illegal_exception_handler(struct ex_= regs *regs) regs->epc +=3D 4; } =20 +static void guest_irq_handler(struct ex_regs *regs) +{ + unsigned int irq_num =3D regs->cause & ~CAUSE_IRQ_FLAG; + struct riscv_pmu_snapshot_data *snapshot_data =3D snapshot_gva; + unsigned long overflown_mask; + unsigned long counter_val =3D 0; + + /* Validate that we are in the correct irq handler */ + GUEST_ASSERT_EQ(irq_num, IRQ_PMU_OVF); + + /* Stop all counters first to avoid further interrupts */ + stop_counter(counter_in_use, SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT); + + csr_clear(CSR_SIP, BIT(IRQ_PMU_OVF)); + + overflown_mask =3D READ_ONCE(snapshot_data->ctr_overflow_mask); + GUEST_ASSERT(overflown_mask & 0x01); + + WRITE_ONCE(vcpu_shared_irq_count, vcpu_shared_irq_count+1); + + counter_val =3D READ_ONCE(snapshot_data->ctr_values[0]); + /* Now start the counter to mimick the real driver behavior */ + start_counter(counter_in_use, SBI_PMU_START_FLAG_SET_INIT_VALUE, counter_= val); +} + static unsigned long get_counter_index(unsigned long cbase, unsigned long = cmask, unsigned long cflags, unsigned long event) @@ -276,6 +305,33 @@ static void test_pmu_event_snapshot(unsigned long even= t) stop_reset_counter(counter, 0); } =20 +static void test_pmu_event_overflow(unsigned long event) +{ + unsigned long counter; + unsigned long counter_value_post; + unsigned long counter_init_value =3D ULONG_MAX - 10000; + struct riscv_pmu_snapshot_data *snapshot_data =3D snapshot_gva; + + counter =3D get_counter_index(0, counter_mask_available, 0, event); + counter_in_use =3D counter; + + /* The counter value is updated w.r.t relative index of cbase passed to s= tart/stop */ + WRITE_ONCE(snapshot_data->ctr_values[0], counter_init_value); + start_counter(counter, SBI_PMU_START_FLAG_INIT_SNAPSHOT, 0); + dummy_func_loop(10000); + udelay(msecs_to_usecs(2000)); + /* irq handler should have stopped the counter */ + stop_counter(counter, SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT); + + counter_value_post =3D READ_ONCE(snapshot_data->ctr_values[0]); + /* The counter value after stopping should be less the init value due to = overflow */ + __GUEST_ASSERT(counter_value_post < counter_init_value, + "counter_value_post %lx counter_init_value %lx for counter\n", + counter_value_post, counter_init_value); + + stop_reset_counter(counter, 0); +} + static void test_invalid_event(void) { struct sbiret ret; @@ -366,6 +422,34 @@ static void test_pmu_events_snaphost(void) GUEST_DONE(); } =20 +static void test_pmu_events_overflow(void) +{ + int num_counters =3D 0; + + /* Verify presence of SBI PMU and minimum requrired SBI version */ + verify_sbi_requirement_assert(); + + snapshot_set_shmem(snapshot_gpa, 0); + csr_set(CSR_IE, BIT(IRQ_PMU_OVF)); + local_irq_enable(); + + /* Get the counter details */ + num_counters =3D get_num_counters(); + update_counter_info(num_counters); + + /* + * Qemu supports overflow for cycle/instruction. + * This test may fail on any platform that do not support overflow for th= ese two events. + */ + test_pmu_event_overflow(SBI_PMU_HW_CPU_CYCLES); + GUEST_ASSERT_EQ(vcpu_shared_irq_count, 1); + + test_pmu_event_overflow(SBI_PMU_HW_INSTRUCTIONS); + GUEST_ASSERT_EQ(vcpu_shared_irq_count, 2); + + GUEST_DONE(); +} + static void run_vcpu(struct kvm_vcpu *vcpu) { struct ucall uc; @@ -451,6 +535,33 @@ static void test_vm_events_snapshot_test(void *guest_c= ode) test_vm_destroy(vm); } =20 +static void test_vm_events_overflow(void *guest_code) +{ + struct kvm_vm *vm =3D NULL; + struct kvm_vcpu *vcpu; + + vm =3D vm_create_with_one_vcpu(&vcpu, guest_code); + __TEST_REQUIRE(__vcpu_has_sbi_ext(vcpu, KVM_RISCV_SBI_EXT_PMU), + "SBI PMU not available, skipping test"); + + __TEST_REQUIRE(__vcpu_has_isa_ext(vcpu, KVM_RISCV_ISA_EXT_SSCOFPMF), + "Sscofpmf is not available, skipping overflow test"); + + + test_vm_setup_snapshot_mem(vm, vcpu); + vm_init_vector_tables(vm); + vm_install_interrupt_handler(vm, guest_irq_handler); + + vcpu_init_vector_tables(vcpu); + /* Initialize guest timer frequency. */ + vcpu_get_reg(vcpu, RISCV_TIMER_REG(frequency), &timer_freq); + sync_global_to_guest(vm, timer_freq); + + run_vcpu(vcpu); + + test_vm_destroy(vm); +} + int main(void) { pr_info("SBI PMU basic test : starting\n"); @@ -463,5 +574,8 @@ int main(void) test_vm_events_snapshot_test(test_pmu_events_snaphost); pr_info("SBI PMU event verification with snapshot test : PASS\n"); =20 + test_vm_events_overflow(test_pmu_events_overflow); + pr_info("SBI PMU event verification with overflow test : PASS\n"); + return 0; } --=20 2.34.1