From nobody Fri Sep 20 01:19:17 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FB1356472; Wed, 3 Apr 2024 07:07:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712128062; cv=none; b=ecMWR1YplXm78UgXxJbkTFXTVJsMfUuC9Z20u5A0opeSAhdUlOIw2AepesC5HMhuQQECXREbiVccOCnfYhi34D/wxIVtkhRoLXl/O6hdSrBd1jk9ONH6zo6pTnPRNJW7LBb22egZROa8/RbldWnk6vv0e0hPtfCcHFNiTIIyCbc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712128062; c=relaxed/simple; bh=3SQfebgo0c9D+6hgUzkYoZc79+Gd52nYA8/B7yOeAHY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Tlh5WjUtpIxK+47L9KJ08qLJ7SSN8i/GQ7lTZzOlIhOi0dZssi1vH4uNKAmhi1fcTCWVXZVbaioJeU2qrLpLUMbwuOOxguZotqgJcBXElL72Ampdwgl2JiPmHW3pZOV7byqOvZkgenBI4ZoGdUFU38HGod/z5JgOd4bJNZfZJhI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=gOT8ugC7; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="gOT8ugC7" X-UUID: d92eb988f18811ee935d6952f98a51a9-20240403 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=C2cAGORlyka9h5MTmzyEnIuwUY4TFoGrpjXuIv5ADPc=; b=gOT8ugC7gPGpgg8y8nbHVvOUUY5hCfLFUTxZ8dVzu7yYlZByvknto/pRqTOxcsgR7s9ROWG8tJUAOlLDtrZ5cWR7qNJQvUxbhTUelpToAQH/c/Scp5eKXxAxyrhzveAb+wxjIz7xqXMYVru1kYbX9O0ctXmB6qhO1wdjYVNunN4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.37,REQID:ddb76e45-7567-4d08-8ad8-c2476c334572,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:6f543d0,CLOUDID:289fc385-8d4f-477b-89d2-1e3bdbef96d1,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: d92eb988f18811ee935d6952f98a51a9-20240403 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1887464480; Wed, 03 Apr 2024 15:07:35 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 3 Apr 2024 15:07:34 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 3 Apr 2024 15:07:34 +0800 From: Shawn Sung To: Chun-Kuang Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann , Sumit Semwal , =?UTF-8?q?Christian=20K=C3=B6nig?= , , , , , , , Jason-JH.Lin , Hsiao Chien Sung Subject: [PATCH v4 4/9] drm/mediatek: Add mtk_ddp_sec_write to config secure buffer info Date: Wed, 3 Apr 2024 15:07:27 +0800 Message-ID: <20240403070732.22085-5-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240403070732.22085-1-shawn.sung@mediatek.com> References: <20240403070732.22085-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--7.158600-8.000000 X-TMASE-MatchedRID: wDTc/wNgEcNvH7GZAcw0g03dRRsh/h6yqQ9UezeTkTj7efdnqtsaE8rv kkfH+U2B6rlI+AD5R5xEzxsFM1euZm94Ipa1otxoDB+ErBr0bANKKWJchzA/cQqiCYa6w8tvXdA L8LmzRmrbU8hbAd0JD9wezITcev2HHxPMjOKY7A8LbigRnpKlKWxlRJiH4397RbBzrX9fqDCIhx Q5/Decvsmy3bJ2rAIwnCY56bO5Mmx5uG5Lfno7eA== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--7.158600-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 48AB657E7C4F9BBDDF1E15C33867E8B23DE5DF3112FD0B89F34D43F642CD0E7D2000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "Jason-JH.Lin" Add mtk_ddp_sec_write to configure secure buffer information to cmdq secure packet data. Then secure cmdq driver will use these information to configure curresponding secure DRAM address to HW overlay in secure world. Signed-off-by: Jason-JH.Lin Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 14 ++++++++++++++ drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 4 ++++ 2 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.c index 8aab373ce67c9..0ee9e42cdf0a0 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -111,6 +111,20 @@ void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, uns= igned int value, #endif } =20 +void mtk_ddp_sec_write(struct cmdq_pkt *cmdq_pkt, u32 addr, u64 base, + const enum cmdq_iwc_addr_metadata_type type, + const u32 offset, const u32 size, const u32 port) +{ +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + if (!cmdq_pkt) + return; + + /* secure buffer will be 4K alignment */ + cmdq_sec_pkt_write(cmdq_pkt, addr, base, type, + offset, ALIGN(size, PAGE_SIZE), port); +#endif +} + static int mtk_ddp_clk_enable(struct device *dev) { struct mtk_ddp_comp_dev *priv =3D dev_get_drvdata(dev); diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.h index b9c79e740abe0..a00258a5cefda 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -8,6 +8,7 @@ =20 #include #include +#include #include #include #include @@ -346,4 +347,7 @@ void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, u= nsigned int value, void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value, struct cmdq_client_reg *cmdq_reg, void __iomem *regs, unsigned int offset, unsigned int mask); +void mtk_ddp_sec_write(struct cmdq_pkt *cmdq_pkt, u32 addr, u64 base, + const enum cmdq_iwc_addr_metadata_type type, + const u32 offset, const u32 size, const u32 port); #endif /* MTK_DDP_COMP_H */ --=20 2.18.0