From nobody Fri Sep 20 01:25:38 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 662AE60266; Wed, 3 Apr 2024 06:56:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712127383; cv=none; b=SgcmIR7W23mqNiCtNRsH/kmP13jtsWUF3iC6zTgNSmlg35lLNmwXymde3knVEAHlHZy/pzD52ljBh+XWQQ38aK9rUBYtQNNmbOldTH3QrXheF5/683vbUBdk/wG3xXWarbN/ud151h1fNj1vJc4rP+dcf/9b18xBEw8bhCn0wGo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712127383; c=relaxed/simple; bh=oBdA26JmC8YuT8Vwkgv3Oggk4xOJFs5mJ4Xhy4EhZMo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qEoa0ey+RU22esVOXwbSyFhFhr31l0q401aybhWFGnhog2Yli2cBVwmfrAdBvlrANFLir2nCkh1j6WFSzUifB6gwSiNxRBeNW14gnpMeRvleIvP7exhINHZgcMEFptyToLLA72fYXlZCR4rpYo/AkXNNrdetKBEnJkx5X0ltwkE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=MvQXH+EQ; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="MvQXH+EQ" X-UUID: 3ed8f944f18711eeb8927bc1f75efef4-20240403 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=URfUMiQT17lJh/yOODBv4ku3XEJlT+WvGvldzqruyDc=; b=MvQXH+EQUco0AVb0iTokZwyqSSkPnDD91UyriLdyjvlyyPmyADNuC3lZUXsbIohiuy4j2fmknBUBGKutLAwFhwW+tSbCYDHqykCYsWWRsnMUUCFUosSX/9eSkr5Weih3HoPaLfybbJs84vecjy/dAkvRVwM8965TOjc+pLaeYfo=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.37,REQID:3c06e590-296b-4225-a28c-ba313df12fdd,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:6f543d0,CLOUDID:62e5a700-c26b-4159-a099-3b9d0558e447,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 3ed8f944f18711eeb8927bc1f75efef4-20240403 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1260599551; Wed, 03 Apr 2024 14:56:07 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS14N2.mediatek.inc (172.21.101.76) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 3 Apr 2024 14:56:06 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 3 Apr 2024 14:56:06 +0800 From: Shawn Sung To: CK Hu , Jassi Brar , AngeloGioacchino Del Regno CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Hsiao Chien Sung , "Jason-JH . Lin" , Houlong Wei , , , , Subject: [PATCH v4 9/9] mailbox: mediatek: Add secure CMDQ driver support for CMDQ driver Date: Wed, 3 Apr 2024 14:56:03 +0800 Message-ID: <20240403065603.21920-10-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240403065603.21920-1-shawn.sung@mediatek.com> References: <20240403065603.21920-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--5.381100-8.000000 X-TMASE-MatchedRID: 4YoTATPIqSwlen1U/pCyekKcYi5Qw/RVCt59Uh3p/NVZps+y1VXzqUY/ auwRJnMLb1ikhugskqP8Qxx3otU4NmJZXQNDzktShK8o4aoss8quiRuR9mCaugqiCYa6w8tv235 yFjo/J+U1Wb8n14I41eXQHI6jQlB9DPIzF4wRfrAURSScn+QSXt0H8LFZNFG7hqz53n/yPnq6Sb mHE/H1FlFBnyH44vf3KT6JGY05QCPJJ6OKxZ1HqboOfFLgUu3n X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--5.381100-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: B592F25D7C28CDD7C62ED6832DD71E7793473CC29696CB18FC5E8E1456399C762000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "Jason-JH.Lin" CMDQ driver will probe a secure CMDQ driver when has_sec flag in platform data is true and its device node in dts has defined a event id of CMDQ_SYNC_TOKEN_SEC_EOF. Secure CMDQ driver support on mt8188 and mt8195 currently. So add a has_secure flag to their driver data to probe it. Signed-off-by: Jason-JH.Lin Signed-off-by: Hsiao Chien Sung --- drivers/mailbox/mtk-cmdq-mailbox.c | 38 ++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-= mailbox.c index e04302ca6ec03..a8a0619baaa5c 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -15,6 +15,7 @@ #include #include #include +#include #include =20 #define CMDQ_MBOX_AUTOSUSPEND_DELAY_MS 100 @@ -60,6 +61,9 @@ struct gce_plat { u8 shift; bool control_by_sw; bool sw_ddr_en; + bool has_secure; + u32 secure_thread_nr; + u32 secure_thread_min; u32 gce_num; }; =20 @@ -569,6 +573,7 @@ static int cmdq_probe(struct platform_device *pdev) int alias_id =3D 0; static const char * const clk_name =3D "gce"; static const char * const clk_names[] =3D { "gce0", "gce1" }; + u32 hwid =3D 0; =20 cmdq =3D devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL); if (!cmdq) @@ -594,6 +599,8 @@ static int cmdq_probe(struct platform_device *pdev) dev, cmdq->base, cmdq->irq); =20 if (cmdq->pdata->gce_num > 1) { + hwid =3D of_alias_get_id(dev->of_node, clk_name); + for_each_child_of_node(phandle->parent, node) { alias_id =3D of_alias_get_id(node, clk_name); if (alias_id >=3D 0 && alias_id < cmdq->pdata->gce_num) { @@ -676,6 +683,31 @@ static int cmdq_probe(struct platform_device *pdev) pm_runtime_set_autosuspend_delay(dev, CMDQ_MBOX_AUTOSUSPEND_DELAY_MS); pm_runtime_use_autosuspend(dev); =20 + if (cmdq->pdata->has_secure) { + struct platform_device *mtk_cmdq_sec; + static struct gce_sec_plat sec_plat =3D {0}; + + if (of_property_read_u32_index(dev->of_node, "mediatek,gce-events", 0, + &sec_plat.cmdq_event) =3D=3D 0) { + sec_plat.gce_dev =3D dev; + sec_plat.hwid =3D hwid; + sec_plat.gce_num =3D cmdq->pdata->gce_num; + sec_plat.clocks =3D cmdq->clocks; + sec_plat.thread_nr =3D cmdq->pdata->thread_nr; + sec_plat.secure_thread_nr =3D cmdq->pdata->secure_thread_nr; + sec_plat.secure_thread_min =3D cmdq->pdata->secure_thread_min; + + mtk_cmdq_sec =3D platform_device_register_data(dev, "mtk-cmdq-sec", + PLATFORM_DEVID_AUTO, + &sec_plat, + sizeof(sec_plat)); + if (IS_ERR(mtk_cmdq_sec)) { + dev_err(dev, "failed to register platform_device mtk-cmdq-sec\n"); + return PTR_ERR(mtk_cmdq_sec); + } + } + } + return 0; } =20 @@ -719,6 +751,9 @@ static const struct gce_plat gce_plat_mt8188 =3D { .thread_nr =3D 32, .shift =3D 3, .control_by_sw =3D true, + .has_secure =3D true, + .secure_thread_nr =3D 2, + .secure_thread_min =3D 8, .gce_num =3D 2 }; =20 @@ -733,6 +768,9 @@ static const struct gce_plat gce_plat_mt8195 =3D { .thread_nr =3D 24, .shift =3D 3, .control_by_sw =3D true, + .has_secure =3D true, + .secure_thread_nr =3D 2, + .secure_thread_min =3D 8, .gce_num =3D 2 }; =20 --=20 2.18.0