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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-3-99ecdfdc87fc@linaro.org> References: <20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-0-99ecdfdc87fc@linaro.org> In-Reply-To: <20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-0-99ecdfdc87fc@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Martin Blumenstingl , Jerome Brunet , Kevin Hilman , Michael Turquette , Stephen Boyd , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Jagan Teki , Nicolas Belin Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=8347; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=irCtyEdiWY+FGXN7CMU2Nw/2h0kut5W+asx0S/10tnc=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBmDQleDSPXTuSsQoM0GoAHrnNTsc6tSDbD2/+j4RN7 4iyUP2OJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZg0JXgAKCRB33NvayMhJ0TgkEA CIy8cFWiC/0oHjJ6hlgZHHl/PlLgbePUaITifqBe27c1Kj0TbQgi35+tOPSVYuFzXZVuj0VYSQ21HF pMGtcQ9z2XVK2/pEfeulW20oHkPAa4LpCxrQsZOqkJy54cKdt5mI92QsbcltcrEj+1U51u1d8Vhm6c DOK8e/xTpmpi5DtgS5zP/XL6BbjmTv2Mh8qvdgkmTpTycy3xvo4YjrLcARZ4jV/3WOoOZzDN+DWdXI SJbJEqRxGNf43eHgDAr9J9kxVuu3/y/W/f21wQCPgBhzo3c8nyFaMLPCVm6IPGyRoLw4peluPIJRMS V6JETXIuVlQQNKQHTdJocdNGRFhvs5k4r3RsNZGmG2tXnLoEh50QW5o69YiiQGVgLaQEKpyhc6F8k2 MMMFQYG/BokGq/6JgsU+odjLlQCOjGBvkfXuyVEUdWcz2yys/ge/oD8QD8t68mHXApubLQi//yJ7u3 QFjLSvVpL31qxUOn6pMYtrnmHD/3oU9X7EQhWI6A/9lfPzMAQQrJR0jcTA6pdw/om5ftkbaOqWmoob I663jf9p2SgwF3wW7ZCKSTJ2SeO6SnkfbaWFgo0SAFaSCSjRksxf4g/AsrY3KxKIVgrCRpKANGBg+r pv85EqLjG5IGBtnVV/XiKMCE4HLQc9RL3jVJCrFK7KgVGoWaOSY6xPBjq5xA== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE In order to setup the DSI clock, let's make the unused VCLK2 clock path configuration via CCF. The nocache option is removed from following clocks: - vclk2_sel - vclk2_input - vclk2_div - vclk2 - vclk_div1 - vclk2_div2_en - vclk2_div4_en - vclk2_div6_en - vclk2_div12_en - vclk2_div2 - vclk2_div4 - vclk2_div6 - vclk2_div12 - cts_encl_sel vclk2 and vclk2_div uses the newly introduced vclk regmap driver to handle the enable and reset bits. In order to set a rate on cts_encl via the vclk2 clock path, the NO_REPARENT flag is set on cts_encl_sel & vclk2_sel in order to keep CCF from selection a parent. The parents of cts_encl_sel & vclk2_sel are expected to be defined in DT or manually set by the display driver at some point. The following clock scheme is to be used for DSI: xtal \_ gp0_pll_dco \_ gp0_pll |- vclk2_sel | \_ vclk2_input | \_ vclk2_div | \_ vclk2 | \_ vclk2_div1 | \_ cts_encl_sel | \_ cts_encl -> to VPU LCD Encoder |- mipi_dsi_pxclk_sel \_ mipi_dsi_pxclk_div \_ mipi_dsi_pxclk -> to DSI controller The mipi_dsi_pxclk_div is set as bypass with a single /1 entry in div_table in order to use the same GP0 for mipi_dsi_pxclk and vclk2_input. The SET_RATE_PARENT is only set on the mipi_dsi_pxclk_sel clock so the DSI bitclock is the reference base clock to calculate the vclk2_div value when pixel clock is set on the cts_encl endpoint. Signed-off-by: Neil Armstrong --- drivers/clk/meson/Kconfig | 1 + drivers/clk/meson/g12a.c | 76 ++++++++++++++++++++++++++++++++++---------= ---- 2 files changed, 57 insertions(+), 20 deletions(-) diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 8a9823789fa3..59a40a49f8e1 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -144,6 +144,7 @@ config COMMON_CLK_G12A select COMMON_CLK_MESON_EE_CLKC select COMMON_CLK_MESON_CPU_DYNDIV select COMMON_CLK_MESON_VID_PLL_DIV + select COMMON_CLK_MESON_VCLK select MFD_SYSCON help Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2 diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 90f4c6103014..df7e17c850d8 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -22,6 +22,7 @@ #include "clk-regmap.h" #include "clk-cpu-dyndiv.h" #include "vid-pll-div.h" +#include "vclk.h" #include "meson-eeclk.h" #include "g12a.h" =20 @@ -3165,7 +3166,7 @@ static struct clk_regmap g12a_vclk2_sel =3D { .ops =3D &clk_regmap_mux_ops, .parent_hws =3D g12a_vclk_parent_hws, .num_parents =3D ARRAY_SIZE(g12a_vclk_parent_hws), - .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, + .flags =3D CLK_SET_RATE_NO_REPARENT, }, }; =20 @@ -3193,7 +3194,6 @@ static struct clk_regmap g12a_vclk2_input =3D { .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &g12a_vclk2_sel.hw }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, }, }; =20 @@ -3215,19 +3215,32 @@ static struct clk_regmap g12a_vclk_div =3D { }; =20 static struct clk_regmap g12a_vclk2_div =3D { - .data =3D &(struct clk_regmap_div_data){ - .offset =3D HHI_VIID_CLK_DIV, - .shift =3D 0, - .width =3D 8, + .data =3D &(struct meson_vclk_div_data){ + .div =3D { + .reg_off =3D HHI_VIID_CLK_DIV, + .shift =3D 0, + .width =3D 8, + }, + .enable =3D { + .reg_off =3D HHI_VIID_CLK_DIV, + .shift =3D 16, + .width =3D 1, + }, + .reset =3D { + .reg_off =3D HHI_VIID_CLK_DIV, + .shift =3D 17, + .width =3D 1, + }, + .flags =3D CLK_DIVIDER_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data){ .name =3D "vclk2_div", - .ops =3D &clk_regmap_divider_ops, + .ops =3D &meson_vclk_div_ops, .parent_hws =3D (const struct clk_hw *[]) { &g12a_vclk2_input.hw }, .num_parents =3D 1, - .flags =3D CLK_GET_RATE_NOCACHE, + .flags =3D CLK_SET_RATE_GATE, }, }; =20 @@ -3246,16 +3259,24 @@ static struct clk_regmap g12a_vclk =3D { }; =20 static struct clk_regmap g12a_vclk2 =3D { - .data =3D &(struct clk_regmap_gate_data){ - .offset =3D HHI_VIID_CLK_CNTL, - .bit_idx =3D 19, + .data =3D &(struct meson_vclk_gate_data){ + .enable =3D { + .reg_off =3D HHI_VIID_CLK_CNTL, + .shift =3D 19, + .width =3D 1, + }, + .reset =3D { + .reg_off =3D HHI_VIID_CLK_CNTL, + .shift =3D 15, + .width =3D 1, + }, }, .hw.init =3D &(struct clk_init_data) { .name =3D "vclk2", - .ops =3D &clk_regmap_gate_ops, + .ops =3D &meson_vclk_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &g12a_vclk2_div.hw }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3339,7 +3360,7 @@ static struct clk_regmap g12a_vclk2_div1 =3D { .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &g12a_vclk2.hw }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3353,7 +3374,7 @@ static struct clk_regmap g12a_vclk2_div2_en =3D { .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &g12a_vclk2.hw }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3367,7 +3388,7 @@ static struct clk_regmap g12a_vclk2_div4_en =3D { .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &g12a_vclk2.hw }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3381,7 +3402,7 @@ static struct clk_regmap g12a_vclk2_div6_en =3D { .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &g12a_vclk2.hw }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3395,7 +3416,7 @@ static struct clk_regmap g12a_vclk2_div12_en =3D { .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &g12a_vclk2.hw }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3461,6 +3482,7 @@ static struct clk_fixed_factor g12a_vclk2_div2 =3D { &g12a_vclk2_div2_en.hw }, .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3474,6 +3496,7 @@ static struct clk_fixed_factor g12a_vclk2_div4 =3D { &g12a_vclk2_div4_en.hw }, .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3487,6 +3510,7 @@ static struct clk_fixed_factor g12a_vclk2_div6 =3D { &g12a_vclk2_div6_en.hw }, .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3500,6 +3524,7 @@ static struct clk_fixed_factor g12a_vclk2_div12 =3D { &g12a_vclk2_div12_en.hw }, .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3561,7 +3586,7 @@ static struct clk_regmap g12a_cts_encl_sel =3D { .ops =3D &clk_regmap_mux_ops, .parent_hws =3D g12a_cts_parent_hws, .num_parents =3D ARRAY_SIZE(g12a_cts_parent_hws), - .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, + .flags =3D CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, }, }; =20 @@ -3717,15 +3742,26 @@ static struct clk_regmap g12a_mipi_dsi_pxclk_sel = =3D { .ops =3D &clk_regmap_mux_ops, .parent_hws =3D g12a_mipi_dsi_pxclk_parent_hws, .num_parents =3D ARRAY_SIZE(g12a_mipi_dsi_pxclk_parent_hws), - .flags =3D CLK_SET_RATE_NO_REPARENT, + .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, }, }; =20 +/* + * FIXME: Force as bypass by forcing a single /1 table entry, and doensn't= on boot value + * when setting a clock whith this node in the clock path, but doesn't gar= antee the divider + * is at /1 at boot until a rate is set. + */ +static const struct clk_div_table g12a_mipi_dsi_pxclk_div_table[] =3D { + { .val =3D 0, .div =3D 1 }, + { /* sentinel */ }, +}; + static struct clk_regmap g12a_mipi_dsi_pxclk_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D HHI_MIPIDSI_PHY_CLK_CNTL, .shift =3D 0, .width =3D 7, + .table =3D g12a_mipi_dsi_pxclk_div_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "mipi_dsi_pxclk_div", --=20 2.34.1