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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-1-99ecdfdc87fc@linaro.org> References: <20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-0-99ecdfdc87fc@linaro.org> In-Reply-To: <20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-0-99ecdfdc87fc@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Martin Blumenstingl , Jerome Brunet , Kevin Hilman , Michael Turquette , Stephen Boyd , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Jagan Teki , Nicolas Belin Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, Neil Armstrong , Conor Dooley X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=886; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=N3wP+RQ7VRT4++7kCDqamWluNf4gtoR05YTHGQbChM4=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBmDQldDTI+SzRhJHYhYdxII9aDRXpw4ZQGmnVanvis mpDKm3uJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZg0JXQAKCRB33NvayMhJ0aIrEA CAjaaiTIpkxGPcKnI9vHfiZrWIDEIV5Fc17MC23AFXn9y6vUK8I6k8t8tjcY70647b9i10lUOnDW+u QTmTVl2J8iqRbWeZ0NUuJkvdiCgHXbuD9N3sJ6rRln1tpGfl6tzAsO1qDOmSoFxIzN3d1LMcisZ9IG EVOso7m5sSQYUpp1jUnx1mXDc1GS77MvuIvE7nwv1vmrkyUh53cxhK9wrFByd2ze7/fShUf2PNzW+X QDeYZbKG6/wq1fPfSCgK7mOS+IjpavXy8aWAIdNoKVvxK8vcv4EuGB2L7ityGXeqEu7h6CIFVQ1VoW oefOSy/kh9jS6GlK+SJBfSdsjHwidkgecN077CdoDspmvB0OSJTN094d0aVTTdZKLc2zbywRzs6TIz 1IHqKljLDCfdlcuI/8tWs0x7PH/cJuXfwYZ+soy/2LONuf8tgFdVXUv0mHoh516guNw7vOry4s08iN IXPc1pYAakMqeuEo4oqLXAIrcZfJtQ7vNW+0miLYAa4LSP7ZzC5fcoNpik5doys5EZDbIDAJyHBnIN duMPHjicb1tOpnatuxPEIypWYT9DuaN5h57UxiUJ9FuDmEXZxSM8XfrmiNACLVNJmIa/j3792PWKEE RfyY3lIrcz8qTs59bJCSHXyezl31JWRG8Svl2gQBFRQN62IEUU7hiTBe9aCg== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The MNT Reform 2 CM4 adapter can be populated with any Raspberry Pi CM4 compatible module such as a BPI-CM4 Module, document that. Acked-by: Conor Dooley Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/arm/amlogic.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documenta= tion/devicetree/bindings/arm/amlogic.yaml index 949537cea6be..b66b93b8bfd3 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -157,6 +157,7 @@ properties: items: - enum: - bananapi,bpi-cm4io + - mntre,reform2-cm4 - const: bananapi,bpi-cm4 - const: amlogic,a311d - const: amlogic,g12b --=20 2.34.1 From nobody Sun Dec 14 06:00:56 2025 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EEC075D47F for ; Wed, 3 Apr 2024 07:46:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.50 ARC-Seal: i=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The VCLK and VCLK_DIV clocks have supplementary bits. The VCLK gate has a "SOFT RESET" bit to toggle after the whole VCLK sub-tree rate has been set, this is implemented in the gate enable callback. The VCLK_DIV clocks as enable and reset bits used to disable and reset the divider, associated with CLK_SET_RATE_GATE it ensures the rate is set while the divider is disabled and in reset mode. The VCLK_DIV enable bit isn't implemented as a gate since it's part of the divider logic and vendor does this exact sequence to ensure the divider is correctly set. Signed-off-by: Neil Armstrong --- drivers/clk/meson/Kconfig | 4 ++ drivers/clk/meson/Makefile | 1 + drivers/clk/meson/vclk.c | 141 +++++++++++++++++++++++++++++++++++++++++= ++++ drivers/clk/meson/vclk.h | 51 ++++++++++++++++ 4 files changed, 197 insertions(+) diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 29ffd14d267b..8a9823789fa3 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -30,6 +30,10 @@ config COMMON_CLK_MESON_VID_PLL_DIV tristate select COMMON_CLK_MESON_REGMAP =20 +config COMMON_CLK_MESON_VCLK + tristate + select COMMON_CLK_MESON_REGMAP + config COMMON_CLK_MESON_CLKC_UTILS tristate =20 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 9ee4b954c896..9ba43fe7a07a 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_PLL) +=3D clk-pll.o obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) +=3D clk-regmap.o obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) +=3D sclk-div.o obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) +=3D vid-pll-div.o +obj-$(CONFIG_COMMON_CLK_MESON_VCLK) +=3D vclk.o =20 # Amlogic Clock controllers =20 diff --git a/drivers/clk/meson/vclk.c b/drivers/clk/meson/vclk.c new file mode 100644 index 000000000000..45dc216941ea --- /dev/null +++ b/drivers/clk/meson/vclk.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 Neil Armstrong + */ + +#include +#include "vclk.h" + +/* The VCLK gate has a supplementary reset bit to pulse after ungating */ + +static inline struct meson_vclk_gate_data * +clk_get_meson_vclk_gate_data(struct clk_regmap *clk) +{ + return (struct meson_vclk_gate_data *)clk->data; +} + +static int meson_vclk_gate_enable(struct clk_hw *hw) +{ + struct clk_regmap *clk =3D to_clk_regmap(hw); + struct meson_vclk_gate_data *vclk =3D clk_get_meson_vclk_gate_data(clk); + + meson_parm_write(clk->map, &vclk->enable, 1); + + /* Do a reset pulse */ + meson_parm_write(clk->map, &vclk->reset, 1); + meson_parm_write(clk->map, &vclk->reset, 0); + + return 0; +} + +static void meson_vclk_gate_disable(struct clk_hw *hw) +{ + struct clk_regmap *clk =3D to_clk_regmap(hw); + struct meson_vclk_gate_data *vclk =3D clk_get_meson_vclk_gate_data(clk); + + meson_parm_write(clk->map, &vclk->enable, 0); +} + +static int meson_vclk_gate_is_enabled(struct clk_hw *hw) +{ + struct clk_regmap *clk =3D to_clk_regmap(hw); + struct meson_vclk_gate_data *vclk =3D clk_get_meson_vclk_gate_data(clk); + + return meson_parm_read(clk->map, &vclk->enable); +} + +const struct clk_ops meson_vclk_gate_ops =3D { + .enable =3D meson_vclk_gate_enable, + .disable =3D meson_vclk_gate_disable, + .is_enabled =3D meson_vclk_gate_is_enabled, +}; +EXPORT_SYMBOL_GPL(meson_vclk_gate_ops); + +/* The VCLK Divider has supplementary reset & enable bits */ + +static inline struct meson_vclk_div_data * +clk_get_meson_vclk_div_data(struct clk_regmap *clk) +{ + return (struct meson_vclk_div_data *)clk->data; +} + +static unsigned long meson_vclk_div_recalc_rate(struct clk_hw *hw, + unsigned long prate) +{ + struct clk_regmap *clk =3D to_clk_regmap(hw); + struct meson_vclk_div_data *vclk =3D clk_get_meson_vclk_div_data(clk); + + return divider_recalc_rate(hw, prate, meson_parm_read(clk->map, &vclk->di= v), + vclk->table, vclk->flags, vclk->div.width); +} + +static int meson_vclk_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_regmap *clk =3D to_clk_regmap(hw); + struct meson_vclk_div_data *vclk =3D clk_get_meson_vclk_div_data(clk); + + return divider_determine_rate(hw, req, vclk->table, vclk->div.width, + vclk->flags); +} + +static int meson_vclk_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_regmap *clk =3D to_clk_regmap(hw); + struct meson_vclk_div_data *vclk =3D clk_get_meson_vclk_div_data(clk); + int ret; + + ret =3D divider_get_val(rate, parent_rate, vclk->table, vclk->div.width, + vclk->flags); + if (ret < 0) + return ret; + + meson_parm_write(clk->map, &vclk->div, ret); + + return 0; +}; + +static int meson_vclk_div_enable(struct clk_hw *hw) +{ + struct clk_regmap *clk =3D to_clk_regmap(hw); + struct meson_vclk_div_data *vclk =3D clk_get_meson_vclk_div_data(clk); + + /* Unreset the divider when ungating */ + meson_parm_write(clk->map, &vclk->reset, 0); + meson_parm_write(clk->map, &vclk->enable, 1); + + return 0; +} + +static void meson_vclk_div_disable(struct clk_hw *hw) +{ + struct clk_regmap *clk =3D to_clk_regmap(hw); + struct meson_vclk_div_data *vclk =3D clk_get_meson_vclk_div_data(clk); + + /* Reset the divider when gating */ + meson_parm_write(clk->map, &vclk->enable, 0); + meson_parm_write(clk->map, &vclk->reset, 1); +} + +static int meson_vclk_div_is_enabled(struct clk_hw *hw) +{ + struct clk_regmap *clk =3D to_clk_regmap(hw); + struct meson_vclk_div_data *vclk =3D clk_get_meson_vclk_div_data(clk); + + return meson_parm_read(clk->map, &vclk->enable); +} + +const struct clk_ops meson_vclk_div_ops =3D { + .recalc_rate =3D meson_vclk_div_recalc_rate, + .determine_rate =3D meson_vclk_div_determine_rate, + .set_rate =3D meson_vclk_div_set_rate, + .enable =3D meson_vclk_div_enable, + .disable =3D meson_vclk_div_disable, + .is_enabled =3D meson_vclk_div_is_enabled, +}; +EXPORT_SYMBOL_GPL(meson_vclk_div_ops); + +MODULE_DESCRIPTION("Amlogic vclk clock driver"); +MODULE_AUTHOR("Neil Armstrong "); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/meson/vclk.h b/drivers/clk/meson/vclk.h new file mode 100644 index 000000000000..20b0b181db09 --- /dev/null +++ b/drivers/clk/meson/vclk.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2024 Neil Armstrong + */ + +#ifndef __VCLK_H +#define __VCLK_H + +#include "clk-regmap.h" +#include "parm.h" + +/** + * struct meson_vclk_gate_data - vclk_gate regmap backed specific data + * + * @enable: vclk enable field + * @reset: vclk reset field + * @flags: hardware-specific flags + * + * Flags: + * Same as clk_gate except CLK_GATE_HIWORD_MASK which is ignored + */ +struct meson_vclk_gate_data { + struct parm enable; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE In order to setup the DSI clock, let's make the unused VCLK2 clock path configuration via CCF. The nocache option is removed from following clocks: - vclk2_sel - vclk2_input - vclk2_div - vclk2 - vclk_div1 - vclk2_div2_en - vclk2_div4_en - vclk2_div6_en - vclk2_div12_en - vclk2_div2 - vclk2_div4 - vclk2_div6 - vclk2_div12 - cts_encl_sel vclk2 and vclk2_div uses the newly introduced vclk regmap driver to handle the enable and reset bits. In order to set a rate on cts_encl via the vclk2 clock path, the NO_REPARENT flag is set on cts_encl_sel & vclk2_sel in order to keep CCF from selection a parent. The parents of cts_encl_sel & vclk2_sel are expected to be defined in DT or manually set by the display driver at some point. The following clock scheme is to be used for DSI: xtal \_ gp0_pll_dco \_ gp0_pll |- vclk2_sel | \_ vclk2_input | \_ vclk2_div | \_ vclk2 | \_ vclk2_div1 | \_ cts_encl_sel | \_ cts_encl -> to VPU LCD Encoder |- mipi_dsi_pxclk_sel \_ mipi_dsi_pxclk_div \_ mipi_dsi_pxclk -> to DSI controller The mipi_dsi_pxclk_div is set as bypass with a single /1 entry in div_table in order to use the same GP0 for mipi_dsi_pxclk and vclk2_input. The SET_RATE_PARENT is only set on the mipi_dsi_pxclk_sel clock so the DSI bitclock is the reference base clock to calculate the vclk2_div value when pixel clock is set on the cts_encl endpoint. Signed-off-by: Neil Armstrong --- drivers/clk/meson/Kconfig | 1 + drivers/clk/meson/g12a.c | 76 ++++++++++++++++++++++++++++++++++---------= ---- 2 files changed, 57 insertions(+), 20 deletions(-) diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 8a9823789fa3..59a40a49f8e1 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -144,6 +144,7 @@ config COMMON_CLK_G12A select COMMON_CLK_MESON_EE_CLKC select COMMON_CLK_MESON_CPU_DYNDIV select COMMON_CLK_MESON_VID_PLL_DIV + select COMMON_CLK_MESON_VCLK select MFD_SYSCON help Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2 diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 90f4c6103014..df7e17c850d8 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -22,6 +22,7 @@ #include "clk-regmap.h" #include "clk-cpu-dyndiv.h" #include "vid-pll-div.h" +#include "vclk.h" #include "meson-eeclk.h" #include "g12a.h" =20 @@ -3165,7 +3166,7 @@ static struct clk_regmap g12a_vclk2_sel =3D { .ops =3D &clk_regmap_mux_ops, .parent_hws =3D g12a_vclk_parent_hws, .num_parents =3D ARRAY_SIZE(g12a_vclk_parent_hws), - .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, + .flags =3D CLK_SET_RATE_NO_REPARENT, }, }; =20 @@ -3193,7 +3194,6 @@ static struct clk_regmap g12a_vclk2_input =3D { .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &g12a_vclk2_sel.hw }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, }, }; =20 @@ -3215,19 +3215,32 @@ static struct clk_regmap g12a_vclk_div =3D { }; =20 static struct clk_regmap g12a_vclk2_div =3D { - .data =3D &(struct clk_regmap_div_data){ - .offset =3D HHI_VIID_CLK_DIV, - .shift =3D 0, - .width =3D 8, + .data =3D &(struct meson_vclk_div_data){ + .div =3D { + .reg_off =3D HHI_VIID_CLK_DIV, + .shift =3D 0, + .width =3D 8, + }, + .enable =3D { + .reg_off =3D HHI_VIID_CLK_DIV, + .shift =3D 16, + .width =3D 1, + }, + .reset =3D { + .reg_off =3D HHI_VIID_CLK_DIV, + .shift =3D 17, + .width =3D 1, + }, + .flags =3D CLK_DIVIDER_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data){ .name =3D "vclk2_div", - .ops =3D &clk_regmap_divider_ops, + .ops =3D &meson_vclk_div_ops, .parent_hws =3D (const struct clk_hw *[]) { &g12a_vclk2_input.hw }, .num_parents =3D 1, - .flags =3D CLK_GET_RATE_NOCACHE, + .flags =3D CLK_SET_RATE_GATE, }, }; =20 @@ -3246,16 +3259,24 @@ static struct clk_regmap g12a_vclk =3D { }; =20 static struct clk_regmap g12a_vclk2 =3D { - .data =3D &(struct clk_regmap_gate_data){ - .offset =3D HHI_VIID_CLK_CNTL, - .bit_idx =3D 19, + .data =3D &(struct meson_vclk_gate_data){ + .enable =3D { + .reg_off =3D HHI_VIID_CLK_CNTL, + .shift =3D 19, + .width =3D 1, + }, + .reset =3D { + .reg_off =3D HHI_VIID_CLK_CNTL, + .shift =3D 15, + .width =3D 1, + }, }, .hw.init =3D &(struct clk_init_data) { .name =3D "vclk2", - .ops =3D &clk_regmap_gate_ops, + .ops =3D &meson_vclk_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &g12a_vclk2_div.hw }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3339,7 +3360,7 @@ static struct clk_regmap g12a_vclk2_div1 =3D { .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &g12a_vclk2.hw }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3353,7 +3374,7 @@ static struct clk_regmap g12a_vclk2_div2_en =3D { .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &g12a_vclk2.hw }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3367,7 +3388,7 @@ static struct clk_regmap g12a_vclk2_div4_en =3D { .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &g12a_vclk2.hw }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3381,7 +3402,7 @@ static struct clk_regmap g12a_vclk2_div6_en =3D { .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &g12a_vclk2.hw }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3395,7 +3416,7 @@ static struct clk_regmap g12a_vclk2_div12_en =3D { .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &g12a_vclk2.hw }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3461,6 +3482,7 @@ static struct clk_fixed_factor g12a_vclk2_div2 =3D { &g12a_vclk2_div2_en.hw }, .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3474,6 +3496,7 @@ static struct clk_fixed_factor g12a_vclk2_div4 =3D { &g12a_vclk2_div4_en.hw }, .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3487,6 +3510,7 @@ static struct clk_fixed_factor g12a_vclk2_div6 =3D { &g12a_vclk2_div6_en.hw }, .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3500,6 +3524,7 @@ static struct clk_fixed_factor g12a_vclk2_div12 =3D { &g12a_vclk2_div12_en.hw }, .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3561,7 +3586,7 @@ static struct clk_regmap g12a_cts_encl_sel =3D { .ops =3D &clk_regmap_mux_ops, .parent_hws =3D g12a_cts_parent_hws, .num_parents =3D ARRAY_SIZE(g12a_cts_parent_hws), - .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, + .flags =3D CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, }, }; =20 @@ -3717,15 +3742,26 @@ static struct clk_regmap g12a_mipi_dsi_pxclk_sel = =3D { .ops =3D &clk_regmap_mux_ops, .parent_hws =3D g12a_mipi_dsi_pxclk_parent_hws, .num_parents =3D ARRAY_SIZE(g12a_mipi_dsi_pxclk_parent_hws), - .flags =3D CLK_SET_RATE_NO_REPARENT, + .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, }, }; =20 +/* + * FIXME: Force as bypass by forcing a single /1 table entry, and doensn't= on boot value + * when setting a clock whith this node in the clock path, but doesn't gar= antee the divider + * is at /1 at boot until a rate is set. + */ +static const struct clk_div_table g12a_mipi_dsi_pxclk_div_table[] =3D { + { .val =3D 0, .div =3D 1 }, + { /* sentinel */ }, +}; + static struct clk_regmap g12a_mipi_dsi_pxclk_div =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D HHI_MIPIDSI_PHY_CLK_CNTL, .shift =3D 0, .width =3D 7, + .table =3D g12a_mipi_dsi_pxclk_div_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "mipi_dsi_pxclk_div", --=20 2.34.1 From nobody Sun Dec 14 06:00:56 2025 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFCA467A15 for ; Wed, 3 Apr 2024 07:46:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Disable the px_clk when setting the rate to recover a fully configured and correctly reset VCLK clock tree after the rate is set. Fixes: 77d9e1e6b846 ("drm/meson: add support for MIPI-DSI transceiver") Signed-off-by: Neil Armstrong Reviewed-by: Nicolas Belin --- drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c b/drivers/gpu/drm/me= son/meson_dw_mipi_dsi.c index a6bc1bdb3d0d..a10cff3ca1fe 100644 --- a/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c +++ b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c @@ -95,6 +95,7 @@ static int dw_mipi_dsi_phy_init(void *priv_data) return ret; } =20 + clk_disable_unprepare(mipi_dsi->px_clk); ret =3D clk_set_rate(mipi_dsi->px_clk, mipi_dsi->mode->clock * 1000); =20 if (ret) { @@ -103,6 +104,12 @@ static int dw_mipi_dsi_phy_init(void *priv_data) return ret; } =20 + ret =3D clk_prepare_enable(mipi_dsi->px_clk); + if (ret) { + dev_err(mipi_dsi->dev, "Failed to enable DSI Pixel clock (ret %d)\n", re= t); + return ret; + } + switch (mipi_dsi->dsi_device->format) { case MIPI_DSI_FMT_RGB888: dpi_data_format =3D DPI_COLOR_24BIT; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-5-99ecdfdc87fc@linaro.org> References: <20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-0-99ecdfdc87fc@linaro.org> In-Reply-To: <20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-0-99ecdfdc87fc@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Martin Blumenstingl , Jerome Brunet , Kevin Hilman , Michael Turquette , Stephen Boyd , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Jagan Teki , Nicolas Belin Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=3028; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=hinQajAEakYqxJaAvUFt65KdqGEthzlwyiYxmTWLSwo=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBmDQleCJepZTdvsH5P04FFdj5scoQuo3RrkBu/7LtR ovFVFJKJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZg0JXgAKCRB33NvayMhJ0awCD/ 4lGsqK7ZBrrsYwndwe68AzeslZJrfHIBwgArd/EZLEm4uE0Mimp8KnfGmCjHpv2dh53lDPDO4OyUXW TyjZKDngAKfl3cik04pPAisgFPXN1rt4snRJjOwmP6Qdrw00FM3DMJF56wcmsSarNKGCJuP5zEaxrx WTxsLsw39sem9jlgmn9lQP3NBr894+saWYaNnihjRjbD28uTZV63ixGtqRZAX0Uv+dr0G60tvufHXx aM+lm6S6v/T89y5euV7BUzGniPrwT3gbjnKvtTIZqJDC/V/wdJ2mb+SfXY0M4w5qgjduBycvJGoGVH DVEhJrncCQ1+d8MWAg41VRTzaLGhgfAu1bzWlrOTnP6LWtGAOUVGAWv/da/PYg1HvgvFWQBUPfCHsz 5aGscOZ8fAPd9DbkEdpW/Hzh2o1TZ3lBJtD/8q0I1TWwEar+co7t25cHPCrcwK1+UoKTaKGwXzbZ7L a87Eosy6L3qVChDGjEc5phAj+kTuVae4lVMjJIQiqAZvZsu+6uTZWY49N6g+jYg5n/Z/OsYnNHH5Qy oIM/jTwrHykmI9Ay1BR4RRMyk8yciDWmwpwiQxhuaEyRgBXlLkB3C218gFvjV+38kwRb0e81xonfox Vl/6+llHRMSy5eR48w4NWI9EDM96hxPfPJyDqbo17HxPpInbEPQUiLqFfLXQ== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add the MIPI DSI Analog & Digital PHY nodes and the DSI control nodes with proper port endpoint to the VPU. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 70 +++++++++++++++++++= ++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64= /boot/dts/amlogic/meson-g12-common.dtsi index 9d5eab6595d0..b058ed78faf0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -1663,9 +1663,28 @@ pwrc: power-controller { <250000000>, <0>; /* Do Nothing */ }; + + mipi_analog_dphy: phy { + compatible =3D "amlogic,g12a-mipi-dphy-analog"; + #phy-cells =3D <0>; + status =3D "disabled"; + }; }; }; =20 + mipi_dphy: phy@44000 { + compatible =3D "amlogic,axg-mipi-dphy"; + reg =3D <0x0 0x44000 0x0 0x2000>; + clocks =3D <&clkc CLKID_MIPI_DSI_PHY>; + clock-names =3D "pclk"; + resets =3D <&reset RESET_MIPI_DSI_PHY>; + reset-names =3D "phy"; + phys =3D <&mipi_analog_dphy>; + phy-names =3D "analog"; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + usb3_pcie_phy: phy@46000 { compatible =3D "amlogic,g12a-usb3-pcie-phy"; reg =3D <0x0 0x46000 0x0 0x2000>; @@ -2152,6 +2171,15 @@ hdmi_tx_out: endpoint { remote-endpoint =3D <&hdmi_tx_in>; }; }; + + /* DPI output port */ + dpi_port: port@2 { + reg =3D <2>; + + dpi_out: endpoint { + remote-endpoint =3D <&mipi_dsi_in>; + }; + }; }; =20 gic: interrupt-controller@ffc01000 { @@ -2189,6 +2217,48 @@ gpio_intc: interrupt-controller@f080 { amlogic,channel-interrupts =3D <64 65 66 67 68 69 70 71>; }; =20 + mipi_dsi: dsi@7000 { + compatible =3D "amlogic,meson-g12a-dw-mipi-dsi"; + reg =3D <0x0 0x7000 0x0 0x1000>; + resets =3D <&reset RESET_MIPI_DSI_HOST>; + reset-names =3D "top"; + clocks =3D <&clkc CLKID_MIPI_DSI_HOST>, + <&clkc CLKID_MIPI_DSI_PXCLK>, + <&clkc CLKID_CTS_ENCL>; + clock-names =3D "pclk", "bit", "px"; + phys =3D <&mipi_dphy>; + phy-names =3D "dphy"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + + assigned-clocks =3D <&clkc CLKID_MIPI_DSI_PXCLK_SEL>, + <&clkc CLKID_CTS_ENCL_SEL>, + <&clkc CLKID_VCLK2_SEL>; + assigned-clock-parents =3D <&clkc CLKID_GP0_PLL>, + <&clkc CLKID_VCLK2_DIV1>, + <&clkc CLKID_GP0_PLL>; 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Wed, 03 Apr 2024 00:46:47 -0700 (PDT) From: Neil Armstrong Date: Wed, 03 Apr 2024 09:46:37 +0200 Subject: [PATCH v12 6/7] arm64: meson: khadas-vim3l: add TS050 DSI panel overlay Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-6-99ecdfdc87fc@linaro.org> References: <20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-0-99ecdfdc87fc@linaro.org> In-Reply-To: <20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-0-99ecdfdc87fc@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Martin Blumenstingl , Jerome Brunet , Kevin Hilman , Michael Turquette , Stephen Boyd , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Jagan Teki , Nicolas Belin Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE This add dtbo overlay to support the Khadas TS050 panel on the Khadas VIM3 & VIM3L boards. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/Makefile | 4 + .../boot/dts/amlogic/meson-khadas-vim3-ts050.dtso | 108 +++++++++++++++++= ++++ 2 files changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/aml= ogic/Makefile index 1ab160bf928a..0b7961de3db7 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -16,6 +16,7 @@ dtb-$(CONFIG_ARCH_MESON) +=3D meson-g12a-u200.dtb dtb-$(CONFIG_ARCH_MESON) +=3D meson-g12a-x96-max.dtb dtb-$(CONFIG_ARCH_MESON) +=3D meson-g12b-a311d-bananapi-m2s.dtb dtb-$(CONFIG_ARCH_MESON) +=3D meson-g12b-a311d-khadas-vim3.dtb +dtb-$(CONFIG_ARCH_MESON) +=3D meson-g12b-a311d-khadas-vim3-ts050.dtb dtb-$(CONFIG_ARCH_MESON) +=3D meson-g12b-bananapi-cm4-cm4io.dtb dtb-$(CONFIG_ARCH_MESON) +=3D meson-g12b-gsking-x.dtb dtb-$(CONFIG_ARCH_MESON) +=3D meson-g12b-gtking-pro.dtb @@ -76,6 +77,7 @@ dtb-$(CONFIG_ARCH_MESON) +=3D meson-sm1-bananapi-m2-pro.d= tb dtb-$(CONFIG_ARCH_MESON) +=3D meson-sm1-bananapi-m5.dtb dtb-$(CONFIG_ARCH_MESON) +=3D meson-sm1-h96-max.dtb dtb-$(CONFIG_ARCH_MESON) +=3D meson-sm1-khadas-vim3l.dtb +dtb-$(CONFIG_ARCH_MESON) +=3D meson-sm1-khadas-vim3l-ts050.dtb dtb-$(CONFIG_ARCH_MESON) +=3D meson-sm1-s905d3-libretech-cc.dtb dtb-$(CONFIG_ARCH_MESON) +=3D meson-sm1-odroid-c4.dtb dtb-$(CONFIG_ARCH_MESON) +=3D meson-sm1-odroid-hc4.dtb @@ -86,3 +88,5 @@ dtb-$(CONFIG_ARCH_MESON) +=3D meson-sm1-x96-air.dtb # Overlays meson-g12a-fbx8am-brcm-dtbs :=3D meson-g12a-fbx8am.dtb meson-g12a-fbx8am-b= rcm.dtbo meson-g12a-fbx8am-realtek-dtbs :=3D meson-g12a-fbx8am.dtb meson-g12a-fbx8a= m-realtek.dtbo +meson-g12b-a311d-khadas-vim3-ts050-dtbs :=3D meson-g12b-a311d-khadas-vim3.= dtb meson-khadas-vim3-ts050.dtbo +meson-sm1-khadas-vim3l-ts050-dtbs :=3D meson-sm1-khadas-vim3l.dtb meson-kh= adas-vim3-ts050.dtbo diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3-ts050.dtso b/arc= h/arm64/boot/dts/amlogic/meson-khadas-vim3-ts050.dtso new file mode 100644 index 000000000000..a41b4e619580 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3-ts050.dtso @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS + * Author: Neil Armstrong + */ + +#include +#include +#include +#include +#include + +/dts-v1/; +/plugin/; + +/* + * Enable Khadas TS050 DSI Panel + Touch Controller + * on Khadas VIM3 (A311D) and VIM3L (S905D3) + */ + +&{/} { + panel_backlight: backlight { + compatible =3D "pwm-backlight"; + pwms =3D <&pwm_AO_cd 0 25000 0>; + brightness-levels =3D <0 255>; + num-interpolated-steps =3D <255>; + default-brightness-level =3D <200>; + }; +}; + +&i2c3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-0 =3D <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + touch-controller@38 { + compatible =3D "edt,edt-ft5206"; + reg =3D <0x38>; + interrupt-parent =3D <&gpio_intc>; + interrupts =3D ; + reset-gpios =3D <&gpio_expander 6 GPIO_ACTIVE_LOW>; + touchscreen-size-x =3D <1080>; + touchscreen-size-y =3D <1920>; + status =3D "okay"; + }; +}; + +&mipi_dsi { + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + assigned-clocks =3D <&clkc CLKID_GP0_PLL>, + <&clkc CLKID_MIPI_DSI_PXCLK_SEL>, + <&clkc CLKID_MIPI_DSI_PXCLK>, + <&clkc CLKID_CTS_ENCL_SEL>, + <&clkc CLKID_VCLK2_SEL>; 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Wed, 03 Apr 2024 00:46:49 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id cc13-20020a5d5c0d000000b00341b8edbe8csm14021282wrb.87.2024.04.03.00.46.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 00:46:49 -0700 (PDT) From: Neil Armstrong Date: Wed, 03 Apr 2024 09:46:38 +0200 Subject: [PATCH v12 7/7] arm64: dts: amlogic: meson-g12b-bananapi-cm4: add support for MNT Reform2 with CM4 adaper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-7-99ecdfdc87fc@linaro.org> References: <20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-0-99ecdfdc87fc@linaro.org> In-Reply-To: <20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-0-99ecdfdc87fc@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Martin Blumenstingl , Jerome Brunet , Kevin Hilman , Michael Turquette , Stephen Boyd , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Jagan Teki , Nicolas Belin Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, Neil Armstrong , "Lukas F. Hartmann" X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=9593; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=IHIbIA10M5UtZQdbmvwkCTUqisoLyeBAPmnzRRwv71g=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBmDQlfjKcZ6w/TgNlhuPFsJ9WXynXRmPP8aHXZ/SQ7 QrEKyJ6JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZg0JXwAKCRB33NvayMhJ0UC7D/ sGnZkQgfVe+li3Yv/HNLsMyeYRrBX9QeK8rjQ8gG3ouuqXzfohWfV+DgxOvV93GooMHxw8LLgGrfCJ bmOWORW/vmWNeAnkJD3D3pJ9vMvXBg0scOcHAxg8ohjR9oBQW8ID0lyObCDPqwovmFcmZ5dSQRk2CG yWzEsBoQJCIZQq4LhSZOoczEW0trDIUb4Jc7kaNokslQzak1cdTonQJuF3IvQ9GeQGXFWSzg7LdYdU QHWklV4MF0v5gRxGbEFLslWqsG0RrrmKMc5zqFzXY8SUSy7Z4q/wEnbw7Q5pgB8jfjQ6LyB71NrOOr 4pJdJYiKqhegeqgfCq98XhmMHh6wSBhL8ajdBYVfowbADW/9k9swSsDkg7htkkuZ6rS41Mjk94HRmX cDd57Iy8ONAIEwuUQHvMkY4YFF0K9hYgl/5ZONOcbZbdBlsgpg0xCT7GfUoizuMLrPIv/QcCm5Dix2 UfGVoe3y2yZKg0UwFuYj8yzGWx8nAM9Ga5Y4ssKK2JMrpS7pVA83AMAgrDdwFcmKHFc0FkJImsGhIp bVK3P9KokxXlyXZghQufxejK47iOUEpNV7fOdxyued2GbVZPVEdtrYUra8SupIo+M+MJKb5bdEJJm2 aTWqYducG2Xq/2mHOuSVHip945WVyXsy6we3RPStsrWXblg1dirkmheQsAEA== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE This adds a basic devicetree for the MNT Reform2 DIY laptop when using a CM4 adapter and a BPI-CM4 module. Co-developed-by: Lukas F. Hartmann Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../meson-g12b-bananapi-cm4-mnt-reform2.dts | 384 +++++++++++++++++= ++++ 2 files changed, 385 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/aml= ogic/Makefile index 0b7961de3db7..d525e5123fbc 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -18,6 +18,7 @@ dtb-$(CONFIG_ARCH_MESON) +=3D meson-g12b-a311d-bananapi-m= 2s.dtb dtb-$(CONFIG_ARCH_MESON) +=3D meson-g12b-a311d-khadas-vim3.dtb dtb-$(CONFIG_ARCH_MESON) +=3D meson-g12b-a311d-khadas-vim3-ts050.dtb dtb-$(CONFIG_ARCH_MESON) +=3D meson-g12b-bananapi-cm4-cm4io.dtb +dtb-$(CONFIG_ARCH_MESON) +=3D meson-g12b-bananapi-cm4-mnt-reform2.dtb dtb-$(CONFIG_ARCH_MESON) +=3D meson-g12b-gsking-x.dtb dtb-$(CONFIG_ARCH_MESON) +=3D meson-g12b-gtking-pro.dtb dtb-$(CONFIG_ARCH_MESON) +=3D meson-g12b-gtking.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-mnt-reform= 2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-mnt-reform2.dts new file mode 100644 index 000000000000..003efed529ba --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-mnt-reform2.dts @@ -0,0 +1,384 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Neil Armstrong + * Copyright 2023 MNT Research GmbH + */ + +/dts-v1/; + +#include "meson-g12b-bananapi-cm4.dtsi" +#include +#include +#include + +/ { + model =3D "MNT Reform 2 with BPI-CM4 Module"; + compatible =3D "mntre,reform2-cm4", "bananapi,bpi-cm4", "amlogic,a311d", = "amlogic,g12b"; + chassis-type =3D "laptop"; + + aliases { + ethernet0 =3D ðmac; + i2c0 =3D &i2c1; + i2c1 =3D &i2c3; + }; + + hdmi_connector: hdmi-connector { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint =3D <&hdmi_tx_tmds_out>; + }; + }; + }; + + leds { + compatible =3D "gpio-leds"; + + led-blue { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + + led-green { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + }; + }; + + sound { + compatible =3D "amlogic,axg-sound-card"; + model =3D "MNT-REFORM2-BPI-CM4"; + audio-widgets =3D "Headphone", "Headphone Jack", + "Speaker", "External Speaker", + "Microphone", "Mic Jack"; + audio-aux-devs =3D <&tdmout_a>, <&tdmout_b>, <&tdmin_b>; + audio-routing =3D "TDMOUT_A IN 0", "FRDDR_A OUT 0", + "TDMOUT_A IN 1", "FRDDR_B OUT 0", + "TDMOUT_A IN 2", "FRDDR_C OUT 0", + "TDM_A Playback", "TDMOUT_A OUT", + "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT", + "TDMIN_B IN 1", "TDM_B Capture", + "TDMIN_B IN 4", "TDM_B Loopback", + "TODDR_A IN 1", "TDMIN_B OUT", + "TODDR_B IN 1", "TDMIN_B OUT", + "TODDR_C IN 1", "TDMIN_B OUT", + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "External Speaker", "SPK_LP", + "External Speaker", "SPK_LN", + "External Speaker", "SPK_RP", + "External Speaker", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + + assigned-clocks =3D <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents =3D <0>, <0>, <0>; + assigned-clock-rates =3D <294912000>, + <270950400>, + <393216000>; + + dai-link-0 { + sound-dai =3D <&frddr_a>; + }; + + dai-link-1 { + sound-dai =3D <&frddr_b>; + }; + + dai-link-2 { + sound-dai =3D <&frddr_c>; + }; + + dai-link-3 { + sound-dai =3D <&toddr_a>; + }; + + dai-link-4 { + sound-dai =3D <&toddr_b>; + }; + + dai-link-5 { + sound-dai =3D <&toddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-6 { + sound-dai =3D <&tdmif_a>; + dai-format =3D "i2s"; + dai-tdm-slot-tx-mask-0 =3D <1 1>; + dai-tdm-slot-tx-mask-1 =3D <1 1>; + dai-tdm-slot-tx-mask-2 =3D <1 1>; + dai-tdm-slot-tx-mask-3 =3D <1 1>; + mclk-fs =3D <256>; + + codec { + sound-dai =3D <&tohdmitx TOHDMITX_I2S_IN_A>; + }; + }; + + /* Analog Audio */ + dai-link-7 { + sound-dai =3D <&tdmif_b>; + dai-format =3D "i2s"; + dai-tdm-slot-tx-mask-0 =3D <1 1>; + mclk-fs =3D <256>; + + codec { + sound-dai =3D <&wm8960>; + }; + }; + + /* hdmi glue */ + dai-link-8 { + sound-dai =3D <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai =3D <&hdmi_tx>; + }; + }; + }; + + reg_main_1v8: regulator-main-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "1V8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <®_main_3v3>; + }; + + reg_main_1v2: regulator-main-1v2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "1V2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + vin-supply =3D <®_main_5v>; + }; + + reg_main_3v3: regulator-main-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + reg_main_5v: regulator-main-5v { + compatible =3D "regulator-fixed"; + regulator-name =3D "5V"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; + + reg_main_usb: regulator-main-usb { + compatible =3D "regulator-fixed"; + regulator-name =3D "USB_PWR"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <®_main_5v>; + }; + + backlight: backlight { + compatible =3D "pwm-backlight"; + pwms =3D <&pwm_AO_ab 0 10000 0>; + power-supply =3D <®_main_usb>; + enable-gpios =3D <&gpio 58 GPIO_ACTIVE_HIGH>; + brightness-levels =3D <0 32 64 128 160 200 255>; + default-brightness-level =3D <6>; + }; + + panel { + compatible =3D "innolux,n125hce-gn1"; + power-supply =3D <®_main_3v3>; + backlight =3D <&backlight>; + no-hpd; + + port { + panel_in: endpoint { + remote-endpoint =3D <&edp_bridge_out>; + }; + }; + }; + + clock_12288: clock_12288 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <12288000>; + }; +}; + +&mipi_analog_dphy { + status =3D "okay"; +}; + +&mipi_dphy { + status =3D "okay"; +}; + +&mipi_dsi { + status =3D "okay"; + + assigned-clocks =3D <&clkc CLKID_GP0_PLL>, + <&clkc CLKID_MIPI_DSI_PXCLK_SEL>, + <&clkc CLKID_MIPI_DSI_PXCLK>, + <&clkc CLKID_CTS_ENCL_SEL>, + <&clkc CLKID_VCLK2_SEL>; + assigned-clock-parents =3D <0>, + <&clkc CLKID_GP0_PLL>, + <0>, + <&clkc CLKID_VCLK2_DIV1>, + <&clkc CLKID_GP0_PLL>; + assigned-clock-rates =3D <936000000>, + <0>, + <936000000>, + <0>, + <0>; +}; + +&mipi_dsi_panel_port { + mipi_dsi_out: endpoint { + remote-endpoint =3D <&edp_bridge_in>; + }; +}; + +&cecb_AO { + status =3D "okay"; +}; + +ðmac { + status =3D "okay"; +}; + +&hdmi_tx { + status =3D "okay"; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint =3D <&hdmi_connector_in>; + }; +}; + +&pwm_AO_ab { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm_ao_a_pins>; + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; +}; + +&i2c3 { + status =3D "okay"; + + edp_bridge: bridge@2c { + compatible =3D "ti,sn65dsi86"; + reg =3D <0x2c>; + enable-gpios =3D <&gpio GPIOX_10 GPIO_ACTIVE_HIGH>; // PIN_24 / GPIO8 + vccio-supply =3D <®_main_1v8>; + vpll-supply =3D <®_main_1v8>; + vcca-supply =3D <®_main_1v2>; + vcc-supply =3D <®_main_1v2>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + edp_bridge_in: endpoint { + remote-endpoint =3D <&mipi_dsi_out>; + }; + }; + + port@1 { + reg =3D <1>; + + edp_bridge_out: endpoint { + remote-endpoint =3D <&panel_in>; + }; + }; + }; + }; +}; + +&i2c2 { + status =3D "okay"; + + wm8960: codec@1a { + compatible =3D "wlf,wm8960"; + reg =3D <0x1a>; + clocks =3D <&clock_12288>; + clock-names =3D "mclk"; + #sound-dai-cells =3D <0>; + wlf,shared-lrclk; + }; + + rtc@68 { + compatible =3D "nxp,pcf8523"; + reg =3D <0x68>; + }; +}; + +&pcie { + status =3D "okay"; +}; + +&sd_emmc_b { + status =3D "okay"; +}; + +&tdmif_a { + status =3D "okay"; +}; + +&tdmout_a { + status =3D "okay"; +}; + +&tdmif_b { + pinctrl-0 =3D <&tdm_b_dout0_pins>, <&tdm_b_fs_pins>, <&tdm_b_sclk_pins>, = <&tdm_b_din1_pins>; + pinctrl-names =3D "default"; + + assigned-clocks =3D <&clkc_audio AUD_CLKID_TDM_SCLK_PAD1>, + <&clkc_audio AUD_CLKID_TDM_LRCLK_PAD1>; + assigned-clock-parents =3D <&clkc_audio AUD_CLKID_MST_B_SCLK>, + <&clkc_audio AUD_CLKID_MST_B_LRCLK>; + assigned-clock-rates =3D <0>, <0>; +}; + +&tdmin_b { + status =3D "okay"; +}; + +&toddr_a { + status =3D "okay"; +}; + +&toddr_b { + status =3D "okay"; +}; + +&toddr_c { + status =3D "okay"; +}; + +&tohdmitx { + status =3D "okay"; +}; + +&usb { + dr_mode =3D "host"; + + status =3D "okay"; +}; --=20 2.34.1