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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240401-typec-fix-sm8250-v3-2-604dce3ad103@linaro.org> References: <20240401-typec-fix-sm8250-v3-0-604dce3ad103@linaro.org> In-Reply-To: <20240401-typec-fix-sm8250-v3-0-604dce3ad103@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss , Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1954; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=IMnWMrJva5plwLKTtuiDtd3gpNM3ZSgoTVFSaJx002Y=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmCxokl48aMrRfcnGP2EioDchgzKMMzRkz1bCnC Qq6Lw/2wA2JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZgsaJAAKCRCLPIo+Aiko 1TFvB/9DaGH7PaDMd7tL6ZfnEx2zIwbNyJGTtoRLHBcECwwFXGUe8lty1f0SffKkWCiXJRZL0X3 jYmEPPcMWuPLyW/tbY3Mc5xPcKDG+7LsQSHwqbEg+sHwZ+W1khjkzEWKNaxw7uXb+Itrc0kzinm 0kDG+srL8Ijgm7AhwbetFyveTrCnAFHysyQV6ivhmrwOiaVDBO0xmKkBd4Egp1+5LHQDkVqSpJH gxt2RcMyb46pCLPFQSalMyfvSrvK3nT8H+kXO12tA/9s5lSqS+nfQ9GRMJ/bhyXuLj7wloH9NRz IP2oy4fQaBzFswwgMJYG2cZdEVtKg0LQ6RGADjcqwiCtYNLe X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Correct the clocks being used by the display clock controller on the SC8180X platform (to match the schema): - Drop the sleep clock - Add DSI clocks - Reorder eDP / DP clocks This changes the order of clocks, however it should be noted that the clock list was neither correct nor followed the schema beforehand. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qc= om/sc8180x.dtsi index 32afc78d5b76..a086dbe0d910 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -3267,21 +3267,27 @@ dispcc: clock-controller@af00000 { compatible =3D "qcom,sc8180x-dispcc"; reg =3D <0 0x0af00000 0 0x20000>; clocks =3D <&rpmhcc RPMH_CXO_CLK>, - <&sleep_clk>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>, - <&usb_sec_dpphy 0>, - <&usb_sec_dpphy 1>, <&edp_phy 0>, - <&edp_phy 1>; + <&edp_phy 1>, + <&usb_sec_dpphy 0>, + <&usb_sec_dpphy 1>; clock-names =3D "bi_tcxo", - "sleep_clk", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", "dp_phy_pll_link_clk", "dp_phy_pll_vco_div_clk", - "dptx1_phy_pll_link_clk", - "dptx1_phy_pll_vco_div_clk", "edp_phy_pll_link_clk", - "edp_phy_pll_vco_div_clk"; + "edp_phy_pll_vco_div_clk", + "dptx1_phy_pll_link_clk", + "dptx1_phy_pll_vco_div_clk"; power-domains =3D <&rpmhpd SC8180X_MMCX>; required-opps =3D <&rpmhpd_opp_low_svs>; #clock-cells =3D <1>; --=20 2.39.2