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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id g16-20020a170906539000b00a46dd1f7dc1sm1869942ejo.92.2024.03.29.05.14.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 05:14:19 -0700 (PDT) From: =?UTF-8?q?Christoph=20M=C3=BCllner?= To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Albert Ou , Philipp Tomsich , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Daniel Henrique Barboza , Heiko Stuebner , Cooper Qu , Zhiwei Liu , Huang Tao , Alistair Francis , Andrew Jones , Conor Dooley , Qingfang Deng , Alexandre Ghiti Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v2 1/2] riscv: thead: Rename T-Head PBMT to MAEE Date: Fri, 29 Mar 2024 13:14:13 +0100 Message-ID: <20240329121414.688391-2-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240329121414.688391-1-christoph.muellner@vrull.eu> References: <20240329121414.688391-1-christoph.muellner@vrull.eu> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable T-Head's vendor extension to set page attributes has the name MAEE (MMU address attribute extension). Let's rename it, so it is clear what this referes to. See also: https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadmae= e.adoc Signed-off-by: Christoph M=C3=BCllner Reviewed-by: Conor Dooley --- arch/riscv/Kconfig.errata | 8 ++++---- arch/riscv/errata/thead/errata.c | 8 ++++---- arch/riscv/include/asm/errata_list.h | 20 ++++++++++---------- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index 910ba8837add..2c24bef7e112 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -82,14 +82,14 @@ config ERRATA_THEAD =20 Otherwise, please say "N" here to avoid unnecessary overhead. =20 -config ERRATA_THEAD_PBMT - bool "Apply T-Head memory type errata" +config ERRATA_THEAD_MAEE + bool "Apply T-Head's MMU address attribute (MAEE)" depends on ERRATA_THEAD && 64BIT && MMU select RISCV_ALTERNATIVE_EARLY default y help - This will apply the memory type errata to handle the non-standard - memory type bits in page-table-entries on T-Head SoCs. + This will apply the memory type errata to handle T-Head's MMU address + attribute extension (MAEE). =20 If you don't know what to do here, say "Y". =20 diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/err= ata.c index b1c410bbc1ae..8c8a8a4b0421 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -19,10 +19,10 @@ #include #include =20 -static bool errata_probe_pbmt(unsigned int stage, +static bool errata_probe_maee(unsigned int stage, unsigned long arch_id, unsigned long impid) { - if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT)) + if (!IS_ENABLED(CONFIG_ERRATA_THEAD_MAEE)) return false; =20 if (arch_id !=3D 0 || impid !=3D 0) @@ -140,8 +140,8 @@ static u32 thead_errata_probe(unsigned int stage, { u32 cpu_req_errata =3D 0; =20 - if (errata_probe_pbmt(stage, archid, impid)) - cpu_req_errata |=3D BIT(ERRATA_THEAD_PBMT); + if (errata_probe_maee(stage, archid, impid)) + cpu_req_errata |=3D BIT(ERRATA_THEAD_MAEE); =20 errata_probe_cmo(stage, archid, impid); =20 diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/= errata_list.h index ea33288f8a25..7c377e137b41 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -23,7 +23,7 @@ #endif =20 #ifdef CONFIG_ERRATA_THEAD -#define ERRATA_THEAD_PBMT 0 +#define ERRATA_THEAD_MAEE 0 #define ERRATA_THEAD_PMU 1 #define ERRATA_THEAD_NUMBER 2 #endif @@ -53,20 +53,20 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_V= ENDOR_ID, \ * in the default case. */ #define ALT_SVPBMT_SHIFT 61 -#define ALT_THEAD_PBMT_SHIFT 59 +#define ALT_THEAD_MAEE_SHIFT 59 #define ALT_SVPBMT(_val, prot) \ asm(ALTERNATIVE_2("li %0, 0\t\nnop", \ "li %0, %1\t\nslli %0,%0,%3", 0, \ RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \ "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID, \ - ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \ + ERRATA_THEAD_MAEE, CONFIG_ERRATA_THEAD_MAEE) \ : "=3Dr"(_val) \ : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), \ - "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT), \ + "I"(prot##_THEAD >> ALT_THEAD_MAEE_SHIFT), \ "I"(ALT_SVPBMT_SHIFT), \ - "I"(ALT_THEAD_PBMT_SHIFT)) + "I"(ALT_THEAD_MAEE_SHIFT)) =20 -#ifdef CONFIG_ERRATA_THEAD_PBMT +#ifdef CONFIG_ERRATA_THEAD_MAEE /* * IO/NOCACHE memory types are handled together with svpbmt, * so on T-Head chips, check if no other memory type is set, @@ -83,11 +83,11 @@ asm volatile(ALTERNATIVE( \ "slli t3, t3, %3\n\t" \ "or %0, %0, t3\n\t" \ "2:", THEAD_VENDOR_ID, \ - ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \ + ERRATA_THEAD_MAEE, CONFIG_ERRATA_THEAD_MAEE) \ : "+r"(_val) \ - : "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_PBMT_SHIFT), \ - "I"(_PAGE_PMA_THEAD >> ALT_THEAD_PBMT_SHIFT), \ - "I"(ALT_THEAD_PBMT_SHIFT) \ + : "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_MAEE_SHIFT), \ + "I"(_PAGE_PMA_THEAD >> ALT_THEAD_MAEE_SHIFT), \ + "I"(ALT_THEAD_MAEE_SHIFT) \ : "t3") #else #define ALT_THEAD_PMA(_val) --=20 2.44.0