From nobody Sun Feb 8 20:22:58 2026 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F27607F46C for ; Thu, 28 Mar 2024 12:34:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711629288; cv=none; b=oG7UFc/OLeaozV555thHcUsgjryM4VMu/XS1Kp06Ae7jopGWpf2OHJw9NnRIT+oCFbupXIBg7CG+Z2dBsNLEQKJhcYi8d2hrtlvkmelE7kwsAuaE/X+jT6PJWHndsW6QraCVruj6OmxPJ/0oP7X1SKDjKs/SgeSyTyo6DpXiAKk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711629288; c=relaxed/simple; bh=nbNp3qfZWcDDvV1zUWwDB7cZvmbMHfTCHJLRRggYk9A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Lri4o6jduWeRMF6PdeXmcnd/xLCxQgo4i1HXty0knZoOP36zUuRZIhmFuEH3PRZ3JRTcD9EY05XD3f8t5q5IdH2Wj0W5qVgp24KL816HmQc/h2QF4a8YCUWIHwaFhXvUCw6j0hVh8C13/GCKZrd5G3F7tY85/kCOrrbXgSAgWi8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=rttbFsEk; arc=none smtp.client-ip=209.85.221.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="rttbFsEk" Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-33ed7ef0ae8so610083f8f.0 for ; Thu, 28 Mar 2024 05:34:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1711629285; x=1712234085; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RjhTo09dO/7V38CJBlOuZewKYi9PkSHGMjLUhNN+TaQ=; b=rttbFsEkfE0WCDfh3IHrfdeHpOA+l9B+onZ7v/4MfjceKF4580RqC0Jql5iXxyOjQB fjve1+5WcnSPKyOjff1037BjJSIUmKHzFOiakpymVP9Tr4eIjZNqavRGZmrgqk9nvnYm 0jFlmILn0rONktVqMV+wf6mAgsQlR1So7vqPu3/OY9ypcFVpr02aw+GFP9XAk8nYjzE0 WUB8qU5Fo14c58bRuitkgDmAn7oMl4RTBwgiXrqM8YkmTMVz9JPpLvJMWkWf8AdJYH+h K58KCQIzpIuFkCfvNs3VzODAR4fL4h+yJ+IL3wOnWTCfp4w7wbs8WLSMf3Cp4/WC7iI/ CPsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711629285; x=1712234085; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RjhTo09dO/7V38CJBlOuZewKYi9PkSHGMjLUhNN+TaQ=; b=EazBH1vxfJ94wvs3cJDu+toJ6czK4V47CwTjRiVYNiuT7seNqS3XeLBuc7HcWsTTDn +gmDG/66n8SKBakLSER6JiRWgfqjRWAyaPsdt2+pWfi7eNiXFv8IOhVgW/YjjGrbI7HX rUUkTUM6l8SSbPdRtRNHsrKIfJfdJr8wH+jOjXgDhJX2SPvYjMP2kuIIq07FIX2eFgP8 UmXrBgAVZjzObagoU2Jf3naQLZinM1mVHkSn9JNhloO9Q1wIzwZ3OYTPHYD1krPrf+Uq jPKpxCakZiculOtt8ldbZNvaolffLkcQ7B9ljBIPoA5fWkWbVVIGoZQP7uu8/e1DSxCz E+sQ== X-Forwarded-Encrypted: i=1; AJvYcCUU7OVt5591HUTN2SPrjhzBOWqGfmp3OGw2WKfo6DDjvWwOtswnWz4ng60qsI5so3Bm3ddNy5uw82R4iQGoKRDsknSakMhaNBBRvQvC X-Gm-Message-State: AOJu0Yx+mhiBxHDNasyI9BjQGRVDw9NlF7hNsSBYVhZUtafuPEVhc+Td 0bfURFE9+6yuMalwx/kKo5YEToY61IDPT0qMW+JARr5lIR7CO+ozYtc0mD2KDio= X-Google-Smtp-Source: AGHT+IEeEXB2tNCVWGb87xNYSbBQDlb72910RZrNwEk6zjsX5DNZR0GunhOGsmBaPuzi8NH9mWDR+g== X-Received: by 2002:a5d:4ccc:0:b0:342:2ea8:18fa with SMTP id c12-20020a5d4ccc000000b003422ea818famr2188036wrt.15.1711629285483; Thu, 28 Mar 2024 05:34:45 -0700 (PDT) Received: from ta2.c.googlers.com.com (158.100.79.34.bc.googleusercontent.com. [34.79.100.158]) by smtp.gmail.com with ESMTPSA id u6-20020adfa186000000b00341e2146b53sm1639671wru.106.2024.03.28.05.34.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 05:34:45 -0700 (PDT) From: Tudor Ambarus To: peter.griffin@linaro.org, krzysztof.kozlowski@linaro.org Cc: alim.akhtar@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, willmcvicker@google.com, kernel-team@android.com, s.nawrocki@samsung.com, cw00.choi@samsung.com, mturquette@baylibre.com, sboyd@kernel.org, semen.protsenko@linaro.org, linux-clk@vger.kernel.org, jaewon02.kim@samsung.com, Tudor Ambarus Subject: [PATCH v3 1/3] clk: samsung: introduce nMUX for MUX clks that can reparented Date: Thu, 28 Mar 2024 12:34:38 +0000 Message-ID: <20240328123440.1387823-2-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.44.0.396.g6e790dbe36-goog In-Reply-To: <20240328123440.1387823-1-tudor.ambarus@linaro.org> References: <20240328123440.1387823-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All samsung MUX clocks that are defined with MUX() set the CLK_SET_RATE_NO_REPARENT flag in __MUX(), which prevents MUXes to be reparented during clk_set_rate(). Introduce nMUX() for MUX clocks that can be reparented on clock rate change. "nMUX" comes from "n-to-1 selector", hopefully emphasising that the selector can change on clock rate changes. Ideally MUX/MUX_F() should change to not have the CLK_SET_RATE_NO_REPARENT flag set by default, and all their users to be updated to add the flag back (like in the case of DIV and GATE). But this is a very intrusive change and because for now only GS101 allows MUX reparenting on clock rate change, stick with nMUX(). One user of nMUX() will be GS101. GS101 defines MUX clocks that are dedicated for each instance of an IP (see MUX USI). The reparenting of these MUX clocks will not affect other instances of the same IP or different IPs altogether. Signed-off-by: Tudor Ambarus Reviewed-by: Andr=C3=A9 Draszik --- drivers/clk/samsung/clk.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index a70bd7cce39f..fb06caa71f0a 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -133,7 +133,7 @@ struct samsung_mux_clock { .name =3D cname, \ .parent_names =3D pnames, \ .num_parents =3D ARRAY_SIZE(pnames), \ - .flags =3D (f) | CLK_SET_RATE_NO_REPARENT, \ + .flags =3D f, \ .offset =3D o, \ .shift =3D s, \ .width =3D w, \ @@ -141,9 +141,16 @@ struct samsung_mux_clock { } =20 #define MUX(_id, cname, pnames, o, s, w) \ - __MUX(_id, cname, pnames, o, s, w, 0, 0) + __MUX(_id, cname, pnames, o, s, w, CLK_SET_RATE_NO_REPARENT, 0) =20 #define MUX_F(_id, cname, pnames, o, s, w, f, mf) \ + __MUX(_id, cname, pnames, o, s, w, (f) | CLK_SET_RATE_NO_REPARENT, mf) + +/* Used by MUX clocks where reparenting on clock rate change is allowed. */ +#define nMUX(_id, cname, pnames, o, s, w) \ + __MUX(_id, cname, pnames, o, s, w, 0, 0) + +#define nMUX_F(_id, cname, pnames, o, s, w, f, mf) \ __MUX(_id, cname, pnames, o, s, w, f, mf) =20 /** --=20 2.44.0.396.g6e790dbe36-goog From nobody Sun Feb 8 20:22:58 2026 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF3747F476 for ; Thu, 28 Mar 2024 12:34:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711629290; cv=none; b=IR5PZljNyhAv2aX2cbeIvF5myaWWEVPmaKZVJgyggE9Qg30EKQeODnXll54dHBrys9p9p3xcd2O1Yl6VgMM7C6j40IpplpDVLLwZo43S0/iGrLVvVeMXw9T4Kvc74I4AVlmWeSCoklOjmAgpPmv/mPf+7EcUMVCwq/RWaXLmqtc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711629290; c=relaxed/simple; bh=G9rajGk0d4ZQFcRW6N7DSPqkzn3MfbXX+XgYTkYr7rE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nHtexqoHfN+vtwlPeDBha5MUoPrqFl2ghB7r/WFMVCOGIWycI4Zqdki155UcnhrhBThNo5c3FVAojLteZDwcGeHp+dvKzQW5SYVfKJ42mhF+BvZcqfZBbwhCN7vI69ii3SUZSetovv12pZixFDUbiTBDGzNH6hEKMsfAwQWB+lY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=L2LVcLxM; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="L2LVcLxM" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-4141156f245so6395375e9.2 for ; Thu, 28 Mar 2024 05:34:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1711629286; x=1712234086; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T+QixHXzYFVjgJw5tBEGG1f8mkq14aJzxd8vq8TimAA=; b=L2LVcLxMcRoO1TyXkv7FeF1xtRZTtZvrNE45QhlsNT9fF4OpaQBAxGI4hasc7UwnsC ouySrmGOmbx2Y94dMbuyaMV0y1woS8WycLbcSKbOjIsl+z4JOU/3avY4SaEjIyxPTRco hmuSBiwWaxX32YJC5ADmDhs7UrjWod5FLUh4kr8d7W7C9SrHCyL9HxMw8Grh4RNzzcyc vXhPkWRRmTo2qHEVlM72xxqGpCZbBrEu4alxU17zWJt16Eb2cRnL9VfvrWw2YGQNOMzh YdFIdnZoEWC8GvYljamSaDEPgPxmipCRgTuAgyHTvw+cdVeqMRqXd4aZeGX2M79qaDKA eWVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711629286; x=1712234086; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T+QixHXzYFVjgJw5tBEGG1f8mkq14aJzxd8vq8TimAA=; b=q0D57cMZSDVNsrYx9RX8P6BWnYUuNmnrl82W0V6jjeQYc8qrhmlqLKo1aoJOELkAed 2YFLrHTPvhipmekbGkLzykUyhgzSXx2dGPE0wT3EfWzAeODIFJFU1p4WORjTtqDXfLId FZXawDTSrRbdCOfcdAynOfVzyF0lAP259ahgtzqu7d6Qc3GFj7TH6lIa0fIn+b7EcuDw Vt5GFMtMx+LzFLSqMbya7ol+nHPF7msqVPztvk3p4P5fyfJ1uckyDNVbl4XyYWEC7kKg 4URb+rIp9fVx7mw5ugcYsbhUiMhLHRJo/6SwtAa95Fx7q/+n2S6udG3YPW5ZPF2EDZN2 JixQ== X-Forwarded-Encrypted: i=1; AJvYcCWzM8Ed/vU3lGkrjnFNjWoUmNVGpvzBo272AOaVaPOCbmWZATKhduMXOGoCfZlUwrTFiUP0HBf4ud77qXNke+XqladkKE5/WhcyH9bV X-Gm-Message-State: AOJu0Yw4lueslcZqGLGf5+eyci2XNg+IReMkNIjAazKdocl4pmrECHBv hquE9emBYner/FUyL/QTjJSZF/jxsP1rEcYrDtkAxHox6JG1hfBS/TiOrO9NN12tn+yrpBG3bHv E X-Google-Smtp-Source: AGHT+IEg9bXN3pX43iAB0Sl1xHuJwsJg1t2ngWepln87O+0j1btTlnVLBn8xAFxqRjumR0gBJD0eJw== X-Received: by 2002:a05:600c:4e8e:b0:414:8065:2d23 with SMTP id f14-20020a05600c4e8e00b0041480652d23mr2331235wmq.20.1711629286314; Thu, 28 Mar 2024 05:34:46 -0700 (PDT) Received: from ta2.c.googlers.com.com (158.100.79.34.bc.googleusercontent.com. [34.79.100.158]) by smtp.gmail.com with ESMTPSA id u6-20020adfa186000000b00341e2146b53sm1639671wru.106.2024.03.28.05.34.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 05:34:45 -0700 (PDT) From: Tudor Ambarus To: peter.griffin@linaro.org, krzysztof.kozlowski@linaro.org Cc: alim.akhtar@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, willmcvicker@google.com, kernel-team@android.com, s.nawrocki@samsung.com, cw00.choi@samsung.com, mturquette@baylibre.com, sboyd@kernel.org, semen.protsenko@linaro.org, linux-clk@vger.kernel.org, jaewon02.kim@samsung.com, Tudor Ambarus Subject: [PATCH v3 2/3] clk: samsung: gs101: propagate PERIC1 USI SPI clock rate Date: Thu, 28 Mar 2024 12:34:39 +0000 Message-ID: <20240328123440.1387823-3-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.44.0.396.g6e790dbe36-goog In-Reply-To: <20240328123440.1387823-1-tudor.ambarus@linaro.org> References: <20240328123440.1387823-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable When SPI transfer is being prepared, the spi-s3c64xx driver will call clk_set_rate() to change the rate of SPI source clock (IPCLK). But IPCLK is a gate (leaf) clock, so it must propagate the rate change up the clock tree, so that corresponding MUX/DIV clocks can actually change their values. Add CLK_SET_RATE_PARENT flag to corresponding clocks for all USI instances in GS101 PERIC1: USI{0, 9, 10, 11, 12, 13}. This change involves the following clocks: PERIC1 USI*: Clock Div range MUX Selection ------------------------------------------------------------------- gout_peric1_peric1_top0_ipclk_* - - dout_peric1_usi*_usi /1..16 - mout_peric1_usi*_usi_user - {24.5 MHz, 400 MHz} With input clock of 400 MHz this scheme provides the following IPCLK rate range, for each USI block: PERIC1 USI*: 1.5 MHz ... 400 MHz Accounting for internal /4 divider in SPI blocks, and because the max SPI frequency is limited at 50 MHz, it gives us next SPI SCK rates: PERIC1 USI_SPI*: 384 KHz ... 49.9 MHz Which shall be fine for the applications of the SPI bus. Note that with this we allow the reparenting of the MUX_USIx clocks to OSCCLK. Each instance of the USI IP has its own MUX_USI clock, thus the reparenting of a MUX_USI clock corresponds to a single instance of the USI IP. The datasheet mentions OSCCLK just in the low-power mode context, but the downstream driver reparents too the MUX_USI clocks to OSCCLK. Follow the downstream driver and do the same. Fixes: 63b4bd1259d9 ("clk: samsung: gs101: add support for cmu_peric1") Reviewed-by: Peter Griffin Acked-by: Andr=C3=A9 Draszik Signed-off-by: Tudor Ambarus --- drivers/clk/samsung/clk-gs101.c | 90 ++++++++++++++++++--------------- 1 file changed, 48 insertions(+), 42 deletions(-) diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs10= 1.c index d065e343a85d..ddf2d57eed68 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -3230,47 +3230,53 @@ static const struct samsung_mux_clock peric1_mux_cl= ks[] __initconst =3D { MUX(CLK_MOUT_PERIC1_I3C_USER, "mout_peric1_i3c_user", mout_peric1_nonbususer_p, PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, 4, 1), - MUX(CLK_MOUT_PERIC1_USI0_USI_USER, - "mout_peric1_usi0_usi_user", mout_peric1_nonbususer_p, - PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 4, 1), - MUX(CLK_MOUT_PERIC1_USI10_USI_USER, - "mout_peric1_usi10_usi_user", mout_peric1_nonbususer_p, - PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4, 1), - MUX(CLK_MOUT_PERIC1_USI11_USI_USER, - "mout_peric1_usi11_usi_user", mout_peric1_nonbususer_p, - PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4, 1), - MUX(CLK_MOUT_PERIC1_USI12_USI_USER, - "mout_peric1_usi12_usi_user", mout_peric1_nonbususer_p, - PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4, 1), - MUX(CLK_MOUT_PERIC1_USI13_USI_USER, - "mout_peric1_usi13_usi_user", mout_peric1_nonbususer_p, - PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 4, 1), - MUX(CLK_MOUT_PERIC1_USI9_USI_USER, - "mout_peric1_usi9_usi_user", mout_peric1_nonbususer_p, - PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 4, 1), + nMUX(CLK_MOUT_PERIC1_USI0_USI_USER, + "mout_peric1_usi0_usi_user", mout_peric1_nonbususer_p, + PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 4, 1), + nMUX(CLK_MOUT_PERIC1_USI10_USI_USER, + "mout_peric1_usi10_usi_user", mout_peric1_nonbususer_p, + PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4, 1), + nMUX(CLK_MOUT_PERIC1_USI11_USI_USER, + "mout_peric1_usi11_usi_user", mout_peric1_nonbususer_p, + PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4, 1), + nMUX(CLK_MOUT_PERIC1_USI12_USI_USER, + "mout_peric1_usi12_usi_user", mout_peric1_nonbususer_p, + PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4, 1), + nMUX(CLK_MOUT_PERIC1_USI13_USI_USER, + "mout_peric1_usi13_usi_user", mout_peric1_nonbususer_p, + PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 4, 1), + nMUX(CLK_MOUT_PERIC1_USI9_USI_USER, + "mout_peric1_usi9_usi_user", mout_peric1_nonbususer_p, + PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 4, 1), }; =20 static const struct samsung_div_clock peric1_div_clks[] __initconst =3D { DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c", "mout_peric1_i3c_user", CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4), - DIV(CLK_DOUT_PERIC1_USI0_USI, - "dout_peric1_usi0_usi", "mout_peric1_usi0_usi_user", - CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 0, 4), - DIV(CLK_DOUT_PERIC1_USI10_USI, - "dout_peric1_usi10_usi", "mout_peric1_usi10_usi_user", - CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4), - DIV(CLK_DOUT_PERIC1_USI11_USI, - "dout_peric1_usi11_usi", "mout_peric1_usi11_usi_user", - CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4), - DIV(CLK_DOUT_PERIC1_USI12_USI, - "dout_peric1_usi12_usi", "mout_peric1_usi12_usi_user", - CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4), - DIV(CLK_DOUT_PERIC1_USI13_USI, - "dout_peric1_usi13_usi", "mout_peric1_usi13_usi_user", - CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 0, 4), - DIV(CLK_DOUT_PERIC1_USI9_USI, - "dout_peric1_usi9_usi", "mout_peric1_usi9_usi_user", - CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 0, 4), + DIV_F(CLK_DOUT_PERIC1_USI0_USI, + "dout_peric1_usi0_usi", "mout_peric1_usi0_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 0, 4, + CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_PERIC1_USI10_USI, + "dout_peric1_usi10_usi", "mout_peric1_usi10_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4, + CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_PERIC1_USI11_USI, + "dout_peric1_usi11_usi", "mout_peric1_usi11_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4, + CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_PERIC1_USI12_USI, + "dout_peric1_usi12_usi", "mout_peric1_usi12_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4, + CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_PERIC1_USI13_USI, + "dout_peric1_usi13_usi", "mout_peric1_usi13_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 0, 4, + CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_PERIC1_USI9_USI, + "dout_peric1_usi9_usi", "mout_peric1_usi9_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 0, 4, + CLK_SET_RATE_PARENT, 0), }; =20 static const struct samsung_gate_clock peric1_gate_clks[] __initconst =3D { @@ -3305,27 +3311,27 @@ static const struct samsung_gate_clock peric1_gate_= clks[] __initconst =3D { GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1, "gout_peric1_peric1_top0_ipclk_1", "dout_peric1_usi0_usi", CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1, - 21, 0, 0), + 21, CLK_SET_RATE_PARENT, 0), GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2, "gout_peric1_peric1_top0_ipclk_2", "dout_peric1_usi9_usi", CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2, - 21, 0, 0), + 21, CLK_SET_RATE_PARENT, 0), GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3, "gout_peric1_peric1_top0_ipclk_3", "dout_peric1_usi10_usi", CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3, - 21, 0, 0), + 21, CLK_SET_RATE_PARENT, 0), GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4, "gout_peric1_peric1_top0_ipclk_4", "dout_peric1_usi11_usi", CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4, - 21, 0, 0), + 21, CLK_SET_RATE_PARENT, 0), GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5, "gout_peric1_peric1_top0_ipclk_5", "dout_peric1_usi12_usi", CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5, - 21, 0, 0), + 21, CLK_SET_RATE_PARENT, 0), GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6, "gout_peric1_peric1_top0_ipclk_6", "dout_peric1_usi13_usi", CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6, - 21, 0, 0), + 21, CLK_SET_RATE_PARENT, 0), GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8, "gout_peric1_peric1_top0_ipclk_8", "dout_peric1_i3c", CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8, --=20 2.44.0.396.g6e790dbe36-goog From nobody Sun Feb 8 20:22:58 2026 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A494D7F487 for ; Thu, 28 Mar 2024 12:34:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711629291; cv=none; b=pHXsz4IfpM7aQDOnYQ5WJdmS8zXhqVK32w52voUPi4HqrsiJ0PbEhbVjYdrHue6K9KXaSk9bbk5OqpgwPN4/nMqrgN14VobmvDUcJ3Z0uUrhAUQrEfK46voYfGq5rCMs7Q/nN18iynHiYlHlnOmF2XM+W80NMQ0kVaxWAbsoDdY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711629291; c=relaxed/simple; bh=AeymmzYOVhV6ILBFdgZM5v3j4YNp4ZKQ8Dg8Z67qRwA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XGwdvwVYiS/UKmRXSj5LVZ1z2V+LucQKEC9AbTLUUTzZstFrMaTlbspnYNScYfMyjAj8y0CTz2uDn/n8SzXZfQMaQIONl1LUIvDDVEz4HLcUclwHj25tuTrb+vJvYBzX0NOcCr0pujnXCOcnTJ5FvT82cNBPUiCqLhJf6IlmWo8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=ONX2w3L4; arc=none smtp.client-ip=209.85.221.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ONX2w3L4" Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-34261edaf7eso581620f8f.1 for ; Thu, 28 Mar 2024 05:34:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1711629287; x=1712234087; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JZ0vv1wQnvryEwq3rhsZ/X7XAHDM6osgJBQ005R7xBw=; b=ONX2w3L455L8KoxKD9jWmjLDD2nSQEGNGeiZ59OHdMGvw/0+V2JTpV3IWJsMTlT9DR kzVy4DMrffviUkxyN82HQd6qc+aD2D5DXoYytqmFgqPuBU36lJ8UYT0Lp2+foJOmCTdj /FOV+SzOPc/NNmXmnzOxg+Tu00zKDzNM+OaneAazQfJcH89uSvO8n2zqS1jWn7FbvKAo mKO1jmNvb9KaoVOOIcaFDrdgACTVcKjCD1T5qexjpl+p0UErRPtbAi2iyRL1JszvBY+9 goJPCCB1WOHOR8xeaCZzwsZYz+OGhostpJLuTQg+MS/q4zI26H+PhmtOASj4urBvsqnf 7N4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711629287; x=1712234087; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JZ0vv1wQnvryEwq3rhsZ/X7XAHDM6osgJBQ005R7xBw=; b=m1koy4G9Oxihc3Zt8qdcUV8LrfD27ZphfxwSnaUcMThNTP8K4Y/+6QiFlOJkErCMaL RhbCYl25SouPRV7nI0+I9cxH+7yyY/O6ukbn7nwE6sD4S+z3sBpy4tgZCgMFJd8Ovvqx uxt/+WIhJIQknCyAoouwvVV1grbp4SOI3+cTca4lT4hEMFESdnms+EcjFP/Xu5XR5Hsd DoIfZiJdva6cCyor4FSJWwJVoKLUTF1YP9PTDMpoLb5RhSERJ9SZ4zZQGZ/U7U1bxZjD RpkPt8IXQDkRzo4nhvvTZkz4ocb6/tWQCu65fN24ueFS+Wpt9LIEoTGTxXAhhgqxo5sn Uwyw== X-Forwarded-Encrypted: i=1; AJvYcCV1nAI1jdaYuDjbclSU9ai2PiP6Q9cX66HeOr6xzgpCd5/D4P9qcsKIA1S3oMLzz+LqiExowPQt7zfESV2ZnnXRvjAWem1xyflgHFmv X-Gm-Message-State: AOJu0YybbsMU/95ArapDBhKQd1OlHhxpLiT7lJ6xW3IfpOt8KUxpOwqw iklNkvIkjGSvvNrAJLqUEzk/KdKn2yhx5Ouh9I9U51IrU1e0OEwTpe4qmP/1i5Y= X-Google-Smtp-Source: AGHT+IGFNHOP84yRVpbydpE4oIv0WdGd/p3WZ93Ua0lXB3ARSXpZbu2w0NOolGbkZr9E3N7yAevC1g== X-Received: by 2002:a5d:64ef:0:b0:341:b846:9b5d with SMTP id g15-20020a5d64ef000000b00341b8469b5dmr2770700wri.52.1711629286962; Thu, 28 Mar 2024 05:34:46 -0700 (PDT) Received: from ta2.c.googlers.com.com (158.100.79.34.bc.googleusercontent.com. [34.79.100.158]) by smtp.gmail.com with ESMTPSA id u6-20020adfa186000000b00341e2146b53sm1639671wru.106.2024.03.28.05.34.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 05:34:46 -0700 (PDT) From: Tudor Ambarus To: peter.griffin@linaro.org, krzysztof.kozlowski@linaro.org Cc: alim.akhtar@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, willmcvicker@google.com, kernel-team@android.com, s.nawrocki@samsung.com, cw00.choi@samsung.com, mturquette@baylibre.com, sboyd@kernel.org, semen.protsenko@linaro.org, linux-clk@vger.kernel.org, jaewon02.kim@samsung.com, Tudor Ambarus Subject: [PATCH v3 3/3] clk: samsung: gs101: propagate PERIC0 USI SPI clock rate Date: Thu, 28 Mar 2024 12:34:40 +0000 Message-ID: <20240328123440.1387823-4-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.44.0.396.g6e790dbe36-goog In-Reply-To: <20240328123440.1387823-1-tudor.ambarus@linaro.org> References: <20240328123440.1387823-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable When SPI transfer is being prepared, the spi-s3c64xx driver will call clk_set_rate() to change the rate of SPI source clock (IPCLK). But IPCLK is a gate (leaf) clock, so it must propagate the rate change up the clock tree, so that corresponding MUX/DIV clocks can actually change their values. Add CLK_SET_RATE_PARENT flag to corresponding clocks for all USI instances in GS101 PERIC0: USI{1-8, 14}. This change involves the following clocks: PERIC0 USI*: Clock Div range MUX Selection ------------------------------------------------------------------- gout_peric0_peric0_top0_ipclk_* - - dout_peric0_usi*_usi /1..16 - mout_peric0_usi*_usi_user - {24.5 MHz, 400 MHz} With input clock of 400 MHz this scheme provides the following IPCLK rate range, for each USI block: PERIC0 USI*: 1.5 MHz ... 400 MHz Accounting for internal /4 divider in SPI blocks, and because the max SPI frequency is limited at 50 MHz, it gives us next SPI SCK rates: PERIC0 USI_SPI*: 384 KHz ... 49.9 MHz Which shall be fine for the applications of the SPI bus. Note that with this we allow the reparenting of the MUX_USIx clocks to OSCCLK. Each instance of the USI IP has its own MUX_USI clock, thus the reparenting of a MUX_USI clock corresponds to a single instance of the USI IP. The datasheet mentions OSCCLK just in the low-power mode context, but the downstream driver reparents too the MUX_USI clocks to OSCCLK. Follow the downstream driver and do the same. Fixes: 893f133a040b ("clk: samsung: gs101: add support for cmu_peric0") Reviewed-by: Peter Griffin Acked-by: Andr=C3=A9 Draszik Signed-off-by: Tudor Ambarus --- drivers/clk/samsung/clk-gs101.c | 135 +++++++++++++++++--------------- 1 file changed, 72 insertions(+), 63 deletions(-) diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs10= 1.c index ddf2d57eed68..bd3c1b02715b 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -2763,33 +2763,33 @@ static const struct samsung_mux_clock peric0_mux_cl= ks[] __initconst =3D { MUX(CLK_MOUT_PERIC0_USI0_UART_USER, "mout_peric0_usi0_uart_user", mout_peric0_usi0_uart_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, 4, 1), - MUX(CLK_MOUT_PERIC0_USI14_USI_USER, - "mout_peric0_usi14_usi_user", mout_peric0_usi_usi_user_p, - PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 4, 1), - MUX(CLK_MOUT_PERIC0_USI1_USI_USER, - "mout_peric0_usi1_usi_user", mout_peric0_usi_usi_user_p, - PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 4, 1), - MUX(CLK_MOUT_PERIC0_USI2_USI_USER, - "mout_peric0_usi2_usi_user", mout_peric0_usi_usi_user_p, - PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 4, 1), - MUX(CLK_MOUT_PERIC0_USI3_USI_USER, - "mout_peric0_usi3_usi_user", mout_peric0_usi_usi_user_p, - PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 4, 1), - MUX(CLK_MOUT_PERIC0_USI4_USI_USER, - "mout_peric0_usi4_usi_user", mout_peric0_usi_usi_user_p, - PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 4, 1), - MUX(CLK_MOUT_PERIC0_USI5_USI_USER, - "mout_peric0_usi5_usi_user", mout_peric0_usi_usi_user_p, - PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 4, 1), - MUX(CLK_MOUT_PERIC0_USI6_USI_USER, - "mout_peric0_usi6_usi_user", mout_peric0_usi_usi_user_p, - PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 4, 1), - MUX(CLK_MOUT_PERIC0_USI7_USI_USER, - "mout_peric0_usi7_usi_user", mout_peric0_usi_usi_user_p, - PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 4, 1), - MUX(CLK_MOUT_PERIC0_USI8_USI_USER, - "mout_peric0_usi8_usi_user", mout_peric0_usi_usi_user_p, - PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 4, 1), + nMUX(CLK_MOUT_PERIC0_USI14_USI_USER, + "mout_peric0_usi14_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 4, 1), + nMUX(CLK_MOUT_PERIC0_USI1_USI_USER, + "mout_peric0_usi1_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 4, 1), + nMUX(CLK_MOUT_PERIC0_USI2_USI_USER, + "mout_peric0_usi2_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 4, 1), + nMUX(CLK_MOUT_PERIC0_USI3_USI_USER, + "mout_peric0_usi3_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 4, 1), + nMUX(CLK_MOUT_PERIC0_USI4_USI_USER, + "mout_peric0_usi4_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 4, 1), + nMUX(CLK_MOUT_PERIC0_USI5_USI_USER, + "mout_peric0_usi5_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 4, 1), + nMUX(CLK_MOUT_PERIC0_USI6_USI_USER, + "mout_peric0_usi6_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 4, 1), + nMUX(CLK_MOUT_PERIC0_USI7_USI_USER, + "mout_peric0_usi7_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 4, 1), + nMUX(CLK_MOUT_PERIC0_USI8_USI_USER, + "mout_peric0_usi8_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 4, 1), }; =20 static const struct samsung_div_clock peric0_div_clks[] __initconst =3D { @@ -2798,33 +2798,42 @@ static const struct samsung_div_clock peric0_div_cl= ks[] __initconst =3D { DIV(CLK_DOUT_PERIC0_USI0_UART, "dout_peric0_usi0_uart", "mout_peric0_usi0_uart_user", CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, 0, 4), - DIV(CLK_DOUT_PERIC0_USI14_USI, - "dout_peric0_usi14_usi", "mout_peric0_usi14_usi_user", - CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 4), - DIV(CLK_DOUT_PERIC0_USI1_USI, - "dout_peric0_usi1_usi", "mout_peric0_usi1_usi_user", - CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 0, 4), - DIV(CLK_DOUT_PERIC0_USI2_USI, - "dout_peric0_usi2_usi", "mout_peric0_usi2_usi_user", - CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 0, 4), - DIV(CLK_DOUT_PERIC0_USI3_USI, - "dout_peric0_usi3_usi", "mout_peric0_usi3_usi_user", - CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 0, 4), - DIV(CLK_DOUT_PERIC0_USI4_USI, - "dout_peric0_usi4_usi", "mout_peric0_usi4_usi_user", - CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 0, 4), - DIV(CLK_DOUT_PERIC0_USI5_USI, - "dout_peric0_usi5_usi", "mout_peric0_usi5_usi_user", - CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 0, 4), - DIV(CLK_DOUT_PERIC0_USI6_USI, - "dout_peric0_usi6_usi", "mout_peric0_usi6_usi_user", - CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 0, 4), - DIV(CLK_DOUT_PERIC0_USI7_USI, - "dout_peric0_usi7_usi", "mout_peric0_usi7_usi_user", - CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI, 0, 4), - DIV(CLK_DOUT_PERIC0_USI8_USI, - "dout_peric0_usi8_usi", "mout_peric0_usi8_usi_user", - CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 0, 4), + DIV_F(CLK_DOUT_PERIC0_USI14_USI, + "dout_peric0_usi14_usi", "mout_peric0_usi14_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 4, + CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_PERIC0_USI1_USI, + "dout_peric0_usi1_usi", "mout_peric0_usi1_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 0, 4, + CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_PERIC0_USI2_USI, + "dout_peric0_usi2_usi", "mout_peric0_usi2_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 0, 4, + CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_PERIC0_USI3_USI, + "dout_peric0_usi3_usi", "mout_peric0_usi3_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 0, 4, + CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_PERIC0_USI4_USI, + "dout_peric0_usi4_usi", "mout_peric0_usi4_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 0, 4, + CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_PERIC0_USI5_USI, + "dout_peric0_usi5_usi", "mout_peric0_usi5_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 0, 4, + CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_PERIC0_USI6_USI, + "dout_peric0_usi6_usi", "mout_peric0_usi6_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 0, 4, + CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_PERIC0_USI7_USI, + "dout_peric0_usi7_usi", "mout_peric0_usi7_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI, 0, 4, + CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_PERIC0_USI8_USI, + "dout_peric0_usi8_usi", "mout_peric0_usi8_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 0, 4, + CLK_SET_RATE_PARENT, 0), }; =20 static const struct samsung_gate_clock peric0_gate_clks[] __initconst =3D { @@ -2857,11 +2866,11 @@ static const struct samsung_gate_clock peric0_gate_= clks[] __initconst =3D { GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0, "gout_peric0_peric0_top0_ipclk_0", "dout_peric0_usi1_usi", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0, - 21, 0, 0), + 21, CLK_SET_RATE_PARENT, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1, "gout_peric0_peric0_top0_ipclk_1", "dout_peric0_usi2_usi", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1, - 21, 0, 0), + 21, CLK_SET_RATE_PARENT, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10, "gout_peric0_peric0_top0_ipclk_10", "dout_peric0_i3c", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, @@ -2889,27 +2898,27 @@ static const struct samsung_gate_clock peric0_gate_= clks[] __initconst =3D { GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2, "gout_peric0_peric0_top0_ipclk_2", "dout_peric0_usi3_usi", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2, - 21, 0, 0), + 21, CLK_SET_RATE_PARENT, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3, "gout_peric0_peric0_top0_ipclk_3", "dout_peric0_usi4_usi", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3, - 21, 0, 0), + 21, CLK_SET_RATE_PARENT, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4, "gout_peric0_peric0_top0_ipclk_4", "dout_peric0_usi5_usi", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, - 21, 0, 0), + 21, CLK_SET_RATE_PARENT, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5, "gout_peric0_peric0_top0_ipclk_5", "dout_peric0_usi6_usi", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, - 21, 0, 0), + 21, CLK_SET_RATE_PARENT, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6, "gout_peric0_peric0_top0_ipclk_6", "dout_peric0_usi7_usi", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, - 21, 0, 0), + 21, CLK_SET_RATE_PARENT, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7, "gout_peric0_peric0_top0_ipclk_7", "dout_peric0_usi8_usi", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, - 21, 0, 0), + 21, CLK_SET_RATE_PARENT, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8, "gout_peric0_peric0_top0_ipclk_8", "dout_peric0_i3c", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, @@ -2990,7 +2999,7 @@ static const struct samsung_gate_clock peric0_gate_cl= ks[] __initconst =3D { GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2, "gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, - 21, 0, 0), + 21, CLK_SET_RATE_PARENT, 0), /* Disabling this clock makes the system hang. Mark the clock as critical= . */ GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0, "gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user", --=20 2.44.0.396.g6e790dbe36-goog