From nobody Tue Feb 10 16:22:11 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E560657DF; Thu, 28 Mar 2024 09:51:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711619485; cv=none; b=ARB0SJQrWA/VA3Mk7cEYEb3k+gF5n9dP0oIvaiT2vCYhdejMMOQmQ7ADyup5NfJfBij/TcQlVLnqraHLVoHiJfUpCFG9Ll0qlXPb4m5TYswBMqaH33q8Wy4FIoz/oGeDCynP6HHD9WaOmHpwaTXmbKew05++anGAyo90nIhlNlw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711619485; c=relaxed/simple; bh=HW6UgJ0Yn1O1XybEUZA+ryIToNj1u5oAyKa2XNpiUGs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=htRUFvpEpqQPBivLBi6IqHg5WPGvIcoHWgp6zYa0MGAyZNRgnHug7BOEiz1E0FNUm3aLbM+fxABxv/ftBdMCURHYCGiidLrgK/ztC9KJqLabn1bOeK+wVTsVa8EFNTvlG2WiOz9N/8JoXlEcXmNRwkeOijwdaxnb/FaVV2Affjo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=LxLev44s; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="LxLev44s" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42S9oc4Q029027; Thu, 28 Mar 2024 09:51:16 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=474CTIUKYJidvKspytIRb41aOV/RpzaCy1VVbecv9wE=; b=Lx Lev44svIaIZt2rZMLkSEIlEDFVJ3PpsGQPemSXlTYW84c6qI5xlGQAnpZ5HXb5a/ KK+6qlhPjUghTcDGxwjuR4JQJvkmdNVck42PBVxn2yjpP/4KGGV7FckfhbnTZZFw xL+G0QgcqI+nkiYjm994crvenBeNXIVXxbhSNYjeGWt1EkOTMyiBzvIi/MByJhFs Vf3T+VoNuexKBVSBJpvuZyTtaBGFWoNGlQOHeYNV1nQ4R51ksK/R94/3o+UPh9kZ j/Kgx06A3V/ww3yYMH48ZMDmiukAi1+UVQJwHP46OtsM3KUBffVt0uKnjicBRzgt ZhiF+ReU9jGlti59St2w== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3x54r60cbh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 28 Mar 2024 09:51:15 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 42S9pETZ019381 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 28 Mar 2024 09:51:14 GMT Received: from hu-sibis-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 28 Mar 2024 02:51:09 -0700 From: Sibi Sankar To: , , , , , , CC: , , , , , , , , , Subject: [PATCH 1/5] dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings Date: Thu, 28 Mar 2024 15:20:40 +0530 Message-ID: <20240328095044.2926125-2-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240328095044.2926125-1-quic_sibis@quicinc.com> References: <20240328095044.2926125-1-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: obBQLGU22vcf_wpTzamyum-UGQrwjCOk X-Proofpoint-ORIG-GUID: obBQLGU22vcf_wpTzamyum-UGQrwjCOk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-28_09,2024-03-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 priorityscore=1501 clxscore=1015 lowpriorityscore=0 malwarescore=0 bulkscore=0 suspectscore=0 impostorscore=0 spamscore=0 mlxlogscore=941 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2403280066 Content-Type: text/plain; charset="utf-8" Add devicetree binding for CPUSS Control Processor (CPUCP) mailbox controller. Signed-off-by: Sibi Sankar Reviewed-by: Rob Herring --- rfc: * Use x1e80100 as the fallback for future SoCs using the cpucp-mbox controller. [Krzysztoff/Konrad/Rob] .../bindings/mailbox/qcom,cpucp-mbox.yaml | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/qcom,cpucp-mb= ox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml= b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml new file mode 100644 index 000000000000..491b0a05e630 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. CPUCP Mailbox Controller + +maintainers: + - Sibi Sankar + +description: + The CPUSS Control Processor (CPUCP) mailbox controller enables communica= tion + between AP and CPUCP by acting as a doorbell between them. + +properties: + compatible: + items: + - const: qcom,x1e80100-cpucp-mbox + + reg: + items: + - description: CPUCP rx register region + - description: CPUCP tx register region + + interrupts: + maxItems: 1 + + "#mbox-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include + + mailbox@17430000 { + compatible =3D "qcom,x1e80100-cpucp-mbox"; + reg =3D <0x17430000 0x10000>, <0x18830000 0x10000>; + interrupts =3D ; + #mbox-cells =3D <1>; + }; --=20 2.34.1