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[34.125.198.4]) by smtp.gmail.com with UTF8SMTPSA id si13-20020a17090b528d00b0029fe0b8859fsm3602158pjb.1.2024.03.27.13.27.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Mar 2024 13:27:44 -0700 (PDT) From: Stephen Boyd To: Michael Turquette , Stephen Boyd , Bjorn Andersson Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, patches@lists.linux.dev, linux-arm-msm@vger.kernel.org, Dmitry Baryshkov , Douglas Anderson , Taniya Das Subject: [PATCH 1/2] clk: qcom: dispcc-sc7180: Force off rotator clk at probe Date: Wed, 27 Mar 2024 13:27:37 -0700 Message-ID: <20240327202740.3075378-2-swboyd@chromium.org> X-Mailer: git-send-email 2.44.0.478.gd926399ef9-goog In-Reply-To: <20240327202740.3075378-1-swboyd@chromium.org> References: <20240327202740.3075378-1-swboyd@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The 'disp_cc_mdss_rot_clk' is parented to 'disp_cc_pll0' and enabled out of boot on sc7180 Trogdor devices. This is a problem because the mdss driver (the driver for compatible node "qcom,sc7180-mdss") turns off 'disp_cc_mdss_mdp_clk' and that clk is also parented to 'disp_cc_pll0'. When the display pll turns off, the rotator clk gets stuck on. We don't really care about this clk being on through boot, so simply disable the clk during driver probe to avoid this issue. Cc: Bjorn Andersson Cc: Dmitry Baryshkov Cc: Douglas Anderson Cc: Taniya Das Signed-off-by: Stephen Boyd --- drivers/clk/qcom/dispcc-sc7180.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7= 180.c index 9536bfc72a43..a3356a7758b3 100644 --- a/drivers/clk/qcom/dispcc-sc7180.c +++ b/drivers/clk/qcom/dispcc-sc7180.c @@ -705,6 +705,20 @@ static int disp_cc_sc7180_probe(struct platform_device= *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); =20 + /* + * Force off 'disp_cc_mdss_rot_clk' so that the driver for the + * "qcom,sc7180-mdss" compatible node can disable + * 'disp_cc_mdss_mdp_clk', which in turn disables 'disp_cc_pll0', + * without making this clk stuck on. When the mdss driver runtime + * suspends, the mdss_gdsc will turn off. If 'disp_cc_mdss_rot_clk' + * isn't off or parked on XO at this time it will wedge the GDSC and + * then 'disp_cc_mdss_mdp_clk' will fail to turn on because the GDSC is + * wedged. + */ + regmap_update_bits(regmap, + disp_cc_mdss_rot_clk.clkr.enable_reg, + disp_cc_mdss_rot_clk.clkr.enable_mask, 0); + /* 1380MHz configuration */ disp_cc_pll_config.l =3D 0x47; disp_cc_pll_config.alpha =3D 0xe000; --=20 https://chromeos.dev