From nobody Sun Feb 8 02:22:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5B8D176537; Wed, 27 Mar 2024 12:22:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711542178; cv=none; b=cjNCiezHUscJev60U9ECnLR3NMgqw4tcnf9s8K/P8t4E5KXLnEHrCSTZVcbYW7ulqMCTh/Ymx8S1BThjr+FswDPklBLjGzJCGlIKYSVq8LgZT15kD7s03dIYTzutWxCgrTQ9WnhA1aRQKoyZN3IMrmMFCwKYEyMSWRTwuYP3k30= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711542178; c=relaxed/simple; bh=+s+pN/A/h4IYsr8OpbqLK5tUDQPzp3B9zQiyDAsIRbw=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=PbZfcpR+AgV87IyY1U54h8TfNVE2RV9B1P/SrD9c0mtOspD1thrwOtJCZHXfHzhAqiw4pQ4XGzoJnExs/nPkwUqCAGcX8k8+1ZfMj599dkCkdh5yQ15h275lvsFqOkQDlLwn6AV14ZUWst2bFQwowKmVDCnWUsj1Rt+38EYpZeI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VaDlmTRt; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VaDlmTRt" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7A415C43394; Wed, 27 Mar 2024 12:22:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711542178; bh=+s+pN/A/h4IYsr8OpbqLK5tUDQPzp3B9zQiyDAsIRbw=; h=From:To:Cc:Subject:Date:From; b=VaDlmTRthSlZB4/zr5FstRtMYPrtOpOZjBK45y4nTc/c1hJ9Xtcg+cPyO9JwrWc+F TXdxxEjgPboz1D1/48MsOUoVHOhrZNuKurFuq2NuqEAD+zEv9arKvMRyURykuj1IvX 4KrUZ7lGM3GUOlKIWmY7DAhgMzfF/DvPwETtmSNgtiLXqcAM4dOQP/U05xJld6kizD LDPHZWYrWhyD9Mn3iQ+A2iy+p/rP9mwafL5DYn5177wY7LCmaICI3E/qVFqcL3UAJl bMsDhFniNiITmIJz8uTiU9P+cAsrQrukUndDaZOWy+JkNhUMNkUXwFgHIb/T1sFYkA XVwQKsnEviMPA== From: Sasha Levin To: stable@vger.kernel.org, wenjing.liu@amd.com Cc: Mario Limonciello , Alex Deucher , Alvin Lee , Alex Hung , Daniel Wheeler , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: FAILED: Patch "drm/amd/display: Lock all enabled otg pipes even with no planes" failed to apply to 5.4-stable tree Date: Wed, 27 Mar 2024 08:22:56 -0400 Message-ID: <20240327122256.2838095-1-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Hint: ignore X-stable: review Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch below does not apply to the 5.4-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to . Thanks, Sasha Acked-by: Alex Hung Reviewed-by: Alvin Lee Tested-by: Daniel Wheeler ------------------ original commit in Linus's tree ------------------ From 94040c2cbb1a872ff779da06bf034ccfee0f9cba Mon Sep 17 00:00:00 2001 From: Wenjing Liu Date: Fri, 23 Feb 2024 15:17:39 -0500 Subject: [PATCH] drm/amd/display: Lock all enabled otg pipes even with no planes [WHY] On DCN32 we support dynamic ODM even when OTG is blanked. When ODM configuration is dynamically changed and the OTG is on blank pattern, we will need to reprogram OPP's test pattern based on new ODM configuration. Therefore we need to lock the OTG pipe to avoid temporary corruption when we are reprogramming OPP blank patterns. [HOW] Add a new interdependent update lock implementation to lock all enabled OTG pipes even when there is no plane on the OTG for DCN32. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Alvin Lee Acked-by: Alex Hung Signed-off-by: Wenjing Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- .../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 23 +++++++++++++++++++ .../amd/display/dc/hwss/dcn32/dcn32_hwseq.h | 2 ++ .../amd/display/dc/hwss/dcn32/dcn32_init.c | 2 +- 3 files changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/driv= ers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index b890db0bfc46b..c0b526cf17865 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -1785,3 +1785,26 @@ void dcn32_prepare_bandwidth(struct dc *dc, context->bw_ctx.bw.dcn.clk.p_state_change_support =3D p_state_change_sup= port; } } + +void dcn32_interdependent_update_lock(struct dc *dc, + struct dc_state *context, bool lock) +{ + unsigned int i; + struct pipe_ctx *pipe; + struct timing_generator *tg; + + for (i =3D 0; i < dc->res_pool->pipe_count; i++) { + pipe =3D &context->res_ctx.pipe_ctx[i]; + tg =3D pipe->stream_res.tg; + + if (!resource_is_pipe_type(pipe, OTG_MASTER) || + !tg->funcs->is_tg_enabled(tg) || + dc_state_get_pipe_subvp_type(context, pipe) =3D=3D SUBVP_PHANTOM) + continue; + + if (lock) + dc->hwss.pipe_control_lock(dc, pipe, true); + else + dc->hwss.pipe_control_lock(dc, pipe, false); + } +} diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h b/driv= ers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h index 069e20bc87c0a..f55c11fc56ec7 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h @@ -129,4 +129,6 @@ bool dcn32_is_pipe_topology_transition_seamless(struct = dc *dc, void dcn32_prepare_bandwidth(struct dc *dc, struct dc_state *context); =20 +void dcn32_interdependent_update_lock(struct dc *dc, + struct dc_state *context, bool lock); #endif /* __DC_HWSS_DCN32_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c b/drive= rs/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c index 2b073123d3ede..67d661dbd5b7c 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c @@ -58,7 +58,7 @@ static const struct hw_sequencer_funcs dcn32_funcs =3D { .disable_plane =3D dcn20_disable_plane, .disable_pixel_data =3D dcn20_disable_pixel_data, .pipe_control_lock =3D dcn20_pipe_control_lock, - .interdependent_update_lock =3D dcn10_lock_all_pipes, + .interdependent_update_lock =3D dcn32_interdependent_update_lock, .cursor_lock =3D dcn10_cursor_lock, .prepare_bandwidth =3D dcn32_prepare_bandwidth, .optimize_bandwidth =3D dcn20_optimize_bandwidth, --=20 2.43.0