From nobody Sun Feb 8 02:22:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB56117497F; Wed, 27 Mar 2024 12:22:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711542154; cv=none; b=QKV70KvXEoxDd+E+Y15c4ZpBfMSBJPFJfiZsAmqCqXgzREe7xsosf/aBnUnAPauq86M8shAUDzA3qcoZisV7zJVmAlUJoxNf5nMz/bvVppBhopIyBEIDTeNAcZwIYLcHSlnRmzV6DNZvVeXzYr8iLbx2Tg/5Hy9nSV5tK4IWY7E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711542154; c=relaxed/simple; bh=eW8v2rqK+YW7ryQK88To+Q6LwmDjw4ITv8QOonCo04E=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=YxS/LwWWUbMrNNsPxm0bHGMeeg6X5B64kE2k49xvOmZ+PdGLGHboetnfSEyqajWPZq/HxiZ2D17FcVWEla7eBlrO/6dnqLa0LHpQ7rCgAxOjOWGQ6AbUPd1tt7XTSTO/JBwSfdEhm8hrS4YgBG4lEoEa5YQuGSYicogoQfNDzBA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bhIZ0Y3k; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bhIZ0Y3k" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A6B9AC433F1; Wed, 27 Mar 2024 12:22:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711542153; bh=eW8v2rqK+YW7ryQK88To+Q6LwmDjw4ITv8QOonCo04E=; h=From:To:Cc:Subject:Date:From; b=bhIZ0Y3kWn0YpHSlPHSoVjEDxAcEd0o/ISyzJKcqJdJZPKqKvmSj7hRWkbt7WpseG IPS5M38H3yc+Q80pixxjSXI/2PJriR6yGB1+ZksDlO00U0WVQ5Nre2La0lV9Kn6uEg H9Ipl/d29m63A+CDQUbjSXiIL7zzYv9x0T1ETW7lNgf8TKhv2DgohrhJzXr4eWgSaG G5fEz/kW/twNWJ8o/EtBaLF7jZVZ4g87ku6/wIs3TVuFqnRdA9Cnd0wMiGTEkx9Jul SiTt+XrrtcVgQpNO8VQ5S6bBykrZFspBVpL1IxDtApgoSGMzLcjpN3iP2qcKBKADp6 3MJo6oDDPtpDQ== From: Sasha Levin To: stable@vger.kernel.org, roman.li@amd.com Cc: Mario Limonciello , Alex Deucher , Nicholas Kazlauskas , Aurabindo Pillai , Daniel Wheeler , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: FAILED: Patch "drm/amd/display: Fix array-index-out-of-bounds in dcn35_clkmgr" failed to apply to 5.4-stable tree Date: Wed, 27 Mar 2024 08:22:31 -0400 Message-ID: <20240327122231.2837784-1-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Hint: ignore X-stable: review Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch below does not apply to the 5.4-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to . Thanks, Sasha Acked-by: Aurabindo Pillai Reviewed-by: Nicholas Kazlauskas Tested-by: Daniel Wheeler ------------------ original commit in Linus's tree ------------------ From a8edc9cc0b14e3769bbc9b82d00e5e5fc6b5ff0a Mon Sep 17 00:00:00 2001 From: Roman Li Date: Tue, 30 Jan 2024 18:07:24 -0500 Subject: [PATCH] drm/amd/display: Fix array-index-out-of-bounds in dcn35_clkmgr [Why] There is a potential memory access violation while iterating through array of dcn35 clks. [How] Limit iteration per array size. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Nicholas Kazlauskas Acked-by: Aurabindo Pillai Signed-off-by: Roman Li Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- .../amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b= /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index 36e5bb611fb10..c378b879c76d8 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -658,10 +658,13 @@ static void dcn35_clk_mgr_helper_populate_bw_params(s= truct clk_mgr_internal *clk struct clk_limit_table_entry def_max =3D bw_params->clk_table.entries[bw_= params->clk_table.num_entries - 1]; uint32_t max_fclk =3D 0, min_pstate =3D 0, max_dispclk =3D 0, max_dppclk = =3D 0; uint32_t max_pstate =3D 0, max_dram_speed_mts =3D 0, min_dram_speed_mts = =3D 0; + uint32_t num_memps, num_fclk, num_dcfclk; int i; =20 /* Determine min/max p-state values. */ - for (i =3D 0; i < clock_table->NumMemPstatesEnabled; i++) { + num_memps =3D (clock_table->NumMemPstatesEnabled > NUM_MEM_PSTATE_LEVELS)= ? NUM_MEM_PSTATE_LEVELS : + clock_table->NumMemPstatesEnabled; + for (i =3D 0; i < num_memps; i++) { uint32_t dram_speed_mts =3D calc_dram_speed_mts(&clock_table->MemPstateT= able[i]); =20 if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts > max_dram_sp= eed_mts) { @@ -673,7 +676,7 @@ static void dcn35_clk_mgr_helper_populate_bw_params(str= uct clk_mgr_internal *clk min_dram_speed_mts =3D max_dram_speed_mts; min_pstate =3D max_pstate; =20 - for (i =3D 0; i < clock_table->NumMemPstatesEnabled; i++) { + for (i =3D 0; i < num_memps; i++) { uint32_t dram_speed_mts =3D calc_dram_speed_mts(&clock_table->MemPstateT= able[i]); =20 if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts < min_dram_sp= eed_mts) { @@ -702,9 +705,13 @@ static void dcn35_clk_mgr_helper_populate_bw_params(st= ruct clk_mgr_internal *clk /* Base the clock table on dcfclk, need at least one entry regardless of = pmfw table */ ASSERT(clock_table->NumDcfClkLevelsEnabled > 0); =20 - max_fclk =3D find_max_clk_value(clock_table->FclkClocks_Freq, clock_table= ->NumFclkLevelsEnabled); + num_fclk =3D (clock_table->NumFclkLevelsEnabled > NUM_FCLK_DPM_LEVELS) ? = NUM_FCLK_DPM_LEVELS : + clock_table->NumFclkLevelsEnabled; + max_fclk =3D find_max_clk_value(clock_table->FclkClocks_Freq, num_fclk); =20 - for (i =3D 0; i < clock_table->NumDcfClkLevelsEnabled; i++) { + num_dcfclk =3D (clock_table->NumFclkLevelsEnabled > NUM_DCFCLK_DPM_LEVELS= ) ? NUM_DCFCLK_DPM_LEVELS : + clock_table->NumDcfClkLevelsEnabled; + for (i =3D 0; i < num_dcfclk; i++) { int j; =20 /* First search defaults for the clocks we don't read using closest lowe= r or equal default dcfclk */ --=20 2.43.0