From nobody Tue May 14 13:48:09 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E26F13A41A; Wed, 27 Mar 2024 12:18:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711541934; cv=none; b=npi0aXB3FWMjYKSxDOPo42JlC0ZcLRR1fepRoCOTNePP5RupGdkXaX1eBX9JW22yO2aRIXuIipLnWIiSN2+OFu+Pdx1XN818MJVoZNwCoEReckEcrJQCJM17jkBYAjonM7iHFvt+Sj0S/TSan5RRB562Hi60f/eHsGlOVw4XuUg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711541934; c=relaxed/simple; bh=jw7DqDCWlcJIxt7zVuuwakseS86jzzqqy34SCyUHTaE=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=LhMIfOh17qiZvhBDLGQfdPyBL+gzHrrJlZq3LRdqbVuHpSJZp87FrDEDTF/c73LQ7zh3i51rdjsuXVa5QahJN17WcCqLMhzY8K5HcKLLZsdPKEtIQfBUiKVRqpi6/cErSVJs2zhEiCvzZ2e7ERZ9LDGDZfu1NCZ7HovFhIQC774= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KhjZA+5M; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KhjZA+5M" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DC95AC433F1; Wed, 27 Mar 2024 12:18:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711541934; bh=jw7DqDCWlcJIxt7zVuuwakseS86jzzqqy34SCyUHTaE=; h=From:To:Cc:Subject:Date:From; b=KhjZA+5MoIk48yHjm+XooSX+8hMPJifz9vz34bWTY5uTof+CkBkbD810FtIFM9Npx 7LjPGhtnicH5bMoOVo+NODoUSQzYHNlOnp7dvAAP5G1Sk0Xlvje1Bcwwu59VsG9fxO Zv/hnq0gEsMw/SPWy/bh3Zz0Zt1mbReWsSFWy96EjeJKhRK+vn8fopOsSde8E82r2G A6LuD09KICXYlCkZK1PjwfDVV2ENHJDbQmNzjFWa9BTlMkrSJ137UyIGtYwEuWbKbx vGhQwVDaw4clyvvGK6PhPC991yNwKI8+t0RE11JMH3dAJ9fR9z3SweKrsfgZTRPeIP 2EJOtouPHUbbQ== From: Sasha Levin To: stable@vger.kernel.org, ilya.bakoulin@amd.com Cc: Mario Limonciello , Alex Deucher , Charlene Liu , Alex Hung , Daniel Wheeler , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: FAILED: Patch "drm/amd/display: Clear OPTC mem select on disable" failed to apply to 5.10-stable tree Date: Wed, 27 Mar 2024 08:18:51 -0400 Message-ID: <20240327121852.2834738-1-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Hint: ignore X-stable: review Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch below does not apply to the 5.10-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to . Thanks, Sasha Acked-by: Alex Hung Reviewed-by: Charlene Liu Tested-by: Daniel Wheeler ------------------ original commit in Linus's tree ------------------ From b4e05bb1dec53fe28c3c88425aded824498666e5 Mon Sep 17 00:00:00 2001 From: Ilya Bakoulin Date: Wed, 3 Jan 2024 09:42:04 -0500 Subject: [PATCH] drm/amd/display: Clear OPTC mem select on disable [Why] Not clearing the memory select bits prior to OPTC disable can cause DSC corruption issues when attempting to reuse a memory instance for another OPTC that enables ODM. [How] Clear the memory select bits prior to disabling an OPTC. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Charlene Liu Acked-by: Alex Hung Signed-off-by: Ilya Bakoulin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c | 3 +++ drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drive= rs/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c index 1788eb29474b4..8234935433254 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c @@ -173,6 +173,9 @@ static bool optc32_disable_crtc(struct timing_generator= *optc) OPTC_SEG3_SRC_SEL, 0xf, OPTC_NUM_OF_INPUT_SEGMENT, 0); =20 + REG_UPDATE(OPTC_MEMORY_CONFIG, + OPTC_MEM_SEL, 0); + /* disable otg request until end of the first line * in the vertical blank region */ diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c b/drive= rs/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c index 3d6c1b2c2b4d6..5b15475088503 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c @@ -145,6 +145,9 @@ static bool optc35_disable_crtc(struct timing_generator= *optc) OPTC_SEG3_SRC_SEL, 0xf, OPTC_NUM_OF_INPUT_SEGMENT, 0); =20 + REG_UPDATE(OPTC_MEMORY_CONFIG, + OPTC_MEM_SEL, 0); + /* disable otg request until end of the first line * in the vertical blank region */ --=20 2.43.0