From nobody Fri May 10 07:18:06 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0ACE215B128; Wed, 27 Mar 2024 12:18:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711541892; cv=none; b=ix3MMhim1TJ16Z7M16/PmdanwsQJKd5OiEL4FucXqi4v7ExVNUAc+9e05Cm1Sl7jC2yviWgRrsviQYzk+wWRhBp01g87HATVVW5Kpc+jV37WTzdMhR4BXTpW0EHAmKWTaHOV/307UzYEae6ICLi1Q6MGrFYguntoTaJIpye0mro= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711541892; c=relaxed/simple; bh=w2u4vgu6Du69+3H02MFyKLByvShk4lpvH/ZdlMuMX5s=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=obxzxK8JH12uVlEoLoep9L8TNu+HGGjTB08103PscmRRWu5YJdzBnSfPzoDzXXyoNfaKDGI/3NRH3KX+kgSb9ipFJ4rpaS2gfCkYsThK/LLizXwLcohEiMEVpND67iLk7/zICx2WDswcKuBCWUfCBEjXNDdZyyDq+bMoiPQBcAA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mmsloUiR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mmsloUiR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CE6EFC43399; Wed, 27 Mar 2024 12:18:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711541891; bh=w2u4vgu6Du69+3H02MFyKLByvShk4lpvH/ZdlMuMX5s=; h=From:To:Cc:Subject:Date:From; b=mmsloUiR0Q3feEhkROWvNAVhojcYITfYs7w2+jkrKeQZg2NbMjoX/IPpGpqwpEPNZ SgNKd3RkHIGmRfNvv4OZepOM+RUU7ZXtx21wrZ7dC28+10kpNT3O9zA+jXasscbioG wxbznD44hWL2M1sxedDUvxoS28W8fhKg4Pq15DlxDdNWQoX74cADFWRcDP2OdcMvEc oJ94GnWwRec2GTUG0sxpbhKmubf9tE3/2HsUrm/uWvHxiYUhEa9xuZ4o/DiWH9UXZi xOq/Q8TK2IHTfxCgvUcSsPMySJyf9yuauvkoc78QDalqZ/pMe+qlR641o/MR4+drVC E9vZr11sh7TFg== From: Sasha Levin To: stable@vger.kernel.org, george.shen@amd.com Cc: Mario Limonciello , Alex Deucher , Martin Leung , Aurabindo Pillai , Daniel Wheeler , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: FAILED: Patch "Revert "drm/amd/display: Add left edge pixel for YCbCr422/420 + ODM pipe split"" failed to apply to 5.10-stable tree Date: Wed, 27 Mar 2024 08:18:09 -0400 Message-ID: <20240327121809.2834111-1-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Hint: ignore X-stable: review Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch below does not apply to the 5.10-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to . Thanks, Sasha Acked-by: Aurabindo Pillai Reviewed-by: Martin Leung Tested-by: Daniel Wheeler ------------------ original commit in Linus's tree ------------------ From e9e1abb397e550aec86a6d9eb7c6f8ed4271d742 Mon Sep 17 00:00:00 2001 From: George Shen Date: Fri, 2 Feb 2024 17:45:32 -0500 Subject: [PATCH] Revert "drm/amd/display: Add left edge pixel for YCbCr422/= 420 + ODM pipe split" [Why/How] A regression was identified with the change to add left edge pixel for YCbCr422/420 + ODM combine cases. This reverts commit 288c0254a0b0c9980dba9df7d5afadf27280b99c Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Martin Leung Acked-by: Aurabindo Pillai Signed-off-by: George Shen Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 -- .../gpu/drm/amd/display/dc/core/dc_resource.c | 37 ------------------- .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 7 +--- .../gpu/drm/amd/display/dc/inc/core_types.h | 2 - drivers/gpu/drm/amd/display/dc/inc/resource.h | 4 -- 5 files changed, 1 insertion(+), 53 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd= /display/dc/core/dc.c index 1d0fd69cc7bd1..4d5194293dbd5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3098,10 +3098,6 @@ static bool update_planes_and_stream_state(struct dc= *dc, =20 if (otg_master && otg_master->stream->test_pattern.type !=3D DP_TEST_PA= TTERN_VIDEO_MODE) resource_build_test_pattern_params(&context->res_ctx, otg_master); - - if (otg_master && (otg_master->stream->timing.pixel_encoding =3D=3D PIX= EL_ENCODING_YCBCR422 || - otg_master->stream->timing.pixel_encoding =3D=3D PIXEL_ENCODING_YCBCR= 420)) - resource_build_subsampling_params(&context->res_ctx, otg_master); } } =20 diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gp= u/drm/amd/display/dc/core/dc_resource.c index 96ea283bd1690..1b7765bc5e5ef 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -822,16 +822,6 @@ static struct rect calculate_odm_slice_in_timing_activ= e(struct pipe_ctx *pipe_ct stream->timing.v_border_bottom + stream->timing.v_border_top; =20 - /* Recout for ODM slices after the first slice need one extra left edge p= ixel - * for 3-tap chroma subsampling. - */ - if (odm_slice_idx > 0 && - (pipe_ctx->stream->timing.pixel_encoding =3D=3D PIXEL_ENCODING_YCBCR422= || - pipe_ctx->stream->timing.pixel_encoding =3D=3D PIXEL_ENCODING_YCBCR420= )) { - odm_rec.x -=3D 1; - odm_rec.width +=3D 1; - } - return odm_rec; } =20 @@ -1448,7 +1438,6 @@ void resource_build_test_pattern_params(struct resour= ce_context *res_ctx, enum controller_dp_test_pattern controller_test_pattern; enum controller_dp_color_space controller_color_space; enum dc_color_depth color_depth =3D otg_master->stream->timing.display_co= lor_depth; - enum dc_pixel_encoding pixel_encoding =3D otg_master->stream->timing.pixe= l_encoding; int h_active =3D otg_master->stream->timing.h_addressable + otg_master->stream->timing.h_border_left + otg_master->stream->timing.h_border_right; @@ -1480,36 +1469,10 @@ void resource_build_test_pattern_params(struct reso= urce_context *res_ctx, else params->width =3D last_odm_slice_width; =20 - /* Extra left edge pixel is required for 3-tap chroma subsampling. */ - if (i !=3D 0 && (pixel_encoding =3D=3D PIXEL_ENCODING_YCBCR422 || - pixel_encoding =3D=3D PIXEL_ENCODING_YCBCR420)) { - params->offset -=3D 1; - params->width +=3D 1; - } - offset +=3D odm_slice_width; } } =20 -void resource_build_subsampling_params(struct resource_context *res_ctx, - struct pipe_ctx *otg_master) -{ - struct pipe_ctx *opp_heads[MAX_PIPES]; - int odm_cnt =3D 1; - int i; - - odm_cnt =3D resource_get_opp_heads_for_otg_master(otg_master, res_ctx, op= p_heads); - - /* For ODM slices after the first slice, extra left edge pixel is required - * for 3-tap chroma subsampling. - */ - if (otg_master->stream->timing.pixel_encoding =3D=3D PIXEL_ENCODING_YCBCR= 422 || - otg_master->stream->timing.pixel_encoding =3D=3D PIXEL_ENCODING_YCBCR42= 0) { - for (i =3D 0; i < odm_cnt; i++) - opp_heads[i]->stream_res.left_edge_extra_pixel =3D (i =3D=3D 0) ? false= : true; - } -} - bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) { const struct dc_plane_state *plane_state =3D pipe_ctx->plane_state; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/driv= ers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index f15ba7335336a..c55d5155ecb9c 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -1573,8 +1573,7 @@ static void dcn20_detect_pipe_changes(struct dc_state= *old_state, * makes this assumption at the moment with how hubp reset is matched to * same index mpcc reset. */ - if (old_pipe->stream_res.opp !=3D new_pipe->stream_res.opp || - old_pipe->stream_res.left_edge_extra_pixel !=3D new_pipe->stream_res.le= ft_edge_extra_pixel) + if (old_pipe->stream_res.opp !=3D new_pipe->stream_res.opp) new_pipe->update_flags.bits.opp_changed =3D 1; if (old_pipe->stream_res.tg !=3D new_pipe->stream_res.tg) new_pipe->update_flags.bits.tg_changed =3D 1; @@ -1962,10 +1961,6 @@ static void dcn20_program_pipe( pipe_ctx->stream_res.opp, &pipe_ctx->stream->bit_depth_params, &pipe_ctx->stream->clamping); - - pipe_ctx->stream_res.opp->funcs->opp_program_left_edge_extra_pixel( - pipe_ctx->stream_res.opp, - pipe_ctx->stream_res.left_edge_extra_pixel); } =20 /* Set ABM pipe after other pipe configurations done */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/= drm/amd/display/dc/inc/core_types.h index ebb659c327e06..3a6bf77a68732 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -333,8 +333,6 @@ struct stream_resource { uint8_t gsl_group; =20 struct test_pattern_params test_pattern_params; - - bool left_edge_extra_pixel; }; =20 struct plane_resource { diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/dr= m/amd/display/dc/inc/resource.h index b14d52e52fa2f..77a60aa9f27bb 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -107,10 +107,6 @@ void resource_build_test_pattern_params( struct resource_context *res_ctx, struct pipe_ctx *pipe_ctx); =20 -void resource_build_subsampling_params( - struct resource_context *res_ctx, - struct pipe_ctx *pipe_ctx); - bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx); =20 enum dc_status resource_build_scaling_params_for_context( --=20 2.43.0