From nobody Sun May 12 13:13:58 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1000159203; Wed, 27 Mar 2024 12:17:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711541849; cv=none; b=PhIa8ttu5xPfJxsqVDx6QrlwS8USB+vxVPSb49nqW9T2jxIU9/WaMpVYGe1Ef4uvnsnJxSlUSkqP5pwG7W00+OOSN+B9uTB5RvyEG6tsX5lnqseZBuzjCi+XII16BwdZeK2fEkdmesReuaAGvwDKoL0j9azaQkfaOVWuCyTxg1c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711541849; c=relaxed/simple; bh=8ptITLWe8FJ2ZPSfilGLbl2BWFiSaOlUPKOks86zVd0=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=HIoUXDonrHGYsau4vz65pj0sAsZg302r6SM1hFd9S6z3awb/Pm8ann0XsssplIrmYwM9Tw2/444F6aeFURV23g8qwz66UyGgmgUxYd5i8o6wmPH3E9kERd9jCaInMG1aMhSyaSUzou6zYFHo7anNBo4W+R+NMDAyIJl3Uo070hc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LZ1azdb4; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LZ1azdb4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BE4CAC43390; Wed, 27 Mar 2024 12:17:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711541848; bh=8ptITLWe8FJ2ZPSfilGLbl2BWFiSaOlUPKOks86zVd0=; h=From:To:Cc:Subject:Date:From; b=LZ1azdb4CT6OmVeWrzo4sFV7XuKtX4DxYqxMacHEUXXrjXkSZa1YzgMQS3gUUMfxj 7+JDMejXpyI4ObPxmqWqFKtp73ficg9shNEYuneHUjsA/JRxzivgxztUgMNp9ijzAn P4/wijmmc/qUrW+rqBzu+YCIbXp56MqJaHUB/MB1EhaUNIuHQ5hP3tJH+/hGb9e+Ex thZlDojmK6zyoGLb6tCDrNTGeTl25p+nnAlTuRXNe1u8cy874p+/Yhg9HTRJkZShsC AneGP7K1g/6RpMlrUZyNR/Z5DcFzL6MzGb+vm4kA3xUdTsWZtI/hEX5xWcKVUkYKKG an6Myt5eOaHrA== From: Sasha Levin To: stable@vger.kernel.org, jerry.zuo@amd.com Cc: Mario Limonciello , Alex Deucher , Charlene Liu , Tom Chung , Daniel Wheeler , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: FAILED: Patch "drm/amd/display: Fix dcn35 8k30 Underflow/Corruption Issue" failed to apply to 5.15-stable tree Date: Wed, 27 Mar 2024 08:17:26 -0400 Message-ID: <20240327121726.2833544-1-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Hint: ignore X-stable: review Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch below does not apply to the 5.15-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to . Thanks, Sasha Acked-by: Tom Chung Reviewed-by: Charlene Liu Tested-by: Daniel Wheeler ------------------ original commit in Linus's tree ------------------ From 4ba9ca63e696f7bdc91293aeb70c22203b7089be Mon Sep 17 00:00:00 2001 From: Fangzhi Zuo Date: Thu, 11 Jan 2024 14:46:01 -0500 Subject: [PATCH] drm/amd/display: Fix dcn35 8k30 Underflow/Corruption Issue [why] odm calculation is missing for pipe split policy determination and cause Underflow/Corruption issue. [how] Add the odm calculation. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Charlene Liu Acked-by: Tom Chung Signed-off-by: Fangzhi Zuo Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- .../display/dc/dml2/dml2_translation_helper.c | 29 +++++++------------ .../gpu/drm/amd/display/dc/inc/core_types.h | 2 ++ 2 files changed, 13 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c = b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c index 8b0f930be5ae1..23a608274096f 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c @@ -791,35 +791,28 @@ static void populate_dml_surface_cfg_from_plane_state= (enum dml_project_id dml2_p } } =20 -/*TODO no support for mpc combine, need rework - should calculate scaling = params based on plane+stream*/ -static struct scaler_data get_scaler_data_for_plane(const struct dc_plane_= state *in, const struct dc_state *context) +static struct scaler_data get_scaler_data_for_plane(const struct dc_plane_= state *in, struct dc_state *context) { int i; - struct scaler_data data =3D { 0 }; + struct pipe_ctx *temp_pipe =3D &context->res_ctx.temp_pipe; + + memset(temp_pipe, 0, sizeof(struct pipe_ctx)); =20 for (i =3D 0; i < MAX_PIPES; i++) { const struct pipe_ctx *pipe =3D &context->res_ctx.pipe_ctx[i]; =20 if (pipe->plane_state =3D=3D in && !pipe->prev_odm_pipe) { - const struct pipe_ctx *next_pipe =3D pipe->next_odm_pipe; - - data =3D context->res_ctx.pipe_ctx[i].plane_res.scl_data; - while (next_pipe) { - data.h_active +=3D next_pipe->plane_res.scl_data.h_active; - data.recout.width +=3D next_pipe->plane_res.scl_data.recout.width; - if (in->rotation =3D=3D ROTATION_ANGLE_0 || in->rotation =3D=3D ROTATI= ON_ANGLE_180) { - data.viewport.width +=3D next_pipe->plane_res.scl_data.viewport.width; - } else { - data.viewport.height +=3D next_pipe->plane_res.scl_data.viewport.heig= ht; - } - next_pipe =3D next_pipe->next_odm_pipe; - } + temp_pipe->stream =3D pipe->stream; + temp_pipe->plane_state =3D pipe->plane_state; + temp_pipe->plane_res.scl_data.taps =3D pipe->plane_res.scl_data.taps; + + resource_build_scaling_params(temp_pipe); break; } } =20 ASSERT(i < MAX_PIPES); - return data; + return temp_pipe->plane_res.scl_data; } =20 static void populate_dummy_dml_plane_cfg(struct dml_plane_cfg_st *out, uns= igned int location, const struct dc_stream_state *in) @@ -864,7 +857,7 @@ static void populate_dummy_dml_plane_cfg(struct dml_pla= ne_cfg_st *out, unsigned out->ScalerEnabled[location] =3D false; } =20 -static void populate_dml_plane_cfg_from_plane_state(struct dml_plane_cfg_s= t *out, unsigned int location, const struct dc_plane_state *in, const struc= t dc_state *context) +static void populate_dml_plane_cfg_from_plane_state(struct dml_plane_cfg_s= t *out, unsigned int location, const struct dc_plane_state *in, struct dc_s= tate *context) { const struct scaler_data scaler_data =3D get_scaler_data_for_plane(in, co= ntext); =20 diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/= drm/amd/display/dc/inc/core_types.h index f74ae0d41d3c4..3a6bf77a68732 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -469,6 +469,8 @@ struct resource_context { unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS]; int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS]; bool is_mpc_3dlut_acquired[MAX_PIPES]; + /* solely used for build scalar data in dml2 */ + struct pipe_ctx temp_pipe; }; =20 struct dce_bw_output { --=20 2.43.0