From nobody Sun May 12 03:46:32 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 528D51591F3; Wed, 27 Mar 2024 12:17:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711541847; cv=none; b=FVe9iPn4LcIK5CIN1aYdbkWuGZAzsKSbDXRq/gXPsR18UfzdpMuW9y1DmhAfmv7xLRkF9RMbMU87LJtCGF2cQOv9TOgo3lsOxiKt2lo8fXhCGl/oLS2Fu/CZxVb3wDYybtQF3/Ia/j5lcZEjrPd4x6j2aDDvuTiKZReYHW7sdyo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711541847; c=relaxed/simple; bh=21Alr+wEup3HifEfM/FwLQoLNMOwaqD8TmQfwr+91Ms=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=GLbfo6xsASXWZyFeER9frRAMO6J5vric4FNKkGkDisyY4vAZvAn8zd0Vbw5SnTHQgNXUXQMKRsBuCaky6TWAHv3OrvafPtRmgsBj98NGPrywxeOvF6BtjJVDFEKOKxAUT6Nefbn9evrImQfQ668BkCzjThQmDDdyYFMJLAqiZAs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AyEFyX/s; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AyEFyX/s" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CAADFC43390; Wed, 27 Mar 2024 12:17:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711541845; bh=21Alr+wEup3HifEfM/FwLQoLNMOwaqD8TmQfwr+91Ms=; h=From:To:Cc:Subject:Date:From; b=AyEFyX/seaVFPTQHoRmd7uL4DIBaoymvgdhgrpMNfJPtEtJVkElAbB9SrpKWH5jLJ pj4cBo67rpS6CmSMvv4xctrADCqcz6AZYDAk2X/yIfNAC2LstIAuUeNog3boNAwhZO Hwh4JcU9wue2ipNpx6V3SKJgaic6QUTxY/CSk4iFrgzq8STWaL6Zr85mh/scqfWle3 CbU6DohbhGCKqZRghql/Kr85EQZAevFPaN7Pbli6imBL//oXMLNY9jFqg4GNJxHh87 gvTg5qmJCVlg1puNQY/lVZTT7dcdW1gFNyyBIqvYL4B4mu+tKpOd7Z7l4sJXOhMHtt fUPDjT+FsRGqw== From: Sasha Levin To: stable@vger.kernel.org, dillon.varone@amd.com Cc: Mario Limonciello , Alex Deucher , Chaitanya Dhere , Alex Hung , Daniel Wheeler , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: FAILED: Patch "drm/amd/display: Init DPPCLK from SMU on dcn32" failed to apply to 5.15-stable tree Date: Wed, 27 Mar 2024 08:17:23 -0400 Message-ID: <20240327121724.2833507-1-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Hint: ignore X-stable: review Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch below does not apply to the 5.15-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to . Thanks, Sasha Acked-by: Alex Hung Reviewed-by: Chaitanya Dhere Tested-by: Daniel Wheeler ------------------ original commit in Linus's tree ------------------ From 4f5b8d78ca43fcc695ba16c83ebfabbfe09506d6 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Wed, 21 Feb 2024 13:21:20 -0500 Subject: [PATCH] drm/amd/display: Init DPPCLK from SMU on dcn32 [WHY & HOW] DPPCLK ranges should be obtained from the SMU when available. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Chaitanya Dhere Acked-by: Alex Hung Signed-off-by: Dillon Varone Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 14 ++++++++++ .../drm/amd/display/dc/dml2/dml2_wrapper.c | 28 +++++++++++++------ .../drm/amd/display/dc/dml2/dml2_wrapper.h | 3 ++ .../dc/resource/dcn32/dcn32_resource.c | 2 ++ .../dc/resource/dcn321/dcn321_resource.c | 2 ++ 5 files changed, 41 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b= /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 668f05c8654ef..bec252e1dd27a 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -216,6 +216,16 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base) if (clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz > 1950) clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz =3D 1950; =20 + /* DPPCLK */ + dcn32_init_single_clock(clk_mgr, PPCLK_DPPCLK, + &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz, + &num_entries_per_clk->num_dppclk_levels); + num_levels =3D num_entries_per_clk->num_dppclk_levels; + clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz =3D dcn30_smu_get_dc_mo= de_max_dpm_freq(clk_mgr, PPCLK_DPPCLK); + //HW recommends limit of 1950 MHz in display clock for all DCN3.2.x + if (clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz > 1950) + clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz =3D 1950; + if (num_entries_per_clk->num_dcfclk_levels && num_entries_per_clk->num_dtbclk_levels && num_entries_per_clk->num_dispclk_levels) @@ -240,6 +250,10 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base) =3D khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz); } =20 + for (i =3D 0; i < num_levels; i++) + if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz > 1950) + clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz =3D 1950; + /* Get UCLK, update bounding box */ clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base); =20 diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c b/drivers/g= pu/drm/amd/display/dc/dml2/dml2_wrapper.c index 2a58a7687bdb5..72cca367062e1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c @@ -703,13 +703,8 @@ static inline struct dml2_context *dml2_allocate_memor= y(void) return (struct dml2_context *) kzalloc(sizeof(struct dml2_context), GFP_K= ERNEL); } =20 -bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_o= ptions *config, struct dml2_context **dml2) +static void dml2_init(const struct dc *in_dc, const struct dml2_configurat= ion_options *config, struct dml2_context **dml2) { - // Allocate Mode Lib Ctx - *dml2 =3D dml2_allocate_memory(); - - if (!(*dml2)) - return false; =20 // Store config options (*dml2)->config =3D *config; @@ -737,9 +732,18 @@ bool dml2_create(const struct dc *in_dc, const struct = dml2_configuration_options initialize_dml2_soc_bbox(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc); =20 initialize_dml2_soc_states(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc, = &(*dml2)->v20.dml_core_ctx.states); +} + +bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_o= ptions *config, struct dml2_context **dml2) +{ + // Allocate Mode Lib Ctx + *dml2 =3D dml2_allocate_memory(); + + if (!(*dml2)) + return false; + + dml2_init(in_dc, config, dml2); =20 - /*Initialize DML20 instance which calls dml2_core_create, and core_dcn3_p= opulate_informative*/ - //dml2_initialize_instance(&(*dml_ctx)->v20.dml_init); return true; } =20 @@ -779,3 +783,11 @@ bool dml2_create_copy(struct dml2_context **dst_dml2, =20 return true; } + +void dml2_reinit(const struct dc *in_dc, + const struct dml2_configuration_options *config, + struct dml2_context **dml2) +{ + + dml2_init(in_dc, config, dml2); +} diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h b/drivers/g= pu/drm/amd/display/dc/dml2/dml2_wrapper.h index ee0eb184eb6d7..cc662d682fd4d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h @@ -214,6 +214,9 @@ void dml2_copy(struct dml2_context *dst_dml2, struct dml2_context *src_dml2); bool dml2_create_copy(struct dml2_context **dst_dml2, struct dml2_context *src_dml2); +void dml2_reinit(const struct dc *in_dc, + const struct dml2_configuration_options *config, + struct dml2_context **dml2); =20 /* * dml2_validate - Determines if a display configuration is supported or n= ot. diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c= b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index f844f57ecc49b..ce1754cc1f463 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -1931,6 +1931,8 @@ static void dcn32_update_bw_bounding_box(struct dc *d= c, struct clk_bw_params *bw { DC_FP_START(); dcn32_update_bw_bounding_box_fpu(dc, bw_params); + if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ct= x.dml2) + dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2); DC_FP_END(); } =20 diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource= .c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c index b356fed1726d9..296a0a8e71459 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c @@ -1581,6 +1581,8 @@ static void dcn321_update_bw_bounding_box(struct dc *= dc, struct clk_bw_params *b { DC_FP_START(); dcn321_update_bw_bounding_box_fpu(dc, bw_params); + if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ct= x.dml2) + dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2); DC_FP_END(); } =20 --=20 2.43.0