From nobody Thu May 9 14:46:22 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D3A3158DD8; Wed, 27 Mar 2024 12:17:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711541843; cv=none; b=LUfpeuIvFmAjdNGqCkubGUkiVrem6iiKjMdBR4HMZI0sQmodPWLQIKpI3apjLD1kXV8FsgCVeoCg6uU0WF5ZJgFR5WoZnD+FEiOGqZVWpQfU0nefKT8/gzDG9MwRLGPRQVqSMo6twYJ/ER1iCAzlSr4PgYunZCmbtxttKXhn7OE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711541843; c=relaxed/simple; bh=PHf8wlZRQC26DVlRvQiL2FXSBkxXak4B92Bmy54w5kM=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=uLs3998+U/ioEtGBaGOXzDdvNDEUYB2nRXrMVLeVHbU1Kc5yIWgmNok+XRpKAINF/GBXSlp2UH981jMKCKHEJ+++IUkWrLxyqE7vn2l+gcFQgCR1BqosJrcvvuzlaDZFp0ZkjUIOTim8tE+eQ0cMgQ0jxKcs9BHuudRf23x1N88= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bWC/lsPQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bWC/lsPQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A25B6C433F1; Wed, 27 Mar 2024 12:17:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711541842; bh=PHf8wlZRQC26DVlRvQiL2FXSBkxXak4B92Bmy54w5kM=; h=From:To:Cc:Subject:Date:From; b=bWC/lsPQstFas2N/xtPEHRY+C3O3a7Le9Pp3xl2DmvXe06RaPQnVllMeS/SLDNJ1H z9oCOtHEDApSNrk4XHs/MxXwxqSuZ+nTnM+YJsdkQJdoFaKcqMQQwuicSfTNN3n0Jj qXPOYeY48Gb9chPVjRhJiVGFMD2lrVSRfH12ntR5jvml28Dj3LlZenCHAIxmjz2abX Xg9nKAU0uRdgyaR+yCCkc1UxdCoSW4W845PXIVlNzDHB0wBDGwnPPZI39HtZREqxEG 5xB8MRPlEdOpyjBJSK5R6YNwylEZqx+w6dfsX4ugXFho7uuhItH3xBFF3YvEEYSGOQ Wu5owoPMxvJZg== From: Sasha Levin To: stable@vger.kernel.org, nicholas.kazlauskas@amd.com Cc: Mario Limonciello , Alex Deucher , Charlene Liu , Alex Hung , Daniel Wheeler , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: FAILED: Patch "drm/amd/display: Port DENTIST hang and TDR fixes to OTG disable W/A" failed to apply to 5.15-stable tree Date: Wed, 27 Mar 2024 08:17:20 -0400 Message-ID: <20240327121720.2833470-1-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Hint: ignore X-stable: review Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch below does not apply to the 5.15-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to . Thanks, Sasha Acked-by: Alex Hung Reviewed-by: Charlene Liu Tested-by: Daniel Wheeler ------------------ original commit in Linus's tree ------------------ From 6c605f44086af24d7ac1867245aa10bb3360c5bf Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Fri, 15 Dec 2023 11:01:42 -0500 Subject: [PATCH] drm/amd/display: Port DENTIST hang and TDR fixes to OTG disable W/A [Why] We can experience DENTIST hangs during optimize_bandwidth or TDRs if FIFO is toggled and hangs. [How] Port the DCN35 fixes to DCN314. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Charlene Liu Acked-by: Alex Hung Signed-off-by: Nicholas Kazlauskas Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- .../dc/clk_mgr/dcn314/dcn314_clk_mgr.c | 21 ++++++++----------- 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c= b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c index 878c0e7b78abd..a84f1e376dee4 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c @@ -145,30 +145,27 @@ static int dcn314_get_active_display_cnt_wa( return display_count; } =20 -static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_= state *context, bool disable) +static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_= state *context, + bool safe_to_lower, bool disable) { struct dc *dc =3D clk_mgr_base->ctx->dc; int i; =20 for (i =3D 0; i < dc->res_pool->pipe_count; ++i) { - struct pipe_ctx *pipe =3D &dc->current_state->res_ctx.pipe_ctx[i]; + struct pipe_ctx *pipe =3D safe_to_lower + ? &context->res_ctx.pipe_ctx[i] + : &dc->current_state->res_ctx.pipe_ctx[i]; =20 if (pipe->top_pipe || pipe->prev_odm_pipe) continue; if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe= ->stream->signal))) { - struct stream_encoder *stream_enc =3D pipe->stream_res.stream_enc; - if (disable) { - if (stream_enc && stream_enc->funcs->disable_fifo) - pipe->stream_res.stream_enc->funcs->disable_fifo(stream_enc); + if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disab= le_crtc) + pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.t= g); =20 - pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg= ); reset_sync_context_for_pipe(dc, context, i); } else { pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg); - - if (stream_enc && stream_enc->funcs->enable_fifo) - pipe->stream_res.stream_enc->funcs->enable_fifo(stream_enc); } } } @@ -297,11 +294,11 @@ void dcn314_update_clocks(struct clk_mgr *clk_mgr_bas= e, } =20 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base= ->clks.dispclk_khz)) { - dcn314_disable_otg_wa(clk_mgr_base, context, true); + dcn314_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true); =20 clk_mgr_base->clks.dispclk_khz =3D new_clocks->dispclk_khz; dcn314_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); - dcn314_disable_otg_wa(clk_mgr_base, context, false); + dcn314_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false); =20 update_dispclk =3D true; } --=20 2.43.0