From nobody Sun May 12 19:56:05 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22A72158D7F; Wed, 27 Mar 2024 12:17:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711541835; cv=none; b=JZ3UDawbhKJPzNXfblMDmuInUM4LvAI3irVzReMPt5Lg3epNx8gD+qqCKFyZLOiB+JteCsfY2B4PE5rB0KwkFwWPmFOAu8nZTkKdYHuhtGxnD4kJ8b0QItchzpcoh8crCl/0WrDpOQJPO2+/zFDPhr8Y82ZEoNfxPu2QIvpD35A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711541835; c=relaxed/simple; bh=5+KUrWmuR0D3D/HWrsoIQeg+Lwj9k7uVG2/VRcEqCCI=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=jU9CBJHcS5YX3l2WBsLcLL333py+O66lgAgLZ5FswhqA3AhBPmFszlt/bmV2Jwn8CjNXQ0GaUr7Xgz0GV71P7/7AliorUa7kOZsA+UXKx4FyzBAYgE1faMNX733+CLPq81rnPqKR6Ctv3vO1bK//xKC3X3varix7Kq/zjXE33SQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SIU6GDy9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SIU6GDy9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 90CD2C433C7; Wed, 27 Mar 2024 12:17:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711541834; bh=5+KUrWmuR0D3D/HWrsoIQeg+Lwj9k7uVG2/VRcEqCCI=; h=From:To:Cc:Subject:Date:From; b=SIU6GDy9JPBsByRiwlRNZR70NyjjrpfqfuMkXLqu8l7Ig9Edkpsm3H8qlgkh01gpm wZJ2Q6GmPsaOow2mzZu6eKA4deaUw7JiqRTeA8W75mKPEx0A9J86oxIXnA31e3lNbi U83TIkpIn6sMB32EepfBCzfZVIQeh51oeEwT40t0M3AtP89amyLhP7H9mDan2PgfKL DdZryvbv39+5MT0TzW2VBk3N2K8OdrMeru1fdDyRHzbhu/Yf/bUwqx9Pdd5ga1qcRv upBm6FhHQ3ce8Tt1GeafzxpDKGaOgQzep8PfCiwJcWRQQPiM+6vyT7J7dzfTjOTdMM sJWyqqfUkIUzg== From: Sasha Levin To: stable@vger.kernel.org, chuntao.tso@amd.com Cc: Mario Limonciello , Alex Deucher , Alvin Lee , Alex Hung , Daniel Wheeler , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: FAILED: Patch "drm/amd/display: Amend coasting vtotal for replay low hz" failed to apply to 5.15-stable tree Date: Wed, 27 Mar 2024 08:17:12 -0400 Message-ID: <20240327121712.2833358-1-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Hint: ignore X-stable: review Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch below does not apply to the 5.15-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to . Thanks, Sasha Acked-by: Alex Hung Reviewed-by: Alvin Lee Tested-by: Daniel Wheeler ------------------ original commit in Linus's tree ------------------ From 8e054b0f1e71531762b8ded7f66c1b4af734671b Mon Sep 17 00:00:00 2001 From: ChunTao Tso Date: Tue, 20 Feb 2024 17:08:39 +0800 Subject: [PATCH] drm/amd/display: Amend coasting vtotal for replay low hz [WHY] The original coasting vtotal is 2 bytes, and it need to be amended to 4 bytes because low hz case. [HOW] Amend coasting vtotal from 2 bytes to 4 bytes. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Alvin Lee Acked-by: Alex Hung Signed-off-by: ChunTao Tso Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc_types.h | 4 ++-- drivers/gpu/drm/amd/display/dc/inc/link.h | 4 ++-- .../display/dc/link/protocols/link_edp_panel_control.c | 4 ++-- .../display/dc/link/protocols/link_edp_panel_control.h | 4 ++-- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 8 ++++++++ drivers/gpu/drm/amd/display/modules/power/power_helpers.c | 2 +- drivers/gpu/drm/amd/display/modules/power/power_helpers.h | 2 +- 7 files changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/am= d/display/dc/dc_types.h index 9900dda2eef5c..be2ac5c442a48 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -1085,9 +1085,9 @@ struct replay_settings { /* SMU optimization is enabled */ bool replay_smu_opt_enable; /* Current Coasting vtotal */ - uint16_t coasting_vtotal; + uint32_t coasting_vtotal; /* Coasting vtotal table */ - uint16_t coasting_vtotal_table[PR_COASTING_TYPE_NUM]; + uint32_t coasting_vtotal_table[PR_COASTING_TYPE_NUM]; /* Maximum link off frame count */ enum replay_link_off_frame_count_level link_off_frame_count_level; /* Replay pseudo vtotal for abm + ips on full screen video which can impr= ove ips residency */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/link.h b/drivers/gpu/drm/am= d/display/dc/inc/link.h index 26fe81f213da5..bf29fc58ea6a6 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/link.h +++ b/drivers/gpu/drm/amd/display/dc/inc/link.h @@ -285,12 +285,12 @@ struct link_service { enum replay_FW_Message_type msg, union dmub_replay_cmd_set *cmd_data); bool (*edp_set_coasting_vtotal)( - struct dc_link *link, uint16_t coasting_vtotal); + struct dc_link *link, uint32_t coasting_vtotal); bool (*edp_replay_residency)(const struct dc_link *link, unsigned int *residency, const bool is_start, const bool is_alpm); bool (*edp_set_replay_power_opt_and_coasting_vtotal)(struct dc_link *link, - const unsigned int *power_opts, uint16_t coasting_vtotal); + const unsigned int *power_opts, uint32_t coasting_vtotal); =20 bool (*edp_wait_for_t12)(struct dc_link *link); bool (*edp_is_ilr_optimization_required)(struct dc_link *link, diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_c= ontrol.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_con= trol.c index acfbbc638cc64..3baa2bdd6dd65 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -1034,7 +1034,7 @@ bool edp_send_replay_cmd(struct dc_link *link, return true; } =20 -bool edp_set_coasting_vtotal(struct dc_link *link, uint16_t coasting_vtota= l) +bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtota= l) { struct dc *dc =3D link->ctx->dc; struct dmub_replay *replay =3D dc->res_pool->replay; @@ -1073,7 +1073,7 @@ bool edp_replay_residency(const struct dc_link *link, } =20 bool edp_set_replay_power_opt_and_coasting_vtotal(struct dc_link *link, - const unsigned int *power_opts, uint16_t coasting_vtotal) + const unsigned int *power_opts, uint32_t coasting_vtotal) { struct dc *dc =3D link->ctx->dc; struct dmub_replay *replay =3D dc->res_pool->replay; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_c= ontrol.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_con= trol.h index 34e521af7bb48..a158c6234d422 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h @@ -59,12 +59,12 @@ bool edp_setup_replay(struct dc_link *link, bool edp_send_replay_cmd(struct dc_link *link, enum replay_FW_Message_type msg, union dmub_replay_cmd_set *cmd_data); -bool edp_set_coasting_vtotal(struct dc_link *link, uint16_t coasting_vtota= l); +bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtota= l); bool edp_replay_residency(const struct dc_link *link, unsigned int *residency, const bool is_start, const bool is_alpm); bool edp_get_replay_state(const struct dc_link *link, uint64_t *state); bool edp_set_replay_power_opt_and_coasting_vtotal(struct dc_link *link, - const unsigned int *power_opts, uint16_t coasting_vtotal); + const unsigned int *power_opts, uint32_t coasting_vtotal); bool edp_wait_for_t12(struct dc_link *link); bool edp_is_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing); diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/= drm/amd/display/dmub/inc/dmub_cmd.h index a529e369b2ace..af3fe8bb0728b 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -3238,6 +3238,14 @@ struct dmub_cmd_replay_set_coasting_vtotal_data { * Currently the support is only for 0 or 1 */ uint8_t panel_inst; + /** + * 16-bit value dicated by driver that indicates the coasting vtotal high= byte part. + */ + uint16_t coasting_vtotal_high; + /** + * Explicit padding to 4 byte boundary. + */ + uint8_t pad[2]; }; =20 /** diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/dr= ivers/gpu/drm/amd/display/modules/power/power_helpers.c index e304e8435fb8f..2a3698fd2dc24 100644 --- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c +++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c @@ -975,7 +975,7 @@ bool psr_su_set_dsc_slice_height(struct dc *dc, struct = dc_link *link, =20 void set_replay_coasting_vtotal(struct dc_link *link, enum replay_coasting_vtotal_type type, - uint16_t vtotal) + uint32_t vtotal) { link->replay_settings.coasting_vtotal_table[type] =3D vtotal; } diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h b/dr= ivers/gpu/drm/amd/display/modules/power/power_helpers.h index bef4815e1703d..ff7e6f3cd6be2 100644 --- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h +++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h @@ -56,7 +56,7 @@ bool dmub_init_abm_config(struct resource_pool *res_pool, void init_replay_config(struct dc_link *link, struct replay_config *pr_con= fig); void set_replay_coasting_vtotal(struct dc_link *link, enum replay_coasting_vtotal_type type, - uint16_t vtotal); + uint32_t vtotal); void set_replay_ips_full_screen_video_src_vtotal(struct dc_link *link, uin= t16_t vtotal); void calculate_replay_link_off_frame_count(struct dc_link *link, uint16_t vtotal, uint16_t htotal); --=20 2.43.0