From nobody Thu May 9 23:32:37 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1370C15820F; Wed, 27 Mar 2024 12:16:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711541812; cv=none; b=Tjz2MTBXb1hd+vf2AKFaUGO0gkJLC8Zn1YcuEkoJR/pFjWurOVE1dOPIvt1JYiSjqFS8FuaZfdpx0GO6z9T2I1DZ8CJKon5xOzZ1tV5VpZiwpR4kbZ/C/aRa3Z4wA1UBT9vx60KZVXi8nQeVIY7y/yqYA14Ccqpp48ZCha+htKI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711541812; c=relaxed/simple; bh=dLjf14wZbYsX5cBwbBgegh4sp8mE15mdZ9oeNdxCy0Q=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=i07jYLU2qtweNUbGLQ5/BTLz9Z3O5ydhROZQpvzun0XeldHe22WPKdMojfjVuTY1BoEOcCNTGnCda/+23g8nTxpbbLC8rolAPNFxqhD1ql6ObOv7YbYUphPVhMtf7jdonRjKGoCRP5OD/Ixp4PabeOKbMBx5cod7jpRuqKH5pX0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=i0DipLL1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="i0DipLL1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CAA23C433A6; Wed, 27 Mar 2024 12:16:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711541811; bh=dLjf14wZbYsX5cBwbBgegh4sp8mE15mdZ9oeNdxCy0Q=; h=From:To:Cc:Subject:Date:From; b=i0DipLL1Y69SxKIDAa1Vt4uxFxgvFVhQWjp2NUgfvBCgk1yA7CliR/Xey/Cmq/fbn L+MWSUmce1mYX+JAOpFzKqdG85d4Jlhe5KQxc9aTTIN6aCa/Zn5NZ3ClDxVXuC+yLl L1mo/sgrJZqbPA7YF7XUz0hdwAZjZBL08Qg2U0PX7TuuE1FMFuGj1jbke4hKVVZuvr 65q7XWC5agxuinAGa+BYUMccTG6Xn7z6/WUh3T7/g9gTw5+ln447mOc/hIU0Pm0TvA AaivCOtBtYjLROVFvPYvH9FqzjIIvTzc54UjpfzES9ypbqlaHSzSDGEpVknNk0bUAu B0LPAjWPQFbGQ== From: Sasha Levin To: stable@vger.kernel.org, sohaib.nadeem@amd.com Cc: Mario Limonciello , Alex Deucher , Alvin Lee , Alex Hung , Daniel Wheeler , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: FAILED: Patch "drm/amd/display: Override min required DCFCLK in dml1_validate" failed to apply to 5.15-stable tree Date: Wed, 27 Mar 2024 08:16:49 -0400 Message-ID: <20240327121650.2833036-1-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Hint: ignore X-stable: review Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch below does not apply to the 5.15-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to . Thanks, Sasha Acked-by: Alex Hung Reviewed-by: Alvin Lee Tested-by: Daniel Wheeler ------------------ original commit in Linus's tree ------------------ From 26fbcb3da77efc77bd7327b7916338d773cca484 Mon Sep 17 00:00:00 2001 From: Sohaib Nadeem Date: Wed, 14 Feb 2024 13:51:16 -0500 Subject: [PATCH] drm/amd/display: Override min required DCFCLK in dml1_validate [WHY]: Increasing min DCFCLK addresses underflow issues that occur when phantom pipe is turned on for some Sub-Viewport configs [HOW]: dcn32_override_min_req_dcfclk is added to override DCFCLK value in dml1_validate when subviewport is being used. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Alvin Lee Acked-by: Alex Hung Signed-off-by: Sohaib Nadeem Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c | 6 ++++++ .../gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c | 1 + .../gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h | 3 +++ 3 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c = b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c index 87760600e154d..f98def6c8c2d2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c @@ -782,3 +782,9 @@ void dcn32_update_dml_pipes_odm_policy_based_on_context= (struct dc *dc, struct dc pipe_cnt++; } } + +void dcn32_override_min_req_dcfclk(struct dc *dc, struct dc_state *context) +{ + if (dcn32_subvp_in_use(dc, context) && context->bw_ctx.bw.dcn.clk.dcfclk_= khz <=3D MIN_SUBVP_DCFCLK_KHZ) + context->bw_ctx.bw.dcn.clk.dcfclk_khz =3D MIN_SUBVP_DCFCLK_KHZ; +} diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c= b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index 3f3951f3ba983..f844f57ecc49b 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -1771,6 +1771,7 @@ static bool dml1_validate(struct dc *dc, struct dc_st= ate *context, bool fast_val dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, v= level); =20 dcn32_override_min_req_memclk(dc, context); + dcn32_override_min_req_dcfclk(dc, context); =20 BW_VAL_TRACE_END_WATERMARKS(); =20 diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h= b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h index 0c87b0fabba7d..2258c5c7212d8 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h @@ -42,6 +42,7 @@ #define SUBVP_ACTIVE_MARGIN_LIST_LEN 2 #define DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ 1800 #define DCN3_2_VMIN_DISPCLK_HZ 717000000 +#define MIN_SUBVP_DCFCLK_KHZ 400000 =20 #define TO_DCN32_RES_POOL(pool)\ container_of(pool, struct dcn32_resource_pool, base) @@ -181,6 +182,8 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struc= t dc_state *context, int =20 void dcn32_update_dml_pipes_odm_policy_based_on_context(struct dc *dc, str= uct dc_state *context, display_e2e_pipe_params_st *pipes); =20 +void dcn32_override_min_req_dcfclk(struct dc *dc, struct dc_state *context= ); + /* definitions for run time init of reg offsets */ =20 /* CLK SRC */ --=20 2.43.0