From nobody Fri Dec 19 16:05:00 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3A56153571; Wed, 27 Mar 2024 12:15:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711541709; cv=none; b=fE0ctLHBcGLflZsArquUj95DPHZkR4M0f9yuctH1jVLapKnNZIv7LI0fBAPLvSb3p8rMf6U2YGIq+BBHJRVA7V5GjF6uQ1Btcd1pjfXF3Fvdmge/h0RztMWv6bvUzdI0hZWvFJwLf8f6zqrVzv8YsHiNWwCGgAg3QShjEli8H6k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711541709; c=relaxed/simple; bh=Bo2dCeM2uEGk/0qpn0AGa5cVN2chYYs8wXP4rWIQdNk=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=Q8BXwuVi/gMuI+t9YlYGrQc2oeCrrpbUNfegYoJXS4+f7VHixCA9NgLA8OrBR52ShhtYItV1+TFHX+ydHSYZeXLBYZxyXkiUeuCb12Z2x+SZt5/iYq1sd2q2sVvu8e3eDcgGtT+QYEO3iq0su80TCGMOT3Bdnld/OQSM5sgCmx8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bc5esJAw; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bc5esJAw" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A65EAC43390; Wed, 27 Mar 2024 12:15:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711541709; bh=Bo2dCeM2uEGk/0qpn0AGa5cVN2chYYs8wXP4rWIQdNk=; h=From:To:Cc:Subject:Date:From; b=bc5esJAwsWWv+TmaUImiAoxRlzjrpml6ZBEDJdGqyhfh+tq6uuG1yw1C5vWF/IPwo 19ahC8+nKINIbm4FetZ9YbocN2Cyi4xkJgnoynNM5IsKTX3rIFVu5knH9EDyQK23Jt 3ozkpcqjm0oIOjOw2oiFAjScYjY2BO+84UiE6zXIfpKoG5LEJ6if7kpj33S53musxP xIGh0d6BDcWe3Mt4wspajITDfMpG6rPbOSiCeJ7OzRuCfKoOFJrfznlqxfwc6rIsDY FzDij3twqGLZtobQsFttmpjkmRVpelvyqdcQUZWTt+RK3b1Hph1mtpbvuFRl4a39aO C7Qu4mgr413sA== From: Sasha Levin To: stable@vger.kernel.org, alexander.deucher@amd.com Cc: Feifei Xu , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: FAILED: Patch "drm/amdgpu/gfx10: set UNORD_DISPATCH in compute MQDs" failed to apply to 5.15-stable tree Date: Wed, 27 Mar 2024 08:15:07 -0400 Message-ID: <20240327121507.2831649-1-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Hint: ignore X-stable: review Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch below does not apply to the 5.15-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to . Thanks, Sasha Reviewed-by: Feifei Xu ------------------ original commit in Linus's tree ------------------ From ca01082353d4c7c316cd8cfa53879970564a9c71 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 19 Jan 2024 12:23:55 -0500 Subject: [PATCH] drm/amdgpu/gfx10: set UNORD_DISPATCH in compute MQDs This needs to be set to 1 to avoid a potential deadlock in the GC 10.x and newer. On GC 9.x and older, this needs to be set to 0. This can lead to hangs in some mixed graphics and compute workloads. Updated firmware is also required for AQL. Reviewed-by: Feifei Xu Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/a= mdgpu/gfx_v10_0.c index 420c82b54650f..be4d5c1e826f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -6589,7 +6589,7 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_d= evice *adev, void *m, #ifdef __BIG_ENDIAN tmp =3D REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); #endif - tmp =3D REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); + tmp =3D REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); tmp =3D REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, prop->allow_tunneling); tmp =3D REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu= /drm/amd/amdkfd/kfd_mqd_manager_v10.c index 8b7fed9135269..22cbfa1bdaddb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c @@ -170,6 +170,7 @@ static void update_mqd(struct mqd_manager *mm, void *mq= d, m->cp_hqd_pq_control =3D 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; m->cp_hqd_pq_control |=3D ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; + m->cp_hqd_pq_control |=3D CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); =20 m->cp_hqd_pq_base_lo =3D lower_32_bits((uint64_t)q->queue_address >> 8); --=20 2.43.0