From nobody Tue Feb 10 15:43:46 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 902FF13B5AB; Wed, 27 Mar 2024 12:09:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711541366; cv=none; b=ZiD5/M86H+/6+MQtCFZUWWDbPQJynaWk126DRYMLt9gaOIdHY5z5tFNbPLIfLBYZNMNHEYMT5siwO4fhMFs33dUn4gfa57NAR2k2yGS1F1wilT8cCFtZvqJ7laz2Z4tDSddWJT/LpahSgNKuij1QMarRY0KNWyqamnzurJDo4lw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711541366; c=relaxed/simple; bh=Km1KWc8tChn4o/la8Cngju4PozNbu+3YFi2eW+/it/Y=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=cHV34hcqSWN8RiBftPveq+/G7yJgo4HPk1vb6Gh7ZN9ep3GS04Y8netdDqjpi2QlF5DKCH0E3AlptNeRI/+WPRpelxh52Vrx7L+SN2Vr0dwXKnriy8bRonaPa+U7eOWJzTC5cS5jrRhnbhmDcJeqLv3uJ9aerzrn0FdY5N+rkSA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DLESoHVI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DLESoHVI" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8C3B4C43390; Wed, 27 Mar 2024 12:09:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711541366; bh=Km1KWc8tChn4o/la8Cngju4PozNbu+3YFi2eW+/it/Y=; h=From:To:Cc:Subject:Date:From; b=DLESoHVIAEIQy3GIAabia10evDgXDIvQIxEJ8ApWXka0NePYXqh0JBXQabBK8/tbU gDYVX6IyD2oQJwRk5LhGaeJgiM6wok4bZhN6HedrSJFXywn26fxrGbydp0k481wEDr h4PoK3KTIEhVGB5eLXwnuJcS/GR8ElQUjun/u1Tv6vz73JhQ2bKBs3ivxJBGs/ntTr cZqWp8md5k2Iom3alGO9Bxn+TznthP8Ayw1dWiEnsZoLVtDilo4Cuz604Ol5p7jMOM KhZbuziNIWVn4pB6H7UhsVsbRdUDGqfCytprJjkwYOgHkztFmXcH94i478/WiWsE9L P5lHrf8DnvxTQ== From: Sasha Levin To: stable@vger.kernel.org, hamza.mahfooz@amd.com Cc: Mario Limonciello , Alex Deucher , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: FAILED: Patch "drm/amdgpu: make damage clips support configurable" failed to apply to 6.6-stable tree Date: Wed, 27 Mar 2024 08:09:24 -0400 Message-ID: <20240327120924.2827027-1-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Hint: ignore X-stable: review Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch below does not apply to the 6.6-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to . Thanks, Sasha Reviewed-by: Mario Limonciello ------------------ original commit in Linus's tree ------------------ From fc184dbe9fd99ad2dfb197b6fe18768bae1774b1 Mon Sep 17 00:00:00 2001 From: Hamza Mahfooz Date: Thu, 8 Feb 2024 16:23:29 -0500 Subject: [PATCH] drm/amdgpu: make damage clips support configurable We have observed that there are quite a number of PSR-SU panels on the market that are unable to keep up with what user space throws at them, resulting in hangs and random black screens. So, make damage clips support configurable and disable it by default for PSR-SU displays. Cc: stable@vger.kernel.org Reviewed-by: Mario Limonciello Signed-off-by: Hamza Mahfooz Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 13 +++++++++++++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 +++++++ 3 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdg= pu/amdgpu.h index 312dfaec7b4a7..1291b8eb9dffa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -198,6 +198,7 @@ extern uint amdgpu_dc_debug_mask; extern uint amdgpu_dc_visual_confirm; extern uint amdgpu_dm_abm_level; extern int amdgpu_backlight; +extern int amdgpu_damage_clips; extern struct amdgpu_mgpu_info mgpu_info; extern int amdgpu_ras_enable; extern uint amdgpu_ras_mask; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_drv.c index 161ecf9b41747..6ef7f22c1152c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -211,6 +211,7 @@ int amdgpu_seamless =3D -1; /* auto */ uint amdgpu_debug_mask; int amdgpu_agp =3D -1; /* auto */ int amdgpu_wbrf =3D -1; +int amdgpu_damage_clips =3D -1; /* auto */ =20 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work= ); =20 @@ -859,6 +860,18 @@ int amdgpu_backlight =3D -1; MODULE_PARM_DESC(backlight, "Backlight control (0 =3D pwm, 1 =3D aux, -1 a= uto (default))"); module_param_named(backlight, amdgpu_backlight, bint, 0444); =20 +/** + * DOC: damageclips (int) + * Enable or disable damage clips support. If damage clips support is disa= bled, + * we will force full frame updates, irrespective of what user space sends= to + * us. + * + * Defaults to -1 (where it is enabled unless a PSR-SU display is detected= ). + */ +MODULE_PARM_DESC(damageclips, + "Damage clips support (0 =3D disable, 1 =3D enable, -1 auto (default))"= ); +module_param_named(damageclips, amdgpu_damage_clips, int, 0444); + /** * DOC: tmz (int) * Trusted Memory Zone (TMZ) is a method to protect data being written diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b7a717c3682f9..f9a7a16f1ec21 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5254,6 +5254,7 @@ static void fill_dc_dirty_rects(struct drm_plane *pla= ne, struct drm_plane_state *new_plane_state, struct drm_crtc_state *crtc_state, struct dc_flip_addrs *flip_addrs, + bool is_psr_su, bool *dirty_regions_changed) { struct dm_crtc_state *dm_crtc_state =3D to_dm_crtc_state(crtc_state); @@ -5278,6 +5279,10 @@ static void fill_dc_dirty_rects(struct drm_plane *pl= ane, num_clips =3D drm_plane_get_damage_clips_count(new_plane_state); clips =3D drm_plane_get_damage_clips(new_plane_state); =20 + if (num_clips && (!amdgpu_damage_clips || (amdgpu_damage_clips < 0 && + is_psr_su))) + goto ffu; + if (!dm_crtc_state->mpo_requested) { if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS) goto ffu; @@ -8412,6 +8417,8 @@ static void amdgpu_dm_commit_planes(struct drm_atomic= _state *state, fill_dc_dirty_rects(plane, old_plane_state, new_plane_state, new_crtc_state, &bundle->flip_addrs[planes_count], + acrtc_state->stream->link->psr_settings.psr_version =3D=3D + DC_PSR_VERSION_SU_1, &dirty_rects_changed); =20 /* --=20 2.43.0