From nobody Sat Feb 7 21:24:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15761E541; Wed, 27 Mar 2024 12:06:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711541190; cv=none; b=apoIp82jOCZZb4sxwuNoxqAO5BE/xfufh6RBt0TNFtqx+uhJ5KM69+fxkovZ4nb5SIdzEoYyOjQjLyfXPaMSIG699uB6/4kqBV2wjZWJ/Zo45nvjFg9u9Tsh/o/5A/tWIztER+3eKjfpLqsKwKvuTy1uwrr/ETKH9ScXOQK7feU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711541190; c=relaxed/simple; bh=c3TxlZ9YhzbZXRFYm5uQoLX9ore9q+uQF6QCIQN7vl8=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=Me983dsYpSYCRtt4lMESYDLRpCGGqpA3AIuXZyjrZ5iHUbwAa/PJRn6Lq1KYzQ94QgBBBg8cYOWAulWCBzANzyMXgCgOn9zHMIdby380Voq0ZI2WhSDJrL9Ust+NzTVnlfTCNe73A5FkoO0Ytl1vzJG7+VsMqgS1RgzjlMGAgmY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PDftGt4v; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PDftGt4v" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DF863C433F1; Wed, 27 Mar 2024 12:06:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711541189; bh=c3TxlZ9YhzbZXRFYm5uQoLX9ore9q+uQF6QCIQN7vl8=; h=From:To:Cc:Subject:Date:From; b=PDftGt4v8IRcgTuhSPIgD+ITjCNlo/b2JKbr6h5b5kaJ0cke5g4dwgdtQOXipdoV2 H4CTzvhGxAHbjzo1I1puM943UtV7BjAiz+JoZcGkZk+ryPgbHjoXAvQmere7L4hLPH sfjhhqTXqvOqo/gupO6Uvk50IL7qhK0NLfzp9/I9m1EDAUQivCpl+M7IsEPX1eCBFL bjpLBchx8m3D+xpTVkWQvB/hZ4/nt0668J8V1qv+YQ4BBy+BTLD2LRaB++3eIB6NwC uaZs43oe7mdY5+/UIqERXU42WpYSgJYQwe+39s0Tj/F1srZZGbP2E0HAxO4KDHvTFg R8duK3ICOrE9g== From: Sasha Levin To: stable@vger.kernel.org, alexander.deucher@amd.com Cc: Feifei Xu , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: FAILED: Patch "drm/amdgpu/gfx11: set UNORD_DISPATCH in compute MQDs" failed to apply to 6.8-stable tree Date: Wed, 27 Mar 2024 08:06:27 -0400 Message-ID: <20240327120628.2824517-1-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Hint: ignore X-stable: review Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch below does not apply to the 6.8-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to . Thanks, Sasha Reviewed-by: Feifei Xu ------------------ original commit in Linus's tree ------------------ From fc8f5a29d4cf0979ac4019282c3ca5cb246969f9 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 19 Jan 2024 12:32:59 -0500 Subject: [PATCH] drm/amdgpu/gfx11: set UNORD_DISPATCH in compute MQDs This needs to be set to 1 to avoid a potential deadlock in the GC 10.x and newer. On GC 9.x and older, this needs to be set to 0. This can lead to hangs in some mixed graphics and compute workloads. Updated firmware is also required for AQL. Reviewed-by: Feifei Xu Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/a= mdgpu/gfx_v11_0.c index 043eff309100f..c1e0000107608 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -3846,7 +3846,7 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_d= evice *adev, void *m, (order_base_2(prop->queue_size / 4) - 1)); tmp =3D REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); - tmp =3D REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); + tmp =3D REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); tmp =3D REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, prop->allow_tunneling); tmp =3D REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c b/drivers/gpu= /drm/amd/amdkfd/kfd_mqd_manager_v11.c index 15277f1d5cf0a..d722cbd317834 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c @@ -224,6 +224,7 @@ static void update_mqd(struct mqd_manager *mm, void *mq= d, m->cp_hqd_pq_control =3D 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; m->cp_hqd_pq_control |=3D ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; + m->cp_hqd_pq_control |=3D CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); =20 m->cp_hqd_pq_base_lo =3D lower_32_bits((uint64_t)q->queue_address >> 8); --=20 2.43.0