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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id z15-20020a170906270f00b00a46b8cd9b51sm5294078ejc.185.2024.03.27.03.31.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 03:31:34 -0700 (PDT) From: =?UTF-8?q?Christoph=20M=C3=BCllner?= To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Albert Ou , Philipp Tomsich , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Daniel Henrique Barboza , Heiko Stuebner , Cooper Qu , Zhiwei Liu , Huang Tao , Alistair Francis , Andrew Jones , Conor Dooley Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH 1/2] riscv: thead: Rename T-Head PBMT to MAEE Date: Wed, 27 Mar 2024 11:31:29 +0100 Message-ID: <20240327103130.3651950-2-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240327103130.3651950-1-christoph.muellner@vrull.eu> References: <20240327103130.3651950-1-christoph.muellner@vrull.eu> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable T-Head's vendor extension to set page attributes has the name MAEE (MMU address attribute extension). Let's rename it, so it is clear what this referes to. See also: https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadmae= e.adoc Signed-off-by: Christoph M=C3=BCllner --- arch/riscv/Kconfig.errata | 8 ++++---- arch/riscv/errata/thead/errata.c | 8 ++++---- arch/riscv/include/asm/errata_list.h | 20 ++++++++++---------- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index 910ba8837add..2c24bef7e112 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -82,14 +82,14 @@ config ERRATA_THEAD =20 Otherwise, please say "N" here to avoid unnecessary overhead. =20 -config ERRATA_THEAD_PBMT - bool "Apply T-Head memory type errata" +config ERRATA_THEAD_MAEE + bool "Apply T-Head's MMU address attribute (MAEE)" depends on ERRATA_THEAD && 64BIT && MMU select RISCV_ALTERNATIVE_EARLY default y help - This will apply the memory type errata to handle the non-standard - memory type bits in page-table-entries on T-Head SoCs. + This will apply the memory type errata to handle T-Head's MMU address + attribute extension (MAEE). =20 If you don't know what to do here, say "Y". =20 diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/err= ata.c index b1c410bbc1ae..8c8a8a4b0421 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -19,10 +19,10 @@ #include #include =20 -static bool errata_probe_pbmt(unsigned int stage, +static bool errata_probe_maee(unsigned int stage, unsigned long arch_id, unsigned long impid) { - if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT)) + if (!IS_ENABLED(CONFIG_ERRATA_THEAD_MAEE)) return false; =20 if (arch_id !=3D 0 || impid !=3D 0) @@ -140,8 +140,8 @@ static u32 thead_errata_probe(unsigned int stage, { u32 cpu_req_errata =3D 0; =20 - if (errata_probe_pbmt(stage, archid, impid)) - cpu_req_errata |=3D BIT(ERRATA_THEAD_PBMT); + if (errata_probe_maee(stage, archid, impid)) + cpu_req_errata |=3D BIT(ERRATA_THEAD_MAEE); =20 errata_probe_cmo(stage, archid, impid); =20 diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/= errata_list.h index ea33288f8a25..7c377e137b41 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -23,7 +23,7 @@ #endif =20 #ifdef CONFIG_ERRATA_THEAD -#define ERRATA_THEAD_PBMT 0 +#define ERRATA_THEAD_MAEE 0 #define ERRATA_THEAD_PMU 1 #define ERRATA_THEAD_NUMBER 2 #endif @@ -53,20 +53,20 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_V= ENDOR_ID, \ * in the default case. */ #define ALT_SVPBMT_SHIFT 61 -#define ALT_THEAD_PBMT_SHIFT 59 +#define ALT_THEAD_MAEE_SHIFT 59 #define ALT_SVPBMT(_val, prot) \ asm(ALTERNATIVE_2("li %0, 0\t\nnop", \ "li %0, %1\t\nslli %0,%0,%3", 0, \ RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \ "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID, \ - ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \ + ERRATA_THEAD_MAEE, CONFIG_ERRATA_THEAD_MAEE) \ : "=3Dr"(_val) \ : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), \ - "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT), \ + "I"(prot##_THEAD >> ALT_THEAD_MAEE_SHIFT), \ "I"(ALT_SVPBMT_SHIFT), \ - "I"(ALT_THEAD_PBMT_SHIFT)) + "I"(ALT_THEAD_MAEE_SHIFT)) =20 -#ifdef CONFIG_ERRATA_THEAD_PBMT +#ifdef CONFIG_ERRATA_THEAD_MAEE /* * IO/NOCACHE memory types are handled together with svpbmt, * so on T-Head chips, check if no other memory type is set, @@ -83,11 +83,11 @@ asm volatile(ALTERNATIVE( \ "slli t3, t3, %3\n\t" \ "or %0, %0, t3\n\t" \ "2:", THEAD_VENDOR_ID, \ - ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \ + ERRATA_THEAD_MAEE, CONFIG_ERRATA_THEAD_MAEE) \ : "+r"(_val) \ - : "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_PBMT_SHIFT), \ - "I"(_PAGE_PMA_THEAD >> ALT_THEAD_PBMT_SHIFT), \ - "I"(ALT_THEAD_PBMT_SHIFT) \ + : "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_MAEE_SHIFT), \ + "I"(_PAGE_PMA_THEAD >> ALT_THEAD_MAEE_SHIFT), \ + "I"(ALT_THEAD_MAEE_SHIFT) \ : "t3") #else #define ALT_THEAD_PMA(_val) --=20 2.44.0 From nobody Mon Feb 9 11:38:22 2026 Received: from mail-ed1-f48.google.com (mail-ed1-f48.google.com [209.85.208.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFF111BDE2 for ; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id z15-20020a170906270f00b00a46b8cd9b51sm5294078ejc.185.2024.03.27.03.31.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 03:31:35 -0700 (PDT) From: =?UTF-8?q?Christoph=20M=C3=BCllner?= To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Albert Ou , Philipp Tomsich , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Daniel Henrique Barboza , Heiko Stuebner , Cooper Qu , Zhiwei Liu , Huang Tao , Alistair Francis , Andrew Jones , Conor Dooley Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH 2/2] riscv: T-Head: Test availability bit before enabling MAEE errata Date: Wed, 27 Mar 2024 11:31:30 +0100 Message-ID: <20240327103130.3651950-3-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240327103130.3651950-1-christoph.muellner@vrull.eu> References: <20240327103130.3651950-1-christoph.muellner@vrull.eu> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable T-Head's MAEE mechanism (non-compatible equivalent of RVI's Svpbmt) is currently assumed for all T-Head harts. However, QEMU recently decided to drop acceptance of guests that write reserved bits in PTEs. As MAEE uses reserved bits in PTEs and Linux applies the MAEE errata for all T-Head harts, this broke the Linux startup on QEMU emulations of the C906 emulation. This patch attempts to address this issue by testing the MAEE bit in TH_MXSTATUS CSR. As the TH_MXSTATUS CSR is only accessible in M-mode this patch depends on M-mode firmware that handles this for us transparently. As this patch breaks Linux bootup on all C9xx machines with MAEE, which don't have M-mode firmware that handles the access to the TH_MXSTATUS CSR, this patch is marked as RFC. Signed-off-by: Christoph M=C3=BCllner --- arch/riscv/errata/thead/errata.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/err= ata.c index 8c8a8a4b0421..dd7bf6c62a35 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -19,6 +19,9 @@ #include #include =20 +#define CSR_TH_MXSTATUS 0x7c0 +#define MXSTATUS_MAEE _AC(0x200000, UL) + static bool errata_probe_maee(unsigned int stage, unsigned long arch_id, unsigned long impid) { @@ -28,11 +31,14 @@ static bool errata_probe_maee(unsigned int stage, if (arch_id !=3D 0 || impid !=3D 0) return false; =20 - if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT || - stage =3D=3D RISCV_ALTERNATIVES_MODULE) - return true; + if (stage !=3D RISCV_ALTERNATIVES_EARLY_BOOT && + stage !=3D RISCV_ALTERNATIVES_MODULE) + return false; =20 - return false; + if (!(csr_read(CSR_TH_MXSTATUS) & MXSTATUS_MAEE)) + return false; + + return true; } =20 /* --=20 2.44.0