From nobody Sun Feb 8 14:22:48 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CE0A13C3F8; Tue, 26 Mar 2024 14:43:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711464211; cv=none; b=pS/PcPiT7lOV3MctFFHWXDjQYaMpQyGReAr1xGn3oL4Rf2eHZmmiQYLFlF2YP5x35gncigHEffbL7ln0+ISwKxO0IFaY1Zr1B6S5byqLsgXMgyz7zFeS/OJsDRL8wY/57CGT3BHWYNsLE9PudRkrfYQZT3Ef6t4HwrxlnfI7Klg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711464211; c=relaxed/simple; bh=dhPNFnXqNz7MyRueA7i8eRJMctZ7L861mSkCd6aiLic=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=WStdbNnalX6Mdw+sLmdJWGeyRF3sEaNX+hSD1sFU15mZGbFGAlUJ73b0NJ7/njOpfrLDFcJ7p4C9hYOMEGqFEpoEfIkBcPvfVixlb9clhvemwT9iBVzawDJylbIqC1I7hjNCyTPZS7s47GzhepxrOq8E5ziCVBaqpqMCCNeqLPo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=igrJ00EC; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="igrJ00EC" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 42QEh4et120096; Tue, 26 Mar 2024 09:43:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1711464184; bh=BXUiSRzxDxZfaQUcL26qbyVKdqBilV07vRkMOn/zbh8=; h=From:To:CC:Subject:Date; b=igrJ00ECxwQaeze00MPcpOWFZhsvQKjWc18mpT5G0Gx+Kk0Zjywmj7+QYUQnk02Vd 8DaJQOaXRk1tCE1eNIYK2S/vhgMCvTV2GQtTmr1eq2Ny0PBwIJy+x4Dbwze2XvtwtL YtsdFWQwE4gyYK2IuvaSi0Dnh6kxhyY8jnas8yF4= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 42QEh4nc092364 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 26 Mar 2024 09:43:04 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 26 Mar 2024 09:43:04 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 26 Mar 2024 09:43:04 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 42QEgxxZ014526; Tue, 26 Mar 2024 09:43:00 -0500 From: Siddharth Vadapalli To: , , , , , , , , , CC: , , , , Subject: [PATCH v6] PCI: keystone: Fix pci_ops for AM654x SoC Date: Tue, 26 Mar 2024 20:12:58 +0530 Message-ID: <20240326144258.2404433-1-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" In the process of converting .scan_bus() callbacks to .add_bus(), the ks_pcie_v3_65_scan_bus() function was changed to ks_pcie_v3_65_add_bus(). The .scan_bus() method belonged to ks_pcie_host_ops which was specific to controller version 3.65a, while the .add_bus() method had been added to ks_pcie_ops which is shared between the controller versions 3.65a and 4.90a. Neither the older ks_pcie_v3_65_scan_bus() method, nor the newer ks_pcie_v3_65_add_bus() method is applicable to the controller version 4.90a which is present in AM654x SoCs. Thus, as a fix, move the contents of "ks_pcie_v3_65_add_bus()" to the .msi_init callback "ks_pcie_msi_host_init()" which is specific to the 3.65a controller. Also, move the definitions of ks_pcie_set_dbi_mode() and ks_pcie_clear_dbi_mode() above ks_pcie_msi_host_init() in order to avoid forward declaration. Fixes: 6ab15b5e7057 ("PCI: dwc: keystone: Convert .scan_bus() callback to u= se add_bus") Suggested-by: Serge Semin Suggested-by: Bjorn Helgaas Suggested-by: Niklas Cassel Reviewed-by: Niklas Cassel Signed-off-by: Siddharth Vadapalli --- Hello, This patch is based on linux-next tagged next-20240326. v5: https://lore.kernel.org/r/20240326111905.2369778-1-s-vadapalli@ti.com/ Changes since v5: - Fixed indentation of comment as pointed out by: Niklas Cassel at: https://lore.kernel.org/r/ZgLUCqh12RMApzyr@x1-carbon/ - Collected Reviewed-by tag from: Niklas Cassel Regards, Siddharth. drivers/pci/controller/dwc/pci-keystone.c | 136 ++++++++++------------ 1 file changed, 60 insertions(+), 76 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/contro= ller/dwc/pci-keystone.c index 844de4418724..6cb3a4713009 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -245,8 +245,68 @@ static struct irq_chip ks_pcie_msi_irq_chip =3D { .irq_unmask =3D ks_pcie_msi_unmask, }; =20 +/** + * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask regis= ters + * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyS= tone + * PCIe host controller driver information. + * + * Since modification of dbi_cs2 involves different clock domain, read the + * status back to ensure the transition is complete. + */ +static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie) +{ + u32 val; + + val =3D ks_pcie_app_readl(ks_pcie, CMD_STATUS); + val |=3D DBI_CS2; + ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); + + do { + val =3D ks_pcie_app_readl(ks_pcie, CMD_STATUS); + } while (!(val & DBI_CS2)); +} + +/** + * ks_pcie_clear_dbi_mode() - Disable DBI mode + * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyS= tone + * PCIe host controller driver information. + * + * Since modification of dbi_cs2 involves different clock domain, read the + * status back to ensure the transition is complete. + */ +static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie) +{ + u32 val; + + val =3D ks_pcie_app_readl(ks_pcie, CMD_STATUS); + val &=3D ~DBI_CS2; + ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); + + do { + val =3D ks_pcie_app_readl(ks_pcie, CMD_STATUS); + } while (val & DBI_CS2); +} + static int ks_pcie_msi_host_init(struct dw_pcie_rp *pp) { + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct keystone_pcie *ks_pcie =3D to_keystone_pcie(pci); + + /* Configure and set up BAR0 */ + ks_pcie_set_dbi_mode(ks_pcie); + + /* Enable BAR0 */ + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1); + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1); + + ks_pcie_clear_dbi_mode(ks_pcie); + + /* + * For BAR0, just setting bus address for inbound writes (MSI) should + * be sufficient. Use physical address to avoid any conflicts. + */ + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start); + pp->msi_irq_chip =3D &ks_pcie_msi_irq_chip; return dw_pcie_allocate_domains(pp); } @@ -340,48 +400,6 @@ static const struct irq_domain_ops ks_pcie_intx_irq_do= main_ops =3D { .xlate =3D irq_domain_xlate_onetwocell, }; =20 -/** - * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask regis= ters - * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyS= tone - * PCIe host controller driver information. - * - * Since modification of dbi_cs2 involves different clock domain, read the - * status back to ensure the transition is complete. - */ -static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie) -{ - u32 val; - - val =3D ks_pcie_app_readl(ks_pcie, CMD_STATUS); - val |=3D DBI_CS2; - ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); - - do { - val =3D ks_pcie_app_readl(ks_pcie, CMD_STATUS); - } while (!(val & DBI_CS2)); -} - -/** - * ks_pcie_clear_dbi_mode() - Disable DBI mode - * @ks_pcie: A pointer to the keystone_pcie structure which holds the KeyS= tone - * PCIe host controller driver information. - * - * Since modification of dbi_cs2 involves different clock domain, read the - * status back to ensure the transition is complete. - */ -static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie) -{ - u32 val; - - val =3D ks_pcie_app_readl(ks_pcie, CMD_STATUS); - val &=3D ~DBI_CS2; - ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); - - do { - val =3D ks_pcie_app_readl(ks_pcie, CMD_STATUS); - } while (val & DBI_CS2); -} - static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) { u32 val; @@ -445,44 +463,10 @@ static struct pci_ops ks_child_pcie_ops =3D { .write =3D pci_generic_config_write, }; =20 -/** - * ks_pcie_v3_65_add_bus() - keystone add_bus post initialization - * @bus: A pointer to the PCI bus structure. - * - * This sets BAR0 to enable inbound access for MSI_IRQ register - */ -static int ks_pcie_v3_65_add_bus(struct pci_bus *bus) -{ - struct dw_pcie_rp *pp =3D bus->sysdata; - struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); - struct keystone_pcie *ks_pcie =3D to_keystone_pcie(pci); - - if (!pci_is_root_bus(bus)) - return 0; - - /* Configure and set up BAR0 */ - ks_pcie_set_dbi_mode(ks_pcie); - - /* Enable BAR0 */ - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1); - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1); - - ks_pcie_clear_dbi_mode(ks_pcie); - - /* - * For BAR0, just setting bus address for inbound writes (MSI) should - * be sufficient. Use physical address to avoid any conflicts. - */ - dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start); - - return 0; -} - static struct pci_ops ks_pcie_ops =3D { .map_bus =3D dw_pcie_own_conf_map_bus, .read =3D pci_generic_config_read, .write =3D pci_generic_config_write, - .add_bus =3D ks_pcie_v3_65_add_bus, }; =20 /** --=20 2.40.1