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[78.88.45.141]) by smtp.gmail.com with ESMTPSA id i8-20020a17090671c800b00a46d4e26301sm4523807ejk.27.2024.03.26.12.42.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Mar 2024 12:42:44 -0700 (PDT) From: Konrad Dybcio Date: Tue, 26 Mar 2024 20:42:34 +0100 Subject: [PATCH 3/4] interconnect: qcom: icc-rpm: Make simple functions return void Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240326-topic-rpm_icc_qos_cleanup-v1-3-357e736792be@linaro.org> References: <20240326-topic-rpm_icc_qos_cleanup-v1-0-357e736792be@linaro.org> In-Reply-To: <20240326-topic-rpm_icc_qos_cleanup-v1-0-357e736792be@linaro.org> To: Bjorn Andersson , Georgi Djakov , Shawn Guo Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Stephan Gerhold , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1711482160; l=7134; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=wB9I6D7BQJWznN8UthzGm+vDfU+W6H61008voNH+YNg=; b=y68BVQ60c5ekdqx/JspG4LRXqNIy5iwcJjZJxz0kWref3DQwaEL4g4XqOWx2hwAotRPjK7FBC pdqGQ3XbWDcCXJlav9pGlfMhACZVm63VM9J86rItGkHEkDs4T94yILR X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Register accesses can't just randomly fail. Change the return type of functions that only do that to void. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/interconnect/qcom/icc-rpm.c | 110 +++++++++++++++-----------------= ---- 1 file changed, 47 insertions(+), 63 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qco= m/icc-rpm.c index a8ed435f696c..0169de588a46 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -50,30 +50,27 @@ =20 #define ICC_BUS_CLK_MIN_RATE 19200ULL /* kHz */ =20 -static int qcom_icc_set_qnoc_qos(struct icc_node *src) +static void qcom_icc_set_qnoc_qos(struct icc_node *src) { struct icc_provider *provider =3D src->provider; struct qcom_icc_provider *qp =3D to_qcom_provider(provider); struct qcom_icc_node *qn =3D src->data; struct qcom_icc_qos *qos =3D &qn->qos; - int rc; - - rc =3D regmap_update_bits(qp->regmap, - qp->qos_offset + QNOC_QOS_MCTL_LOWn_ADDR(qos->qos_port), - QNOC_QOS_MCTL_DFLT_PRIO_MASK, - qos->areq_prio << QNOC_QOS_MCTL_DFLT_PRIO_SHIFT); - if (rc) - return rc; - - return regmap_update_bits(qp->regmap, - qp->qos_offset + QNOC_QOS_MCTL_LOWn_ADDR(qos->qos_port), - QNOC_QOS_MCTL_URGFWD_EN_MASK, - !!qos->urg_fwd_en << QNOC_QOS_MCTL_URGFWD_EN_SHIFT); + + regmap_update_bits(qp->regmap, + qp->qos_offset + QNOC_QOS_MCTL_LOWn_ADDR(qos->qos_port), + QNOC_QOS_MCTL_DFLT_PRIO_MASK, + qos->areq_prio << QNOC_QOS_MCTL_DFLT_PRIO_SHIFT); + + regmap_update_bits(qp->regmap, + qp->qos_offset + QNOC_QOS_MCTL_LOWn_ADDR(qos->qos_port), + QNOC_QOS_MCTL_URGFWD_EN_MASK, + !!qos->urg_fwd_en << QNOC_QOS_MCTL_URGFWD_EN_SHIFT); } =20 -static int qcom_icc_bimc_set_qos_health(struct qcom_icc_provider *qp, - struct qcom_icc_qos *qos, - int regnum) +static void qcom_icc_bimc_set_qos_health(struct qcom_icc_provider *qp, + struct qcom_icc_qos *qos, + int regnum) { u32 val; u32 mask; @@ -90,19 +87,18 @@ static int qcom_icc_bimc_set_qos_health(struct qcom_icc= _provider *qp, mask |=3D M_BKE_HEALTH_CFG_LIMITCMDS_MASK; } =20 - return regmap_update_bits(qp->regmap, - qp->qos_offset + M_BKE_HEALTH_CFG_ADDR(regnum, qos->qos_port), - mask, val); + regmap_update_bits(qp->regmap, + qp->qos_offset + M_BKE_HEALTH_CFG_ADDR(regnum, qos->qos_port), + mask, val); } =20 -static int qcom_icc_set_bimc_qos(struct icc_node *src) +static void qcom_icc_set_bimc_qos(struct icc_node *src) { struct qcom_icc_provider *qp; struct qcom_icc_node *qn; struct icc_provider *provider; u32 mode =3D NOC_QOS_MODE_BYPASS; u32 val =3D 0; - int i, rc =3D 0; =20 qn =3D src->data; provider =3D src->provider; @@ -115,48 +111,42 @@ static int qcom_icc_set_bimc_qos(struct icc_node *src) * only if we are NOT in Bypass Mode. */ if (mode !=3D NOC_QOS_MODE_BYPASS) { - for (i =3D 3; i >=3D 0; i--) { - rc =3D qcom_icc_bimc_set_qos_health(qp, - &qn->qos, i); - if (rc) - return rc; - } + qcom_icc_bimc_set_qos_health(qp, &qn->qos, 3); + qcom_icc_bimc_set_qos_health(qp, &qn->qos, 2); + qcom_icc_bimc_set_qos_health(qp, &qn->qos, 1); + qcom_icc_bimc_set_qos_health(qp, &qn->qos, 0); =20 /* Set BKE_EN to 1 when Fixed, Regulator or Limiter Mode */ val =3D 1; } =20 - return regmap_update_bits(qp->regmap, - qp->qos_offset + M_BKE_EN_ADDR(qn->qos.qos_port), - M_BKE_EN_EN_BMASK, val); + regmap_update_bits(qp->regmap, + qp->qos_offset + M_BKE_EN_ADDR(qn->qos.qos_port), + M_BKE_EN_EN_BMASK, val); } =20 -static int qcom_icc_noc_set_qos_priority(struct qcom_icc_provider *qp, +static void qcom_icc_noc_set_qos_priority(struct qcom_icc_provider *qp, struct qcom_icc_qos *qos) { u32 val; - int rc; =20 /* Must be updated one at a time, P1 first, P0 last */ val =3D qos->areq_prio << NOC_QOS_PRIORITY_P1_SHIFT; - rc =3D regmap_update_bits(qp->regmap, - qp->qos_offset + NOC_QOS_PRIORITYn_ADDR(qos->qos_port), - NOC_QOS_PRIORITY_P1_MASK, val); - if (rc) - return rc; - - return regmap_update_bits(qp->regmap, - qp->qos_offset + NOC_QOS_PRIORITYn_ADDR(qos->qos_port), - NOC_QOS_PRIORITY_P0_MASK, qos->prio_level); + regmap_update_bits(qp->regmap, + qp->qos_offset + NOC_QOS_PRIORITYn_ADDR(qos->qos_port), + NOC_QOS_PRIORITY_P1_MASK, val); + + regmap_update_bits(qp->regmap, + qp->qos_offset + NOC_QOS_PRIORITYn_ADDR(qos->qos_port), + NOC_QOS_PRIORITY_P0_MASK, qos->prio_level); } =20 -static int qcom_icc_set_noc_qos(struct icc_node *src) +static void qcom_icc_set_noc_qos(struct icc_node *src) { struct qcom_icc_provider *qp; struct qcom_icc_node *qn; struct icc_provider *provider; u32 mode =3D NOC_QOS_MODE_BYPASS_VAL; - int rc =3D 0; =20 qn =3D src->data; provider =3D src->provider; @@ -166,15 +156,12 @@ static int qcom_icc_set_noc_qos(struct icc_node *src) dev_dbg(src->provider->dev, "NoC QoS: Skipping %s: vote aggregated on parent.\n", qn->name); - return 0; } =20 if (qn->qos.qos_mode =3D=3D NOC_QOS_MODE_FIXED) { dev_dbg(src->provider->dev, "NoC QoS: %s: Set Fixed mode\n", qn->name); mode =3D NOC_QOS_MODE_FIXED_VAL; - rc =3D qcom_icc_noc_set_qos_priority(qp, &qn->qos); - if (rc) - return rc; + qcom_icc_noc_set_qos_priority(qp, &qn->qos); } else if (qn->qos.qos_mode =3D=3D NOC_QOS_MODE_BYPASS) { dev_dbg(src->provider->dev, "NoC QoS: %s: Set Bypass mode\n", qn->name); mode =3D NOC_QOS_MODE_BYPASS_VAL; @@ -182,12 +169,12 @@ static int qcom_icc_set_noc_qos(struct icc_node *src) /* How did we get here? */ } =20 - return regmap_update_bits(qp->regmap, - qp->qos_offset + NOC_QOS_MODEn_ADDR(qn->qos.qos_port), - NOC_QOS_MODEn_MASK, mode); + regmap_update_bits(qp->regmap, + qp->qos_offset + NOC_QOS_MODEn_ADDR(qn->qos.qos_port), + NOC_QOS_MODEn_MASK, mode); } =20 -static int qcom_icc_qos_set(struct icc_node *node) +static void qcom_icc_qos_set(struct icc_node *node) { struct qcom_icc_provider *qp =3D to_qcom_provider(node->provider); struct qcom_icc_node *qn =3D node->data; @@ -196,11 +183,14 @@ static int qcom_icc_qos_set(struct icc_node *node) =20 switch (qp->type) { case QCOM_ICC_BIMC: - return qcom_icc_set_bimc_qos(node); + qcom_icc_set_bimc_qos(node); + break; case QCOM_ICC_QNOC: - return qcom_icc_set_qnoc_qos(node); + qcom_icc_set_qnoc_qos(node); + break; default: - return qcom_icc_set_noc_qos(node); + qcom_icc_set_noc_qos(node); + break; } } =20 @@ -586,14 +576,8 @@ int qnoc_probe(struct platform_device *pdev) =20 /* Set QoS registers (we only need to do it once, generally) */ if (qnodes[i]->qos.ap_owned && - qnodes[i]->qos.qos_mode !=3D NOC_QOS_MODE_INVALID) { - ret =3D qcom_icc_qos_set(node); - if (ret) { - clk_bulk_disable_unprepare(qp->num_intf_clks, - qp->intf_clks); - goto err_remove_nodes; - } - } + qnodes[i]->qos.qos_mode !=3D NOC_QOS_MODE_INVALID) + qcom_icc_qos_set(node); =20 data->nodes[i] =3D node; } --=20 2.44.0