From nobody Mon Feb 9 05:44:01 2026 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA16E7317C; Mon, 25 Mar 2024 15:39:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711381153; cv=none; b=C0EuOaFQQcRc5XSKyBWULNVkm9/7yCf41yLH+h88CZjEjH1L6jS3xtZkAjVnCnXye8BzDvaxJG1HYYZ6168vtapAQ8C82c15OZC+w/e9jkYYmZCqr0/Ejjtt+8ojwDxzjs9kNGR2gVMIMwzYi8N+XPVfEs+QNz5jL+8dkHSKvVY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711381153; c=relaxed/simple; bh=I3p4Ib0ISW7IQcsOO8wa91qosPmVrlgxRcCilUELSWY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MdGFlUzUBnR/vDVU0ZAHhsyf9Xj91mNBAbbjU2xx3BuHzg18gacEhmE/g1VV5VWmZ5ESx00isEN93BOF3IM71vjig1AeSqFCDd223ClAiIIpgR/4DR5kRhpseoLjI56Y/TOV/6y4A2KvbNF/8jho6xQVY6Rmirot+04oK3aKvEs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=SPwZ4Igs; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="SPwZ4Igs" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1711381148; bh=I3p4Ib0ISW7IQcsOO8wa91qosPmVrlgxRcCilUELSWY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SPwZ4Igslqq8cVcUFNt0jAQDh1F57pq5lT93gOA2EuPpG6+DiNigoyClRTBxq+top WukpDbcUjOWh/M3jWTqsLv+0tSwyTIGtEKvmoWAzswrwtuzSK4cvh7Vwa8uapVtlrR LOPL84gY8duLNLWn4B3yU3CUT0FFXL+8Oo3QOj7hEWIraOfENqwGraQ8ctl/2JM9OJ 6RYs3B4fHn+IPowVN2Lk978NnDooF7teQVhc3ypdYw7E+o/V1tL0AMeZOgx6T1SWue w0ZlAZntqlRwoTfcByFIX+mAPUb9dTOX7fynkXsl6Vk+HMGiFCSGvQ7hi2FJLOUIlS y3e7evKr9dG0A== Received: from jupiter.universe (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by madrid.collaboradmins.com (Postfix) with ESMTPSA id D350037820CA; Mon, 25 Mar 2024 15:39:07 +0000 (UTC) Received: by jupiter.universe (Postfix, from userid 1000) id 6F8BD4800CB; Mon, 25 Mar 2024 16:39:07 +0100 (CET) From: Sebastian Reichel To: Heiko Stuebner , linux-rockchip@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Boris Brezillon , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v1 1/4] arm64: defconfig: support Mali CSF-based GPUs Date: Mon, 25 Mar 2024 16:37:18 +0100 Message-ID: <20240325153850.189128-2-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240325153850.189128-1-sebastian.reichel@collabora.com> References: <20240325153850.189128-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable support for Mali CSF-based GPUs, which is found on recent ARM SoCs, such as Rockchip or Mediatek. Signed-off-by: Sebastian Reichel --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 2c30d617e180..65e33174f813 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -907,6 +907,7 @@ CONFIG_DRM_MESON=3Dm CONFIG_DRM_PL111=3Dm CONFIG_DRM_LIMA=3Dm CONFIG_DRM_PANFROST=3Dm +CONFIG_DRM_PANTHOR=3Dm CONFIG_DRM_TIDSS=3Dm CONFIG_DRM_POWERVR=3Dm CONFIG_FB=3Dy --=20 2.43.0 From nobody Mon Feb 9 05:44:01 2026 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA1045A0F9; Mon, 25 Mar 2024 15:39:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711381153; cv=none; b=Bl6YWXhVdBZoANiINknRRXtbYofWjOQe+YB70v9VZar4UMZvuf/hhmKIyZ7Z0whJonH9Is3L+W+kYG25kYG+3cnOQROmbZEuZvwPqz3T77NGe1nCRQhB8Ay5F3Y4U2qQy2QT7h3MkXEibrelizjUEmHnQUB6Vv6fITTCKo8ZDrU= ARC-Message-Signature: i=1; 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charset="utf-8" From: Boris Brezillon Add Mali GPU Node to the RK3588 SoC DT including GPU clock operating points Signed-off-by: Boris Brezillon Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 56 +++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi index 87b83c87bd55..89d40cff635f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -501,6 +501,62 @@ usb_host2_xhci: usb@fcd00000 { status =3D "disabled"; }; =20 + gpu: gpu@fb000000 { + compatible =3D "rockchip,rk3588-mali", "arm,mali-valhall-csf"; + reg =3D <0x0 0xfb000000 0x0 0x200000>; + #cooling-cells =3D <2>; + assigned-clocks =3D <&scmi_clk SCMI_CLK_GPU>; + assigned-clock-rates =3D <200000000>; + clocks =3D <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, + <&cru CLK_GPU_STACKS>; + clock-names =3D "core", "coregroup", "stacks"; + dynamic-power-coefficient =3D <2982>; + interrupts =3D , + , + ; + interrupt-names =3D "job", "mmu", "gpu"; + operating-points-v2 =3D <&gpu_opp_table>; + power-domains =3D <&power RK3588_PD_GPU>; + status =3D "disabled"; + + gpu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + opp-microvolt =3D <675000 675000 850000>; + }; + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + opp-microvolt =3D <675000 675000 850000>; + }; + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + opp-microvolt =3D <675000 675000 850000>; + }; + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + opp-microvolt =3D <675000 675000 850000>; + }; + opp-700000000 { + opp-hz =3D /bits/ 64 <700000000>; + opp-microvolt =3D <700000 700000 850000>; + }; + opp-800000000 { + opp-hz =3D /bits/ 64 <800000000>; + opp-microvolt =3D <750000 750000 850000>; + }; + opp-900000000 { + opp-hz =3D /bits/ 64 <900000000>; + opp-microvolt =3D <800000 800000 850000>; + }; + opp-1000000000 { + opp-hz =3D /bits/ 64 <1000000000>; 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charset="utf-8" From: Boris Brezillon Enable the Mali GPU in the Rock 5B. Signed-off-by: Boris Brezillon Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/b= oot/dts/rockchip/rk3588-rock-5b.dts index 1fe8b2a0ed75..096ee7a98b89 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -180,6 +180,11 @@ &cpu_l3 { cpu-supply =3D <&vdd_cpu_lit_s0>; }; =20 +&gpu { + mali-supply =3D <&vdd_gpu_s0>; + status =3D "okay"; +}; + &i2c0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&i2c0m2_xfer>; @@ -470,6 +475,7 @@ rk806_dvs3_null: dvs3-null-pins { =20 regulators { vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-always-on; regulator-boot-on; regulator-min-microvolt =3D <550000>; regulator-max-microvolt =3D <950000>; --=20 2.43.0 From nobody Mon Feb 9 05:44:01 2026 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC7C37317F; Mon, 25 Mar 2024 15:39:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711381152; cv=none; b=EV5UfW990zmDIAU8USqqQk1z+tx9fhvcMrcuxqi8EZGPWAWhoYUwl70NqevLgExikRAJcMVAnrbP1QWHk9P+cGV/AmIHum7GliKzz+byj8KFaYrHzClftyq3k8YmTkrh4Ij/gOAyxErT9nPxV2tFP5PLxxlVkePR2Wt7/N6QKTU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711381152; c=relaxed/simple; bh=3v5iUw5gs5zUBSvUjIKafb/MEF4mCCtd8Xpd9HFcly8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FeYDa74/KqKtYFq5HseG0GJpjMHj/2Nl82F2XwM+4XzMpK14tVle3cLtHbPXXQifjytRWwehmlzQ5PUlqeY1yzFTxjUMzE9NXJheR3mkf4m2fkQ6cezOEfdJJDVh2dmwMO6tapw5JFYSHFI0WC8j5u/OUEUoSUxUrBQoF1xyMw8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=fWCbp4Iy; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="fWCbp4Iy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1711381148; bh=3v5iUw5gs5zUBSvUjIKafb/MEF4mCCtd8Xpd9HFcly8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fWCbp4IyGLzPOFMJJg+VSbS+HT7L1NzmN6dZqo2/wbtZlhKq39kskWcyQrnFtW8b6 +0k2/tsnUHdYS6TeqAzU6ChOATtBpTizePaVHfm9OJ0CP7nCn2DTxdQDTStsE+RsOv KjwXiZGyXz4K/SdBdLUoj4JSZuuURhKrJpxIBy53aD0gzrniU4EBvCf8bHwaWQgYZB TH7u2XWrFTkpObziBn0Ww19yAW1GBTg294N6OYHdGAQQLn7OlN6/822tXnjofJqI0f 83GnkCu0Q0ObPqfonpGcGYQriHRQrhiwy9zsXgpif3+55Ung38KNK8B1LKfYBzUFhG aadvHD++IKngw== Received: from jupiter.universe (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by madrid.collaboradmins.com (Postfix) with ESMTPSA id EE66E37820E4; Mon, 25 Mar 2024 15:39:07 +0000 (UTC) Received: by jupiter.universe (Postfix, from userid 1000) id 748AE4800D1; Mon, 25 Mar 2024 16:39:07 +0100 (CET) From: Sebastian Reichel To: Heiko Stuebner , linux-rockchip@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Boris Brezillon , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Sebastian Reichel Subject: [PATCH v1 4/4] arm64: dts: rockchip: rk3588-evb1: Enable GPU Date: Mon, 25 Mar 2024 16:37:21 +0100 Message-ID: <20240325153850.189128-5-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240325153850.189128-1-sebastian.reichel@collabora.com> References: <20240325153850.189128-1-sebastian.reichel@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Boris Brezillon Enable the Mali GPU in the RK3588 EVB1. Signed-off-by: Boris Brezillon Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/= boot/dts/rockchip/rk3588-evb1-v10.dts index de30c2632b8e..b51a17b404f3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -281,6 +281,12 @@ &gmac0_rgmii_clk status =3D "okay"; }; =20 +&gpu { + mali-supply =3D <&vdd_gpu_s0>; + sram-supply =3D <&vdd_gpu_mem_s0>; + status =3D "okay"; +}; + &i2c2 { status =3D "okay"; =20 @@ -484,12 +490,15 @@ rk806_dvs3_null: dvs3-null-pins { =20 regulators { vdd_gpu_s0: dcdc-reg1 { + regulator-always-on; regulator-boot-on; regulator-min-microvolt =3D <550000>; regulator-max-microvolt =3D <950000>; regulator-ramp-delay =3D <12500>; regulator-name =3D "vdd_gpu_s0"; regulator-enable-ramp-delay =3D <400>; + regulator-coupled-with =3D <&vdd_gpu_mem_s0>; + regulator-coupled-max-spread =3D <10000>; regulator-state-mem { regulator-off-in-suspend; }; @@ -534,12 +543,15 @@ regulator-state-mem { }; =20 vdd_gpu_mem_s0: dcdc-reg5 { + regulator-always-on; regulator-boot-on; regulator-min-microvolt =3D <675000>; regulator-max-microvolt =3D <950000>; regulator-ramp-delay =3D <12500>; regulator-enable-ramp-delay =3D <400>; regulator-name =3D "vdd_gpu_mem_s0"; + regulator-coupled-with =3D <&vdd_gpu_s0>; + regulator-coupled-max-spread =3D <10000>; regulator-state-mem { regulator-off-in-suspend; }; --=20 2.43.0