From nobody Wed Dec 17 13:50:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9914515ADB0 for ; Mon, 25 Mar 2024 11:23:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711365836; cv=none; b=kvJw9+/ohXgJCS7BLkEv7SvTO41VIMFe3wbrI426yw3BTmMVMGIw9wqhvng9ahrIqj3ov/XQT6qGdei3eJMOAUtt1bDicVmIsjAov3216JLHr7YQm/kF19+G65k2bXrJWF7PfMNyTsErXYua3rQ4GiwUBw42WxjZRfndswTYAS8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711365836; c=relaxed/simple; bh=TkQFAl0y/SHZ/rPLxSlv1JjtbvVld+zmq7CDJ3afisw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=O/fS0858dJqqdJ2ThJ4Qeldx6joFou/ydtpwz+nXmgzpvreHSO+QBsd745kUkyh1QHeirss7qyZU96Lx05bkXTqRw39QKpk7sSDkcNzePt2fhN3bxSOPhnyLjYT8oWzoO7cNE3+5rO9Q0VhoaCgnSy/kguMkI4SVy8SJJUX71Os= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WDstMSAU; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WDstMSAU" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6D14AC433F1; Mon, 25 Mar 2024 11:23:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711365836; bh=TkQFAl0y/SHZ/rPLxSlv1JjtbvVld+zmq7CDJ3afisw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WDstMSAUtMz3dbEcVm+KLj1GR9k7r52hnpVzlF2STimuRRvPFMDaOrFV7Ov/86urM zkXfEq9MVCWVOD9OWWqn7Drl8ilkELX/EqjZG6TzDk7LfjGKaAs+wfBGaUDX3u2v5i KeSkxzv2cEv+9KJbpqxro/uYf9da5AiVxCu71SIB86Fx2MsLQI3kZDailyNKwl1VIl BT++7eVE+OcTA6uRxlJuy3a5oLyc8cTSBl6kJ0AEkSYOp4+4pkwrdvzfJgv9eGXoQ3 1HCQ4zA7BRYic/5jofv/E1MRs15h7yHC0sJZZdCB1JdpRT4JkkZZJ2FWTZzQRLlsES 41Wunpx0FrcUg== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Andrea Parri Subject: [PATCH v3 RESEND 1/2] riscv: select ARCH_USE_CMPXCHG_LOCKREF Date: Mon, 25 Mar 2024 19:10:37 +0800 Message-ID: <20240325111038.1700-2-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240325111038.1700-1-jszhang@kernel.org> References: <20240325111038.1700-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Select ARCH_USE_CMPXCHG_LOCKREF to enable the cmpxchg-based lockless lockref implementation for riscv. Using Linus' test case[1] on TH1520 platform, I see a 11.2% improvement. On JH7110 platform, I see 12.0% improvement. Link: http://marc.info/?l=3Dlinux-fsdevel&m=3D137782380714721&w=3D4 [1] Signed-off-by: Jisheng Zhang Reviewed-by: Andrea Parri --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index aba42b2bf660..7895c77545f1 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -58,6 +58,7 @@ config RISCV select ARCH_SUPPORTS_PAGE_TABLE_CHECK if MMU select ARCH_SUPPORTS_PER_VMA_LOCK if MMU select ARCH_SUPPORTS_SHADOW_CALL_STACK if HAVE_SHADOW_CALL_STACK + select ARCH_USE_CMPXCHG_LOCKREF if 64BIT select ARCH_USE_MEMTEST select ARCH_USE_QUEUED_RWLOCKS select ARCH_USES_CFI_TRAPS if CFI_CLANG --=20 2.43.0 From nobody Wed Dec 17 13:50:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC60D157498 for ; Mon, 25 Mar 2024 11:23:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711365838; cv=none; b=Vu16PHBciOyID56y0l1ez2lIWzldE9pG7KFDkNz1XBoJAGgUPA3OXj+9FGRT/QRi8l/egno9sHx8CsTXfx5SeSkeBr1s3ddOB1/D5usv080mVP3wEVF/zpty6THyhlpUVZpuhox8Z2ZrMzh0IHOs0/7vXljn5McRFmbhARmOkjk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711365838; c=relaxed/simple; bh=Hcvo8TwKTObsbxJiMa+DCZVgn0Ppw92GI2jy5pNrT8U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BI1eaBORYwU6ju/f2xMNM2eML5hk1yM5FFiRUlHKvMgxdhbaiMMDG1XCf+E4f06Ll2tikbef39co25DOO3RqzMOv5COiWm7R608pUlP+2+Pv4Ka0dN0g2+2FBhWJQMCZk/IgWORb7tGKjN4iGBPqHClltsz8MAPZYvuza5KjWeI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jO7CNTxY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jO7CNTxY" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A096BC43390; Mon, 25 Mar 2024 11:23:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711365838; bh=Hcvo8TwKTObsbxJiMa+DCZVgn0Ppw92GI2jy5pNrT8U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jO7CNTxYsgsZN0RpxKG0TpN4fr1dM9M9yxv+ojbrGrYYXRCbxXahb8xuDan7vP8sv WZyGX8W3kdx6Sxf8n/Z4HZurOBXMK+LrW4JFiFNZmBOFzKzLm6Y+42MyT6FMGmF1fk Z4AzEMBU5CArTOI6LXvuNA7YziuXIF6N0YwuTB/vevJAcO9LNJ1TXwdeOvrXoKYkyk mvUEqRJG9njKVzoKQ6AEE2XMd8qCvc3/TwmTk3Ad5CsAAPU13aPUHfPI4yoTpIEagU XjpT785o1D9K11kj7r5hzg5D287Bfzs5kdqvojZ0NEF0zfwweC6jBN/aGINOws2wxp B/O4bxQ5adlbg== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Andrea Parri Subject: [PATCH v3 RESEND 2/2] riscv: cmpxchg: implement arch_cmpxchg64_{relaxed|acquire|release} Date: Mon, 25 Mar 2024 19:10:38 +0800 Message-ID: <20240325111038.1700-3-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240325111038.1700-1-jszhang@kernel.org> References: <20240325111038.1700-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" After selecting ARCH_USE_CMPXCHG_LOCKREF, one straight futher optimization is implementing the arch_cmpxchg64_relaxed() because the lockref code does not need the cmpxchg to have barrier semantics. At the same time, implement arch_cmpxchg64_acquire and arch_cmpxchg64_release as well. However, on both TH1520 and JH7110 platforms, I didn't see obvious performance improvement with Linus' test case [1]. IMHO, this may be related with the fence and lr.d/sc.d hw implementations. In theory, lr/sc without fence could give performance improvement over lr/sc plus fence, so add the code here to leave performance improvement room on newer HW platforms. Link: http://marc.info/?l=3Dlinux-fsdevel&m=3D137782380714721&w=3D4 [1] Signed-off-by: Jisheng Zhang Reviewed-by: Andrea Parri --- arch/riscv/include/asm/cmpxchg.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpx= chg.h index 2fee65cc8443..f1c8271c66f8 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -359,4 +359,22 @@ arch_cmpxchg_relaxed((ptr), (o), (n)); \ }) =20 +#define arch_cmpxchg64_relaxed(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) !=3D 8); \ + arch_cmpxchg_relaxed((ptr), (o), (n)); \ +}) + +#define arch_cmpxchg64_acquire(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) !=3D 8); \ + arch_cmpxchg_acquire((ptr), (o), (n)); \ +}) + +#define arch_cmpxchg64_release(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) !=3D 8); \ + arch_cmpxchg_release((ptr), (o), (n)); \ +}) + #endif /* _ASM_RISCV_CMPXCHG_H */ --=20 2.43.0