From nobody Fri Dec 19 20:13:35 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D9FF181D16; Sun, 24 Mar 2024 23:49:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711324147; cv=none; b=dnO5MdBGYlJ06MqvEg5n1ADYWGFAsUg4CRjm4fSd7kFlTYI4QXtgiLN9YkJ5PdA0FTAnUjvbFb2d0kj8FQim7slAZpTp6f8vXnGadQJdgAslm3De7fweKk06PTY4FfF6TMx14+jOt1mPQ5A8Se5PH08CEiMFx0FOgMGViW/xTJU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711324147; c=relaxed/simple; bh=GasxbuW90lsjKa6WhOQETR31tGoaeHe/4jBfXK0euBo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Al3GCg4/4Y7rFXZdTlp2yiL9V5QlZHiitjU30x87LIH/wMFaV3IqHjlbL4gWamQtSU+yO3G3d2r+3gRteJKTkX+un7SJcvKYprZjciRfmIOPgUEeX6pTHix4NLk9x2kvMvppjPYJVrHgADCgnT7cZZ2y7y7SHJ3W+JK3HqNjaqo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iP6AXD2r; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iP6AXD2r" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C25E0C433B1; Sun, 24 Mar 2024 23:49:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711324146; bh=GasxbuW90lsjKa6WhOQETR31tGoaeHe/4jBfXK0euBo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iP6AXD2rsttIVqdE/5Qq4NuGdb3Id++3eK9ob+JZGX9Ynd5rZYuM9/uJUVHlDYVkl 3mIdxHjN5l60XL6rTwoKCphKUnSrh5FFXijukLRt1OOBifiA99YRiH0FiERkjY8q99 RD9QQhYsZDePNqn7CF28sEst2cAr5nLRD6bFsANWiIaGNU1czCCtQ3K8aL2ZbrRo6J OQ+h0vJMADaJpiKW+Qo+C7VtJVaPWJvSXnSOHkYfDoZvRe6XbSNrXGkBqnXZBwao1B 3MDDV6vanxGpU/9ayccH17wrOF4uC95Q9lyX5slN6BTnF5F65l8O7vgKCwnGA3j3uu RLE1dxj8lDslg== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Paloma Arellano , Dmitry Baryshkov , Sasha Levin Subject: [PATCH 5.4 142/183] drm/msm/dpu: add division of drm_display_mode's hskew parameter Date: Sun, 24 Mar 2024 19:45:55 -0400 Message-ID: <20240324234638.1355609-143-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240324234638.1355609-1-sashal@kernel.org> References: <20240324234638.1355609-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Paloma Arellano [ Upstream commit 551ee0f210991d25f336bc27262353bfe99d3eed ] Setting up the timing engine when the physical encoder has a split role neglects dividing the drm_display_mode's hskew parameter. Let's fix this since this must also be done in preparation for implementing YUV420 over DP. Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Paloma Arellano Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/579605/ Link: https://lore.kernel.org/r/20240222194025.25329-3-quic_parellan@quicin= c.com Signed-off-by: Dmitry Baryshkov Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers= /gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index b9c84fb4d4a1f..311863a05a6fa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -258,12 +258,14 @@ static void dpu_encoder_phys_vid_setup_timing_engine( mode.htotal >>=3D 1; mode.hsync_start >>=3D 1; mode.hsync_end >>=3D 1; + mode.hskew >>=3D 1; =20 DPU_DEBUG_VIDENC(phys_enc, - "split_role %d, halve horizontal %d %d %d %d\n", + "split_role %d, halve horizontal %d %d %d %d %d\n", phys_enc->split_role, mode.hdisplay, mode.htotal, - mode.hsync_start, mode.hsync_end); + mode.hsync_start, mode.hsync_end, + mode.hskew); } =20 drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params); --=20 2.43.0