From nobody Fri Dec 19 20:14:02 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0653F181CE3; Sun, 24 Mar 2024 23:48:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711324125; cv=none; b=OIfHHy/oYTzzLGa6sFPsMnvHFOhzW+gn5AGs6g2Jij1wZNoEAnFLiclfXSTnSLhmso2reALS9OBeHPlUIhUQrqYsV4Eg2VqrKf5cE49HK+mYeEhtCWG6MfskFCG4I6zqAvrpIS2yrBo16Py2cHAoPbJ1TCGuxbL0zCGjQDx8R4E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711324125; c=relaxed/simple; bh=ZfOUDs7jrsD7iao803en/1YeW13GBtchnkANuEkhMvg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BWsevuMwy6ySIvTmzlhAl56jq3+xpS2MWmbbHAEww8K1XdvbDeQ6GXePsGVZfxwbMdDVd6YFeH5RrMQRN0LyGvQiXGSsQqTHzI8TlrbbogAQbjBtDcCqQ/WRbp8GyXffr+ZNWVyI4YjjHm9LtliVa3bNdxQWvYYivGoXw8UoxUs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jeeO3puJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jeeO3puJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C8671C433F1; Sun, 24 Mar 2024 23:48:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711324123; bh=ZfOUDs7jrsD7iao803en/1YeW13GBtchnkANuEkhMvg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jeeO3puJDqmVnndLpd4HmSdi+r92n1fbS344j7W6Ou59JvenNMqXE47j3MNT+HAwX 3dphW8DktwRiTndCTpZnCccRfXg2zmRQo8ymL43abckFPB1UQ3wB9+laiP5MvXGPIe KR+Gf8S6buU5L/azwNcG5S1kjoqBl4BoxZcQmWhjsF+bO0V7Tl7z4W0OZwdDuAxK4+ pkMjUjyb4magu36sksLvVZOpmle5Vrd6vogr1BRaRKuxDvjQiMyZ2EOwRIvBo26jGm tXyQsVy5lLG5SZ2/nOZZxlVro3WJEwsVLxwqPhnpAT8jOS7HIGG/y1jAMFLptVbp0z /75HNGgdgyihA== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Konrad Dybcio , Caleb Connolly , Bjorn Andersson , Sasha Levin Subject: [PATCH 5.4 121/183] clk: qcom: dispcc-sdm845: Adjust internal GDSC wait times Date: Sun, 24 Mar 2024 19:45:34 -0400 Message-ID: <20240324234638.1355609-122-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240324234638.1355609-1-sashal@kernel.org> References: <20240324234638.1355609-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Konrad Dybcio [ Upstream commit 117e7dc697c2739d754db8fe0c1e2d4f1f5d5f82 ] SDM845 downstream uses non-default values for GDSC internal waits. Program them accordingly to avoid surprises. Fixes: 81351776c9fb ("clk: qcom: Add display clock controller driver for SD= M845") Signed-off-by: Konrad Dybcio Tested-by: Caleb Connolly # OnePlus 6 Link: https://lore.kernel.org/r/20240103-topic-845gdsc-v1-1-368efbe1a61d@li= naro.org Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin --- drivers/clk/qcom/dispcc-sdm845.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm= 845.c index 0cc4909b5dbef..cb7a2d9247b04 100644 --- a/drivers/clk/qcom/dispcc-sdm845.c +++ b/drivers/clk/qcom/dispcc-sdm845.c @@ -569,6 +569,8 @@ static struct clk_branch disp_cc_mdss_vsync_clk =3D { =20 static struct gdsc mdss_gdsc =3D { .gdscr =3D 0x3000, + .en_few_wait_val =3D 0x6, + .en_rest_wait_val =3D 0x5, .pd =3D { .name =3D "mdss_gdsc", }, --=20 2.43.0