From nobody Fri Dec 19 19:16:01 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BBDA17B509; Sun, 24 Mar 2024 23:42:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711323724; cv=none; b=Lip1Aauxc1FttVTL0b5YPpgzRqoV6CiaCp24Opyc7pQDwvxzV12FannsprT+bh+YAbyPpKjRBcnzq5gyBpbNhArM3zYpkQ39oLHc5uXqydFvZCEBIszkOfboY7n6bnxXGp39q6aTR5eMwoVvz6nm0q9v6d9rQmSsfBLj+ZGd7Ik= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711323724; c=relaxed/simple; bh=wTx2CP0rQOPjoKpSAi8r0GICFQMvOfBkNPFf9R3b24w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BwIbj8OHjYIwudEZSXS78H+qd6PIe24VBSO74HrtKZR9MT8wh/cSwzYIOQnd2Cr2s6hFmY7wRRQHMF43Drb+H9eL9QU5iOfu2QQ+c6N7UktWdnoBKq9716iRGs+vLjeJLwSJ7UNPxOiLCahKEI+fPhQ7kC25dU3taP6ARYVEOXI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oKVDcEXm; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oKVDcEXm" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 47AA8C433A6; Sun, 24 Mar 2024 23:42:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711323724; bh=wTx2CP0rQOPjoKpSAi8r0GICFQMvOfBkNPFf9R3b24w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oKVDcEXmVTlUt+yV/kg46kkOkfErAaoyRqcHMQxZrk4MzeEcqM7GWFu2FeNBavRvw 5NdKjWHpl3/ggAwZDyi8LpKdgjna+/czSRh2fEgVnxV1yHqV/b9vElA4ripPUs2nYU 606KIEXeKW1FrZkq4M9K78Sfmyevv28CGclI5MPpYaDaSUD9NYE5gE4Db0X7kagGeO 7I8BB9od03YPgzkv5VW0QlckyHdiUKkj1Av2ZyLhCHdmuXRBlMF0QcuIYJqagXy6Yw 4ZW5BFfvBCRExTIh9aGrUqnR+pAtAi3oJALbkzMIOwwnhyjhZRK9UgJT4WePVlIrWc QX/IxG29/SH1g== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Tommaso Merciai , Michael Trimarchi , Alberto Bianchi , Andrew Lunn , "David S . Miller" , Sasha Levin Subject: [PATCH 5.10 097/238] net: phy: DP83822: enable rgmii mode if phy_interface_is_rgmii Date: Sun, 24 Mar 2024 19:38:05 -0400 Message-ID: <20240324234027.1354210-98-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240324234027.1354210-1-sashal@kernel.org> References: <20240324234027.1354210-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Tommaso Merciai [ Upstream commit 621427fbdada788f18f77238e1c36f463c2cb9d1 ] RGMII mode can be enable from dp83822 straps, and also writing bit 9 of register 0x17 - RMII and Status Register (RCSR). When phy_interface_is_rgmii rgmii mode must be enabled, same for contrary, this prevents malconfigurations of hw straps References: - https://www.ti.com/lit/gpn/dp83822i p66 Signed-off-by: Tommaso Merciai Co-developed-by: Michael Trimarchi Suggested-by: Alberto Bianchi Tested-by: Tommaso Merciai Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller Stable-dep-of: c8a5c731fd12 ("net: phy: dp83822: Fix RGMII TX delay configu= ration") Signed-off-by: Sasha Levin --- drivers/net/phy/dp83822.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c index 81412999445d8..dce87589b1120 100644 --- a/drivers/net/phy/dp83822.c +++ b/drivers/net/phy/dp83822.c @@ -94,7 +94,8 @@ #define DP83822_WOL_INDICATION_SEL BIT(8) #define DP83822_WOL_CLR_INDICATION BIT(11) =20 -/* RSCR bits */ +/* RCSR bits */ +#define DP83822_RGMII_MODE_EN BIT(9) #define DP83822_RX_CLK_SHIFT BIT(12) #define DP83822_TX_CLK_SHIFT BIT(11) =20 @@ -386,6 +387,12 @@ static int dp83822_config_init(struct phy_device *phyd= ev) if (err) return err; } + + phy_set_bits_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); + } else { + phy_clear_bits_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); } =20 if (dp83822->fx_enabled) { --=20 2.43.0