From nobody Tue Dec 23 09:39:26 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 251F617C6AE; Sun, 24 Mar 2024 23:43:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711323782; cv=none; b=fESKrNHndUaO06QCyxa4osXhAKGQTUqQuDWuG6kV/758g7drRA2oCVYJFufArklaWvZJLvmVP0XK8oNr5YR/GzVlhr+MINaZRcuXWniXIMcH3Av1wZrttW30ZzUxPYaKdEAfMLMM50c/xRhuJYDD4jhcPhvAZ1JhfQtIrZMmyts= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711323782; c=relaxed/simple; bh=Drqi5r3d6775OKi+5Qy3gKeom29Vnn5yKc0wag/duSQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Yemp1Wjd/GnPRCdvIQBXQYks0AInioSsUJLt1m8yNVNsQ8gpk9ZPaMSD+gr4LC5LC1gD4nf8jnRxxW3V+roqfScaGdi26o7l1bdDxbdEfbkplC/nB/iJ3I8ayTssByumv1ES6YwdTfbEhgo+5SQ1jJNmPOBFPS8My2iE6KIu1cM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=T8sI8W2t; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="T8sI8W2t" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 45F22C43399; Sun, 24 Mar 2024 23:43:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711323782; bh=Drqi5r3d6775OKi+5Qy3gKeom29Vnn5yKc0wag/duSQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=T8sI8W2tvKzu0P9n08vc40t+uekqbUn11wkblzaE/4IlOik0ULfGVA2pI0EHxsiV/ HK5mJ/oG1NyG+YzmagDprCrPFGgnAqcJiyfF/TWJyh+xfd11/EC+LKb07+kmOK+zBB Amb5zyc+QOZBIqO3j9X6wGJ06DWUpkbMyYzZWLkZADRgfaD9Vt690Rvq7cWfhliDcM SbDgEk0d3bD4WXDRZuH61vAKw8PVMDUCN+PrMe4FVu2HWQsLiEPV4c+txIvc78L0Ht sfvumKGej2IXW+HX0FcKdobi4121lqOxD9jHeROC0KxBQSZKEqSX8236XWcWJRJLWo 5Bc+gaLc1srSQ== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Konrad Dybcio , Caleb Connolly , Bjorn Andersson , Sasha Levin Subject: [PATCH 5.10 158/238] clk: qcom: dispcc-sdm845: Adjust internal GDSC wait times Date: Sun, 24 Mar 2024 19:39:06 -0400 Message-ID: <20240324234027.1354210-159-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240324234027.1354210-1-sashal@kernel.org> References: <20240324234027.1354210-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Konrad Dybcio [ Upstream commit 117e7dc697c2739d754db8fe0c1e2d4f1f5d5f82 ] SDM845 downstream uses non-default values for GDSC internal waits. Program them accordingly to avoid surprises. Fixes: 81351776c9fb ("clk: qcom: Add display clock controller driver for SD= M845") Signed-off-by: Konrad Dybcio Tested-by: Caleb Connolly # OnePlus 6 Link: https://lore.kernel.org/r/20240103-topic-845gdsc-v1-1-368efbe1a61d@li= naro.org Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin --- drivers/clk/qcom/dispcc-sdm845.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm= 845.c index 5c932cd17b140..8cd8174ac9aa7 100644 --- a/drivers/clk/qcom/dispcc-sdm845.c +++ b/drivers/clk/qcom/dispcc-sdm845.c @@ -768,6 +768,8 @@ static struct clk_branch disp_cc_mdss_vsync_clk =3D { =20 static struct gdsc mdss_gdsc =3D { .gdscr =3D 0x3000, + .en_few_wait_val =3D 0x6, + .en_rest_wait_val =3D 0x5, .pd =3D { .name =3D "mdss_gdsc", }, --=20 2.43.0