From nobody Wed Oct 15 22:47:49 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5C0E5B1FB; Sun, 24 Mar 2024 23:38:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711323529; cv=none; b=MTGbcq8+8T0USdrmVvZs/42gp6vNCAKOvs/rys3lwFrX+k5hlywhXDJtvEbbGQ7AOaQb0xyFSQbVkB+dEnLTaHci3txkMZei39BmBR8UcOhMWhKdtkUcpC2iDhVniI2M+KCqR7enu/TMWNKDDL9zZSMWOT5UqBpXE3hGtdDAyuY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711323529; c=relaxed/simple; bh=bGqiKPptXOHEfqmYyIQqeo0MoA8k4E0MPRvyPCmNQ6U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=a1K1misgZz25dsSX9ZNRdEyq07symnBE48yUj53lgFdKjit1ZGWBoYwe7+8JtABSfno4ahGOt/O51LgenXevNQI/ZTxqSqqZwso2bMiIhrq90ukykoI3vQV+OsFbnDv8FUbB3K9pW2WL1dcK2d2WznQZt+mP0uWA3Sxc6qg88m0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VMCcMsWN; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VMCcMsWN" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2594FC43390; Sun, 24 Mar 2024 23:38:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711323529; bh=bGqiKPptXOHEfqmYyIQqeo0MoA8k4E0MPRvyPCmNQ6U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VMCcMsWNidWtTkK8fCbEl5HfFAu/LRIo1DgZ0mANV7t0ZbdQUaABXWp0ztacnwqfP WRcJXH7iIoNTIMuhbjEkcAPxAhTy1Y/hP89BSPV+ZxzT653VXwvPAjMvTX2Khu8G6N AjSqf4wfpvaPz/gOfFUsr0FlHLKen9N0GAlix1E1YJAycRA7prMOeSqb44Pz97ysn7 K6AVBWKMuKxljIAOd7xdQ0zlP3igbA2qRYhGoAGFG8xNMll597BZ6LpPg/alLTigBw hCs93yWKKwQlAKB23OVmlhmQ0SLR/jkUHQlcE/1Wc8EGI4Bq+PQlhXcgD2XRqVjOVr GAX4kpR24CQfw== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Paloma Arellano , Dmitry Baryshkov , Sasha Levin Subject: [PATCH 5.15 237/317] drm/msm/dpu: add division of drm_display_mode's hskew parameter Date: Sun, 24 Mar 2024 19:33:37 -0400 Message-ID: <20240324233458.1352854-238-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240324233458.1352854-1-sashal@kernel.org> References: <20240324233458.1352854-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Paloma Arellano [ Upstream commit 551ee0f210991d25f336bc27262353bfe99d3eed ] Setting up the timing engine when the physical encoder has a split role neglects dividing the drm_display_mode's hskew parameter. Let's fix this since this must also be done in preparation for implementing YUV420 over DP. Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Paloma Arellano Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/579605/ Link: https://lore.kernel.org/r/20240222194025.25329-3-quic_parellan@quicin= c.com Signed-off-by: Dmitry Baryshkov Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers= /gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 185379b185725..7c58e9ba71b77 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -267,12 +267,14 @@ static void dpu_encoder_phys_vid_setup_timing_engine( mode.htotal >>=3D 1; mode.hsync_start >>=3D 1; mode.hsync_end >>=3D 1; + mode.hskew >>=3D 1; =20 DPU_DEBUG_VIDENC(phys_enc, - "split_role %d, halve horizontal %d %d %d %d\n", + "split_role %d, halve horizontal %d %d %d %d %d\n", phys_enc->split_role, mode.hdisplay, mode.htotal, - mode.hsync_start, mode.hsync_end); + mode.hsync_start, mode.hsync_end, + mode.hskew); } =20 drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params); --=20 2.43.0