From nobody Fri Dec 19 18:43:33 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FA88152197; Sun, 24 Mar 2024 23:06:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711321598; cv=none; b=kKHKIDj6vGvXWPth0/b0mB4+IINqc9u7vtvHX31WV/cH8CLoNgGwZEaRIdlv08wVufwipwS4GJ20wcKC8zgwfjV/k5Bptew/Ikh9wCnx1qa5WgPcHIF0E8LhoZjVN2JvHAPFPwL4Rbbl964s5JPikS/Ifn0j83lMsZW9lLL/PPk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711321598; c=relaxed/simple; bh=eHTqfpRH4w1jwSBCjC/7u/xx40HMa+l75jbyu7n46y0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=t4815LuB52UzOmVtoKPa3taCEiGQwWjX+/W4GsIB4dGeEvhLMAgsNamSWzbH7I9DsGlrl4RTAfXyvSQ2UUTFaAkgehYCuJHmBcmfVxC0ycEahhd/SsquYEobh7f7jY/bXCL+WcUCElo5uDTP9duwoNpc3pc64nKojFSDz5oI0cc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=l6NxvZCl; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="l6NxvZCl" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BBF18C43394; Sun, 24 Mar 2024 23:06:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711321597; bh=eHTqfpRH4w1jwSBCjC/7u/xx40HMa+l75jbyu7n46y0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l6NxvZClaRLACLG82hZLLbvTD5IdjDqCuFT/HSJQDec6M0NgZ/+AhYVht/q83pAI3 T17db60RB+2vmKee/HqbJIpyPIu57CZ3gX31Cr1p82b/35ZeAA1k1/M2hnSQ3br/6H 1UdrZaGXA4wGH31RVZdniT/mT1JkfNdvuXoR9NBcJH+QThk7uNTrzX2MFfro5sJXY/ BHKVBoeEDfnkwbfHM2meP3uNPFR6I94wjnF0isOKYOdiPsuJnEXXKLKxUJiY14Byn/ c4bXd2+Uz3mM5H/gWqRp8lhpqv/0twHr5GutF8DSjRP5+BYiHy+mWj9Q2taFmVxWXq Pq+5SOuqFAqjQ== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Tim Pambor , Jakub Kicinski , Sasha Levin Subject: [PATCH 6.6 327/638] net: phy: dp83822: Fix RGMII TX delay configuration Date: Sun, 24 Mar 2024 18:56:04 -0400 Message-ID: <20240324230116.1348576-328-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240324230116.1348576-1-sashal@kernel.org> References: <20240324230116.1348576-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Tim Pambor [ Upstream commit c8a5c731fd1223090af57da33838c671a7fc6a78 ] The logic for enabling the TX clock shift is inverse of enabling the RX clock shift. The TX clock shift is disabled when DP83822_TX_CLK_SHIFT is set. Correct the current behavior and always write the delay configuration to ensure consistent delay settings regardless of bootloader configuration. Reference: https://www.ti.com/lit/ds/symlink/dp83822i.pdf p. 69 Fixes: 8095295292b5 ("net: phy: DP83822: Add setting the fixed internal del= ay") Signed-off-by: Tim Pambor Link: https://lore.kernel.org/r/20240305110608.104072-1-tp@osasysteme.de Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/phy/dp83822.c | 37 ++++++++++++++++++++----------------- 1 file changed, 20 insertions(+), 17 deletions(-) diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c index b7cb71817780c..29e1cbea6dc0c 100644 --- a/drivers/net/phy/dp83822.c +++ b/drivers/net/phy/dp83822.c @@ -380,7 +380,7 @@ static int dp83822_config_init(struct phy_device *phyde= v) { struct dp83822_private *dp83822 =3D phydev->priv; struct device *dev =3D &phydev->mdio.dev; - int rgmii_delay; + int rgmii_delay =3D 0; s32 rx_int_delay; s32 tx_int_delay; int err =3D 0; @@ -390,30 +390,33 @@ static int dp83822_config_init(struct phy_device *phy= dev) rx_int_delay =3D phy_get_internal_delay(phydev, dev, NULL, 0, true); =20 - if (rx_int_delay <=3D 0) - rgmii_delay =3D 0; - else - rgmii_delay =3D DP83822_RX_CLK_SHIFT; + /* Set DP83822_RX_CLK_SHIFT to enable rx clk internal delay */ + if (rx_int_delay > 0) + rgmii_delay |=3D DP83822_RX_CLK_SHIFT; =20 tx_int_delay =3D phy_get_internal_delay(phydev, dev, NULL, 0, false); + + /* Set DP83822_TX_CLK_SHIFT to disable tx clk internal delay */ if (tx_int_delay <=3D 0) - rgmii_delay &=3D ~DP83822_TX_CLK_SHIFT; - else rgmii_delay |=3D DP83822_TX_CLK_SHIFT; =20 - if (rgmii_delay) { - err =3D phy_set_bits_mmd(phydev, DP83822_DEVADDR, - MII_DP83822_RCSR, rgmii_delay); - if (err) - return err; - } + err =3D phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR, + DP83822_RX_CLK_SHIFT | DP83822_TX_CLK_SHIFT, rgmii_delay); + if (err) + return err; + + err =3D phy_set_bits_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); =20 - phy_set_bits_mmd(phydev, DP83822_DEVADDR, - MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); + if (err) + return err; } else { - phy_clear_bits_mmd(phydev, DP83822_DEVADDR, - MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); + err =3D phy_clear_bits_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); + + if (err) + return err; } =20 if (dp83822->fx_enabled) { --=20 2.43.0