From nobody Fri Dec 19 07:00:46 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3081A1EF7DC; Sun, 24 Mar 2024 22:57:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711321035; cv=none; b=iUAeKeXmPvHXITBraWgfdefrzp+AiTL75qnpIs1GbZR2SX/TsQ57kGiZdy1WGs9WYM4+C+Uox5n993V7ZNQ3j0yfJqbh99ZMogMvDeZglgc3NOFCrK03K9f7I/MgMDOaHCMXDNh6DHdGjSWQjADtUvbO4n1YH9gO0lgNhsL4jjU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711321035; c=relaxed/simple; bh=yUS06+jBKCnlD25vjcbgsGFLnvBZQdDnVaI/PR/gXtk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hsSkgprLlF6MCZnFlIPt40874sRnz4of1ZuBAYi8+3DOkGsLXJWVQs1lcXPed9kPVcv/I2HKTvHLIT+tQubMPxIM4mtoji169SjylbBu8GgS/D8GWvnUcvAkEInBy6IoMldgwSSb0xLEcpKX40t+WiyngdbxX3IW/PWQnCAHblI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dst1og2e; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dst1og2e" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6B1F5C433A6; Sun, 24 Mar 2024 22:57:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711321035; bh=yUS06+jBKCnlD25vjcbgsGFLnvBZQdDnVaI/PR/gXtk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dst1og2ebcPqA/E37s9NjrzsuV46tE8zY1nGulmStIgzi8yJrILX81xot5Eed5T97 hp4KgFVZglgIepLmvWtHZDkwmFNV3eGwrACbv3aAUVGic/c7oKtAB4z3lYLUbMtm4b yDUP0DhAr9TR47g89wU7BXP5OPSg188LXAWssXFJbZRdd6k1u4aws4CAC96Ong4BZW So3rcEroGgnrp+YvgbLZWySV+fp5X0de8OoHWCmaZs+4zGnTWoZtytEt5cjgBbl+Xb SR4gCAxJgO7yoksLF+2nQpMBf7TK04SK/9O7676b3bxUeTwMKizq05fkcrq/m1BJ6a zlLD4f34AwgJA== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Jeff LaBundy , Dmitry Torokhov , Sasha Levin Subject: [PATCH 6.7 598/713] Input: iqs7222 - add support for IQS7222D v1.1 and v1.2 Date: Sun, 24 Mar 2024 18:45:24 -0400 Message-ID: <20240324224720.1345309-599-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240324224720.1345309-1-sashal@kernel.org> References: <20240324224720.1345309-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jeff LaBundy [ Upstream commit 992cf65674778e22436807796b2df927de21bb75 ] The vendor has introduced two new revisions with slightly different memory maps; update the driver to support them. Fixes: dd24e202ac72 ("Input: iqs7222 - add support for Azoteq IQS7222D") Signed-off-by: Jeff LaBundy Link: https://lore.kernel.org/r/ZelTRYX3fenMQuhF@nixie71 Signed-off-by: Dmitry Torokhov Signed-off-by: Sasha Levin --- drivers/input/misc/iqs7222.c | 112 +++++++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/drivers/input/misc/iqs7222.c b/drivers/input/misc/iqs7222.c index 36aeeae776110..9ca5a743f19fe 100644 --- a/drivers/input/misc/iqs7222.c +++ b/drivers/input/misc/iqs7222.c @@ -620,6 +620,118 @@ static const struct iqs7222_dev_desc iqs7222_devs[] = =3D { }, }, }, + { + .prod_num =3D IQS7222_PROD_NUM_D, + .fw_major =3D 1, + .fw_minor =3D 2, + .touch_link =3D 1770, + .allow_offset =3D 9, + .event_offset =3D 10, + .comms_offset =3D 11, + .reg_grps =3D { + [IQS7222_REG_GRP_STAT] =3D { + .base =3D IQS7222_SYS_STATUS, + .num_row =3D 1, + .num_col =3D 7, + }, + [IQS7222_REG_GRP_CYCLE] =3D { + .base =3D 0x8000, + .num_row =3D 7, + .num_col =3D 2, + }, + [IQS7222_REG_GRP_GLBL] =3D { + .base =3D 0x8700, + .num_row =3D 1, + .num_col =3D 3, + }, + [IQS7222_REG_GRP_BTN] =3D { + .base =3D 0x9000, + .num_row =3D 14, + .num_col =3D 3, + }, + [IQS7222_REG_GRP_CHAN] =3D { + .base =3D 0xA000, + .num_row =3D 14, + .num_col =3D 4, + }, + [IQS7222_REG_GRP_FILT] =3D { + .base =3D 0xAE00, + .num_row =3D 1, + .num_col =3D 2, + }, + [IQS7222_REG_GRP_TPAD] =3D { + .base =3D 0xB000, + .num_row =3D 1, + .num_col =3D 24, + }, + [IQS7222_REG_GRP_GPIO] =3D { + .base =3D 0xC000, + .num_row =3D 3, + .num_col =3D 3, + }, + [IQS7222_REG_GRP_SYS] =3D { + .base =3D IQS7222_SYS_SETUP, + .num_row =3D 1, + .num_col =3D 12, + }, + }, + }, + { + .prod_num =3D IQS7222_PROD_NUM_D, + .fw_major =3D 1, + .fw_minor =3D 1, + .touch_link =3D 1774, + .allow_offset =3D 9, + .event_offset =3D 10, + .comms_offset =3D 11, + .reg_grps =3D { + [IQS7222_REG_GRP_STAT] =3D { + .base =3D IQS7222_SYS_STATUS, + .num_row =3D 1, + .num_col =3D 7, + }, + [IQS7222_REG_GRP_CYCLE] =3D { + .base =3D 0x8000, + .num_row =3D 7, + .num_col =3D 2, + }, + [IQS7222_REG_GRP_GLBL] =3D { + .base =3D 0x8700, + .num_row =3D 1, + .num_col =3D 3, + }, + [IQS7222_REG_GRP_BTN] =3D { + .base =3D 0x9000, + .num_row =3D 14, + .num_col =3D 3, + }, + [IQS7222_REG_GRP_CHAN] =3D { + .base =3D 0xA000, + .num_row =3D 14, + .num_col =3D 4, + }, + [IQS7222_REG_GRP_FILT] =3D { + .base =3D 0xAE00, + .num_row =3D 1, + .num_col =3D 2, + }, + [IQS7222_REG_GRP_TPAD] =3D { + .base =3D 0xB000, + .num_row =3D 1, + .num_col =3D 24, + }, + [IQS7222_REG_GRP_GPIO] =3D { + .base =3D 0xC000, + .num_row =3D 3, + .num_col =3D 3, + }, + [IQS7222_REG_GRP_SYS] =3D { + .base =3D IQS7222_SYS_SETUP, + .num_row =3D 1, + .num_col =3D 12, + }, + }, + }, { .prod_num =3D IQS7222_PROD_NUM_D, .fw_major =3D 0, --=20 2.43.0